公开(公告)号：US09196694B2

公开(公告)日：2015-11-24

申请号：US14043017

申请日：2013-10-01

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Guillaume Bouche ,  Shao Ming Koh ,  Jeremy A. Wahl ,  Andy Wei

IPC: H01L21/44 ,  H01L29/417 ,  H01L27/092

CPC classification number: H01L29/45 ,  H01L21/823814 ,  H01L27/092 ,  H01L29/41725

Abstract: Integrated circuits with dual silicide contacts and methods for fabricating integrated circuits with dual silicide contacts are provided. In an embodiment, a method for fabricating an integrated circuit includes providing a semiconductor substrate having PFET areas and NFET areas. The method selectively forms first silicide contacts from a first metal in the PFET areas. Further, the method selectively forms second silicide contacts from a second metal in the NFET areas. The second metal is different from the first metal.

Abstract translation: 提供了具有双硅化物触点的集成电路和用于制造具有双硅化物触点的集成电路的方法。 在一个实施例中，一种用于制造集成电路的方法包括提供具有PFET区域和NFET区域的半导体衬底。 该方法选择性地从PFET区域中的第一金属形成第一硅化物接触。 此外，该方法从NFET区域中的第二金属选择性地形成第二硅化物接触。 第二种金属与第一种金属不同。

公开(公告)号：US09129987B2

公开(公告)日：2015-09-08

申请号：US14163687

申请日：2014-01-24

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jing Wan ,  Jin Ping Liu ,  Guillaume Bouche ,  Andy Wei ,  Lakshmanan H. Vanamurthy ,  Cuiqin Xu ,  Sridhar Kuchibhatla ,  Rama Kambhampati ,  Xiuyu Cai

IPC: H01L29/66 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/28

CPC classification number: H01L29/66545 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/31055 ,  H01L21/31111 ,  H01L29/165 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66636 ,  H01L29/7848

Abstract: A method includes providing a gate structure having a gate, a first spacer along at least one side of the gate and an interlayer dielectric on at least one of the gate and the first spacer. The interlayer dielectric is removed to reveal the first spacer. The first spacer is removed and a second spacer is deposited on at least one side of the gate. The second spacer is formed of material having a lower dielectric constant than the first spacer.

Abstract translation: 一种方法包括提供具有栅极的栅极结构，沿栅极的至少一侧的第一间隔物，以及至少一个栅极和第一间隔物上的层间电介质。 去除层间电介质以露出第一间隔物。 去除第一间隔物并且在栅极的至少一侧上沉积第二间隔物。 第二间隔物由具有比第一间隔物低的介电常数的材料形成。

公开(公告)号：US08916928B2

公开(公告)日：2014-12-23

申请号：US14039450

申请日：2013-09-27

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Tim Baldauf ,  Andy Wei ,  Tom Herrmann ,  Stefan Flachowsky ,  Ralf Illgen

IPC: H01L29/78 ,  H01L21/8234 ,  H01L27/088

CPC classification number: H01L29/785 ,  H01L21/823431 ,  H01L27/0886

Abstract: When forming sophisticated multiple gate transistors and planar transistors in a common manufacturing sequence, the threshold voltage characteristics of the multiple gate transistors may be intentionally “degraded” by selectively incorporating a dopant species into corner areas of the semiconductor fins, thereby obtaining a superior adaptation of the threshold voltage characteristics of multiple gate transistors and planar transistors. In advantageous embodiments, the incorporation of the dopant species may be accomplished by using the hard mask, which is also used for patterning the self-aligned semiconductor fins.

Abstract translation: 当在共同的制造顺序中形成复杂的多栅极晶体管和平面晶体管时，通过选择性地将掺杂剂物质结合到半导体鳍片的角区域中，可以有意地“降低”多个栅极晶体管的阈值电压特性，从而获得 多个栅极晶体管和平面晶体管的阈值电压特性。 在有利的实施方案中，可以通过使用硬掩模来实现掺杂物种的掺入，该硬掩模也用于图案化自对准半导体鳍片。

公开(公告)号：US20140154854A1

公开(公告)日：2014-06-05

申请号：US14027837

申请日：2013-09-16

Applicant: Globalfoundries, Inc.

Inventor： Andy Wei ,  Peter Baars ,  Erik P. Geiss

IPC: H01L21/8234

CPC classification number: H01L21/823418 ,  H01L21/76224 ,  H01L21/76897 ,  H01L21/823431 ,  H01L21/823821 ,  H01L29/41783 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/7848

Abstract: Methods are provided for fabricating integrated circuits. One method includes etching a plurality of trenches into a silicon substrate and filling the trenches with an insulating material to delineate a plurality of spaced apart silicon fins. A layer of undoped silicon is epitaxially grown to form an upper, undoped region of the fins. Dummy gate structures are formed overlying and transverse to the plurality of fins and a back fill material fills between the dummy gate structures. The dummy gate structures are removed to expose a portion of the fins and a high-k dielectric material and a work function determining gate electrode material are deposited overlying the portion of the fins. The back fill material is removed to expose a second portion and metal silicide contacts are formed on the second portion. Conductive contacts are then formed to the work function determining material and to the metal silicide.

Abstract translation: 提供了用于制造集成电路的方法。 一种方法包括将多个沟槽蚀刻成硅衬底并用绝缘材料填充沟槽以描绘多个间隔开的硅片。 外延生长一层未掺杂的硅以形成翅片的上部未掺杂区域。 虚拟门结构形成为覆盖并横向于多个翅片，并且后填充材料填充在虚拟栅极结构之间。 去除虚拟栅极结构以暴露一部分散热片，并且将高k电介质材料和确定栅极电极材料的功函数沉积在鳍片的该部分上。 去除后填充材料以暴露第二部分，并且在第二部分上形成金属硅化物接触。 然后，将导电触点形成到功函数确定材料和金属硅化物。

公开(公告)号：US10181420B2

公开(公告)日：2019-01-15

申请号：US15425478

申请日：2017-02-06

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jason Eugene Stephens ,  David Michael Permana ,  Guillaume Bouche ,  Andy Wei ,  Mark Zaleski ,  Anbu Selvam K M Mahalingam ,  Craig Michael Child, Jr. ,  Roderick Alan Augur ,  Shyam Pal ,  Linus Jang ,  Xiang Hu ,  Akshey Sehgal

IPC: H01L21/768 ,  H01L21/311 ,  H01L21/027 ,  H01L23/522 ,  H01L23/528

Abstract: Semiconductor devices and methods of fabricating the semiconductor devices with chamfer-less via multi-patterning are disclosed. One method includes, for instance: obtaining an intermediate semiconductor device; performing a trench etch into a portion of the intermediate semiconductor device to form a trench pattern; depositing an etching stack; performing at least one via patterning process; and forming at least one via opening into a portion of the intermediate semiconductor device. An intermediate semiconductor device is also disclosed.

公开(公告)号：US09508850B2

公开(公告)日：2016-11-29

申请号：US15012760

申请日：2016-02-01

Applicant: GLOBALFOUNDRIES INC.

Inventor： Zhenyu Hu ,  Richard J. Carter ,  Andy Wei ,  Qi Zhang ,  Sruthi Muralidharan ,  Amy L. Child

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/06 ,  H01L29/08 ,  H01L29/161 ,  H01L29/24

CPC classification number: H01L29/7848 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/24 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/785

Abstract: Approaches for enabling uniform epitaxial (epi) growth in an epi junction area of a semiconductor device (e.g., a fin field effect transistor device) are provided. Specifically, a semiconductor device is provided including a dummy gate and a set of fin field effect transistors (FinFETs) formed over a substrate; a spacer layer formed over the dummy gate and each of the set of FinFETs; and an epi material formed within a set of recesses in the substrate, the set of recesses formed prior to removal of an epi block layer over the dummy gate.

公开(公告)号：US09455316B2

公开(公告)日：2016-09-27

申请号：US14871289

申请日：2015-09-30

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jagar Singh ,  Andy Wei ,  Mahadeva Iyer Natarajan

IPC: H01L29/06 ,  H01L27/02 ,  H01L21/306 ,  H01L21/308 ,  H01L29/417 ,  H01L29/45 ,  H01L29/861 ,  H01L29/866

CPC classification number: H01L29/0657 ,  H01L21/30604 ,  H01L21/308 ,  H01L21/3081 ,  H01L21/3086 ,  H01L27/0251 ,  H01L27/0255 ,  H01L27/0259 ,  H01L27/0296 ,  H01L29/41708 ,  H01L29/456 ,  H01L29/861 ,  H01L29/866

Abstract: Three-dimensional electrostatic discharge (ESD) semiconductor devices are fabricated together with three-dimensional non-ESD semiconductor devices. For example, an ESD diode and FinFET are fabricated on the same bulk semiconductor substrate. A spacer merger technique is used in the ESD portion of a substrate to create double-width fins on which the ESD devices can be made larger to handle more current.

公开(公告)号：US09437713B2

公开(公告)日：2016-09-06

申请号：US14181790

申请日：2014-02-17

Applicant: GLOBALFOUNDRIES INC.

Inventor： Jagar Singh ,  Andy Wei ,  Gopal Srinivasan ,  Amaury Gendron

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/308 ,  H01L29/94 ,  H01L27/06

CPC classification number: H01L29/66795 ,  H01L21/3086 ,  H01L27/0629 ,  H01L29/785 ,  H01L29/94

Abstract: Devices and methods for forming semiconductor devices with wider FinFETs for higher tunability of the varactor are provided. One method includes, for instance: obtaining an intermediate semiconductor device; applying a spacer layer over the semiconductor device; etching the semiconductor device to remove at least a portion of the spacer layer to expose the plurality of mandrels; removing the mandrels; etching the semiconductor device to remove a portion of the dielectric layer; forming at least one fin; and removing the spacer layer and the dielectric layer. One intermediate semiconductor device includes, for instance: a substrate; a dielectric layer over the substrate; a plurality of mandrels formed on the dielectric layer, the mandrels including a first set of mandrels and a second set of mandrels, wherein the first set of mandrels have a width twice as large as the second set of mandrels; and a spacer layer applied over the mandrels.

Abstract translation: 提供了用于形成具有更宽FinFET的半导体器件以用于变容二极管的较高可调性的装置和方法。 一种方法包括，例如：获得中间半导体器件; 在所述半导体器件上施加间隔层; 蚀刻半导体器件以去除间隔层的至少一部分以暴露多个心轴; 去除心轴; 蚀刻半导体器件以去除电介质层的一部分; 形成至少一个翅片; 以及去除间隔层和电介质层。 一个中间半导体器件包括例如：衬底; 介电层; 形成在所述电介质层上的多个心轴，所述心轴包括第一组心轴和第二组心轴，其中所述第一组心轴的宽度是所述第二组心轴的两倍; 以及施加在心轴上的间隔层。

公开(公告)号：US09425097B1

公开(公告)日：2016-08-23

申请号：US14699154

申请日：2015-04-29

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Guillaume Bouche ,  Andy Wei ,  Sudharshanan Raghunathan

IPC: H01L23/48 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532

CPC classification number: H01L23/528 ,  H01L21/02118 ,  H01L21/0337 ,  H01L21/31051 ,  H01L21/32139 ,  H01L21/76802 ,  H01L21/76816 ,  H01L21/76897

Abstract: A method of lithographically cutting a Mx line before the Mx line is lithographically defined by patterning and the resulting 2DSAV device are provided. Embodiments include forming an a-Si dummy metal layer over a SiO2 layer; forming a first softmask stack over the a-Si dummy metal layer; patterning a plurality of vias through the first softmask stack down to the SiO2 layer; removing the first soft mask stack; forming first and second etch stop layers over the a-Si dummy metal layer, the first etch stop layer formed in the plurality of vias; forming a-Si mandrels on the second etch stop layer; forming oxide spacers on opposite sides of each a-Si mandrel; removing the a-Si mandrels; forming a-Si dummy metal lines in the a-Si dummy metal layer below the oxide spacers; and forming a SiOC layer between the a-Si dummy metal lines.

Abstract translation: 在Mx线之前光刻地切割Mx线的方法通过图案化光刻定义，并且提供所得到的2DSAV器件。 实施例包括在SiO 2层上形成a-Si虚拟金属层; 在所述a-Si虚拟金属层上形成第一软掩模堆叠; 将通过第一软掩模堆叠的多个通孔图形化成SiO 2层; 移除第一软掩模层; 在a-Si虚拟金属层上形成第一和第二蚀刻停止层，形成在多个通孔中的第一蚀刻停止层; 在第二蚀刻停止层上形成a-Si心轴; 在每个a-Si心轴的相对侧上形成氧化物间隔物; 去除a-Si心轴; 在氧化物间隔物下面的a-Si虚拟金属层中形成a-Si虚拟金属线; 并在a-Si虚拟金属线之间形成SiOC层。

公开(公告)号：US20160163862A1

公开(公告)日：2016-06-09

申请号：US15012760

申请日：2016-02-01

Applicant: GLOBALFOUNDRIES INC.

Inventor： ZHENYU HU ,  Richard J. Carter ,  Andy Wei ,  Qi Zhang ,  Sruthi Muralidharan ,  Amy L. Child

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/161 ,  H01L29/24 ,  H01L29/66 ,  H01L29/08

CPC classification number: H01L29/7848 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/24 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/785

Abstract: Approaches for enabling uniform epitaxial (epi) growth in an epi junction area of a semiconductor device (e.g., a fin field effect transistor device) are provided. Specifically, a semiconductor device is provided including a dummy gate and a set of fin field effect transistors (FinFETs) formed over a substrate; a spacer layer formed over the dummy gate and each of the set of FinFETs; and an epi material formed within a set of recesses in the substrate, the set of recesses formed prior to removal of an epi block layer over the dummy gate.