中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

72 records (took 0.017 seconds)

    Methods of forming transistor structures including forming channel material after formation processes to prevent damage to the channel material
    33.
    发明授权
    Methods of forming transistor structures including forming channel material after formation processes to prevent damage to the channel material 有权
    形成晶体管结构的方法，包括在形成工艺之后形成沟道材料以防止损坏沟道材料

    公开(公告)号：US09570588B2

    公开(公告)日：2017-02-14

    申请号：US14883045

    申请日：2015-10-14

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Murat Kerem Akarvardar ,  Steven Bentley

    IPC: H01L29/66 ,  H01L21/306 ,  H01L21/3213

    CPC classification number: H01L29/66795 ,  H01L21/30604 ,  H01L21/32134 ,  H01L29/1054 ,  H01L29/66545 ,  H01L29/785

    Abstract: Methods for fabricating transistor structures are provided, the methods including: forming a fin structure with an upper fin portion and a lower fin portion, the upper fin portion including a sacrificial material; forming a gate structure over the fin; selectively removing the upper fin portion to form a tunnel between the gate structure and lower fin portion; and providing a channel material in the tunnel to define the channel region of the gate structure. The sacrificial material may be a material that can be selectively etched without etching the material of the lower fin portion. The channel material may further be provided to form source and drain regions of the transistor structure, which may result in a junctionless FinFET structure.

    Abstract translation: 提供了制造晶体管结构的方法，所述方法包括：形成具有上翅片部分和下翅片部分的翅片结构，所述上翅片部分包括牺牲材料; 在翅片上形成栅极结构; 选择性地去除所述上翅片部分以在所述门结构和所述下翅片部分之间形成隧道; 以及在隧道中提供通道材料以限定栅极结构的沟道区域。 牺牲材料可以是可以选择性地蚀刻而不蚀刻下部翅片部分的材料的材料。 可以进一步提供沟道材料以形成晶体管结构的源极和漏极区域，这可能导致无连接的FinFET结构。

    FinFET device including a uniform silicon alloy fin
    34.
    发明授权
    FinFET device including a uniform silicon alloy fin 有权
    FinFET器件包括均匀的硅合金翅片

    公开(公告)号：US09406803B2

    公开(公告)日：2016-08-02

    申请号：US14676239

    申请日：2015-04-01

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Ajey Poovannummoottil Jacob ,  Jody A. Fronheiser ,  Murat Kerem Akarvardar ,  Steven Bentley

    IPC: H01L21/326 ,  H01L21/8234 ,  H01L29/78 ,  H01L27/088 ,  H01L29/06 ,  H01L29/161 ,  H01L21/02 ,  H01L21/324

    CPC classification number: H01L29/7851 ,  H01L21/02532 ,  H01L21/02664 ,  H01L21/18 ,  H01L29/161

    Abstract: A method includes forming at least one fin on a semiconductor substrate. A silicon alloy material is formed on the fin and on exposed surface portions of the substrate. A thermal process is performed to define a silicon alloy fin from the silicon alloy material and the fin and to define silicon alloy surface portions from the silicon alloy material and the exposed surface portions of the substrate. A semiconductor device includes a substrate, a fin defined on the substrate, the fin comprising a silicon alloy and having a substantially vertical sidewall, and silicon alloy surface portions on the substrate adjacent the fin.

    Abstract translation: 一种方法包括在半导体衬底上形成至少一个翅片。 在所述散热片和所述基板的暴露的表面部分上形成硅合金材料。 执行热处理以从硅合金材料和翅片限定硅合金翅片，并且从硅合金材料和基底的暴露表面部分限定硅合金表面部分。 半导体器件包括衬底，限定在衬底上的鳍，鳍包括硅合金并且具有基本上垂直的侧壁，以及衬底上的与硅相邻的硅合金表面部分。

    METHODS OF FORMING SUBSTRATES COMPRISED OF DIFFERENT SEMICONDUCTOR MATERIALS AND THE RESULTING DEVICE
    35.
    发明申请
    METHODS OF FORMING SUBSTRATES COMPRISED OF DIFFERENT SEMICONDUCTOR MATERIALS AND THE RESULTING DEVICE 有权
    形成由不同的半导体材料和结果器件组成的衬底的方法

    公开(公告)号：US20140217467A1

    公开(公告)日：2014-08-07

    申请号：US13758225

    申请日：2013-02-04

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Bartlomiej Jan Pawlak ,  Steven Bentley ,  Ajey Jacob

    IPC: H01L21/02 ,  H01L29/12

    CPC classification number: H01L29/12 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0924 ,  H01L27/1207 ,  H01L27/1211

    Abstract: Obtaining a structure comprised of first and second layers of a first semiconductor materials and a strain relief buffer (SRB) layer between the first and second layers, forming a sidewall spacer on the sidewalls of an opening in the second layer, and forming a third semiconductor material in the opening, wherein the first, second and third semiconductor materials are different. A device includes first and second layers of first and second semiconductor materials and an SRB layer positioned above the first layer. The second layer is positioned above a first portion of the SRB layer, a region of a third semiconductor material is in an opening in the second layer and above a second portion of the SRB layer, and an insulating material is positioned between the region comprised of the third semiconductor material and the second layer.

    Abstract translation: 在第一和第二层之间获得由第一半导体材料的第一和第二层和应变释放缓冲层（SRB）层组成的结构，在第二层的开口的侧壁上形成侧壁间隔物，并形成第三半导体 所述开口中的材料，其中所述第一，第二和第三半导体材料是不同的。 一种器件包括第一和第二层第一和第二半导体材料以及位于第一层之上的SRB层。 第二层位于SRB层的第一部分之上，第三半导体材料的区域位于第二层的开口中并且位于SRB层的第二部分之上，并且绝缘材料位于由 第三半导体材料和第二层。

    Method of forming vertical field effect transistors with self-aligned gates and gate extensions and the resulting structure
    38.
    发明授权
    Method of forming vertical field effect transistors with self-aligned gates and gate extensions and the resulting structure 有权

    公开(公告)号：US10283621B2

    公开(公告)日：2019-05-07

    申请号：US15709500

    申请日：2017-09-20

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Ruilong Xie ,  Lars Liebmann ,  Hui Zang ,  Steven Bentley

    IPC: H01L29/66

    Abstract: Disclosed is a method of forming an integrated circuit (IC) that incorporates multiple vertical field effect transistors (VFETs) (e.g., in a VFET array). In the method, self-aligned gates for each pair of VFETs and a self-aligned gate extension for contacting those self-aligned gates are essentially simultaneously formed such that the gates wrap around a pair of semiconductor fins, which are in end-to-end alignment, and such that the gate extension fills the space between adjacent ends of those semiconductor fins. By forming self-aligned gates and a self-aligned gate extension for a pair of VFETs, the method avoids the need for lithographically patterning extension cut isolation regions between adjacent pairs of VFETs in a VFET array. Thus, the method enables implementation of VFET array designs with a reduced fin pitch without incurring defects caused, for example, by overlay errors. Also disclosed herein is an IC formed according to the method.

    Insulated epitaxial structures in nanosheet complementary field effect transistors
    40.
    发明授权
    Insulated epitaxial structures in nanosheet complementary field effect transistors 有权

    公开(公告)号：US10256158B1

    公开(公告)日：2019-04-09

    申请号：US15820477

    申请日：2017-11-22

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Julien Frougier ,  Ruilong Xie ,  Steven Bentley ,  Puneet H. Suvarna

    IPC: H01L21/8238 ,  H01L29/06 ,  H01L29/167 ,  H01L29/423 ,  H01L27/092 ,  H01L21/822 ,  H01L29/161 ,  H01L21/84

    Abstract: Integrated circuit structures include isolation elements extending into a substrate, and source/drain regions of a first transistor contacting the isolation elements. The isolation elements extend from the substrate to the source/drain regions of the first transistor. Isolation layers contact the source/drain regions of the first transistor, and source/drain regions of a second transistor also contact the isolation layers. Thus, the isolation layers are between the source/drain regions of the first transistor and the source/drain regions of the second transistor. Channel regions of the first transistor contact and extend between the source/drain regions of the first transistor, and channel regions of the second transistor contact and extend between the source/drain regions of the second transistor. A gate conductor surrounds sides of the channel region of the first transistor and the channel region of the second transistor.

Patent Agency Ranking