公开(公告)号：US20180190807A1

公开(公告)日：2018-07-05

申请号：US15567579

申请日：2015-05-19

Applicant: Intel Corporation

Inventor： Marko RADOSAVLJEVIC ,  Sansaptak DASGUPTA ,  Sanaz K. GARDNER ,  Seung Hoon SUNG ,  Han Wui THEN ,  Robert S. CHAU

IPC: H01L29/778 ,  H01L29/08 ,  H01L29/20 ,  H01L29/205 ,  H01L21/02 ,  H01L21/8258

CPC classification number: H01L29/7786 ,  H01L21/02381 ,  H01L21/02488 ,  H01L21/02513 ,  H01L21/0254 ,  H01L21/02647 ,  H01L21/823431 ,  H01L21/8252 ,  H01L21/8258 ,  H01L29/0657 ,  H01L29/0847 ,  H01L29/0891 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/66462

Abstract: Semiconductor devices including an elevated or raised doped crystalline structure extending from a device layer are described. In embodiments, III-N transistors include raised crystalline n+ doped source/drain structures on either side of a gate stack. In embodiments, an amorphous material is employed to limit growth of polycrystalline source/drain material, allowing a high quality source/drain doped crystal to grow from an undamaged region and laterally expand to form a low resistance interface with a two-degree electron gas (2DEG) formed within the device layer. In some embodiments, regions of damaged GaN that may spawn competitive polycrystalline overgrowths are covered with the amorphous material prior to commencing raised source/drain growth.

公开(公告)号：US20180145164A1

公开(公告)日：2018-05-24

申请号：US15574817

申请日：2015-06-26

Applicant: Intel Corporation

Inventor： Sansaptak DASGUPTA ,  Han Wui THEN ,  Marko RADOSAVLJEVIC ,  Sanaz K. GARDNER ,  Seung Hoon SUNG ,  Robert S. CHAU

IPC: H01L29/778 ,  H01L29/66 ,  H01L21/02 ,  H01L29/20 ,  H01L21/04

CPC classification number: H01L29/7786 ,  H01L21/02381 ,  H01L21/02439 ,  H01L21/02458 ,  H01L21/0254 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/0445 ,  H01L21/8258 ,  H01L27/085 ,  H01L29/0657 ,  H01L29/2003 ,  H01L29/66462 ,  H01L29/785

Abstract: Crystalline heterostructures including an elevated crystalline structure extending from one or more trenches in a trench layer disposed over a crystalline substrate are described. In some embodiments, an interfacial layer is disposed over a silicon substrate surface. The interfacial layer facilitates growth of the elevated structure from a bottom of the trench at growth temperatures that may otherwise degrade the substrate surface and induce more defects in the elevated structure. The trench layer may be disposed over the interfacial layer with a trench bottom exposing a portion of the interfacial layer. Arbitrarily large merged crystal structures having low defect density surfaces may be overgrown from the trenches. Devices, such as III-N transistors, may be further formed on the raised crystalline structures while silicon-based devices (e.g., transistors) may be formed in other regions of the silicon substrate.

公开(公告)号：US20170263708A1

公开(公告)日：2017-09-14

申请号：US15605795

申请日：2017-05-25

Applicant: Intel Corporation

Inventor： Han Wui THEN ,  Robert CHAU ,  Benjamin CHU-KUNG ,  Gilbert DEWEY ,  Jack KAVALIEROS ,  Matthew METZ ,  Niloy MUKHERJEE ,  Ravi PILLARISETTY ,  Marko RADOSAVLJEVIC

IPC: H01L29/06 ,  B82Y10/00 ,  G05F3/02 ,  H01L21/02 ,  H01L21/225 ,  H01L21/283 ,  H01L21/306 ,  H01L21/31 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/324 ,  H01L29/04 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786 ,  H01L29/20

CPC classification number: H01L29/0673 ,  B82Y10/00 ,  G05F3/02 ,  H01L21/02603 ,  H01L21/02636 ,  H01L21/225 ,  H01L21/283 ,  H01L21/30604 ,  H01L21/31 ,  H01L21/31116 ,  H01L21/32133 ,  H01L21/324 ,  H01L29/04 ,  H01L29/0676 ,  H01L29/068 ,  H01L29/2003 ,  H01L29/41725 ,  H01L29/42356 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66462 ,  H01L29/66469 ,  H01L29/775 ,  H01L29/78696

Abstract: Transistors suitable for high voltage and high frequency operation. A nanowire is disposed vertically or horizontally on a substrate. A longitudinal length of the nanowire is defined into a channel region of a first semiconductor material, a source region electrically coupled with a first end of the channel region, a drain region electrically coupled with a second end of the channel region, and an extrinsic drain region disposed between the channel region and drain region. The extrinsic drain region has a wider bandgap than that of the first semiconductor. A gate stack including a gate conductor and a gate insulator coaxially wraps completely around the channel region, drain and source contacts similarly coaxially wrap completely around the drain and source regions.

公开(公告)号：US20160365341A1

公开(公告)日：2016-12-15

申请号：US14738799

申请日：2015-06-12

Applicant: Intel Corporation

Inventor： Han Wui THEN ,  Sansaptak Dasgupta ,  Gerhard Schrom ,  Valluri R. Rao ,  Robert S. Chau

IPC: H01L27/06 ,  H01L29/04 ,  H01L29/20 ,  H01L29/10 ,  H01L29/205 ,  H01L29/94 ,  H01L29/778

CPC classification number: H01L27/0629 ,  H01L21/8252 ,  H01L21/8258 ,  H01L27/0605 ,  H01L29/04 ,  H01L29/045 ,  H01L29/0657 ,  H01L29/1095 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/66181 ,  H01L29/7787 ,  H01L29/94 ,  H01L29/945

Abstract: III-N high voltage MOS capacitors and System on Chip (SoC) solutions integrating at least one III-N MOS capacitor capable of high breakdown voltages (BV) to implement high voltage and/or high power circuits. Breakdown voltages over 4V may be achieved avoiding any need to series couple capacitors in an RFIC and/or PMIC. In embodiments, depletion mode III-N capacitors including a GaN layer in which a two dimensional electron gas (2DEG) is formed at threshold voltages below 0V are monolithically integrated with group IV transistor architectures, such as planar and non-planar silicon CMOS transistor technologies. In embodiments, silicon substrates are etched to provide a (111) epitaxial growth surface over which a GaN layer and III-N barrier layer are formed. In embodiments, a high-K dielectric layer is deposited, and capacitor terminal contacts are made to the 2DEG and over the dielectric layer.

Abstract translation: 集成了至少一个具有高击穿电压（BV）的III-N MOS电容器的III-N高压MOS电容器和片上系统（SoC）解决方案，以实现高压和/或高功率电路。 可以实现超过4V的击穿电压，避免了RFIC和/或PMIC中的串联耦合电容的任何需要。 在实施例中，包括其中在低于0V的阈值电压下形成二维电子气（2DEG）的GaN层的耗尽型III-N电容器与IV族晶体管架构单片集成，例如平面和非平面硅CMOS晶体管技术 。 在实施例中，蚀刻硅衬底以提供形成GaN层和III-N势垒层的（111）外延生长表面。 在实施例中，沉积高K电介质层，并且电容器端子触点被制成2DEG并且在电介质层上。

公开(公告)号：US20160291641A1

公开(公告)日：2016-10-06

申请号：US15037639

申请日：2013-12-26

Applicant: INTEL CORPORATION

Inventor： Brian S. DOYLE ,  Han Wui THEN ,  Valluri RAO ,  Niloy MUKHERJEE ,  Robert S. CHAU ,  Ravi PILLARISETTY

IPC: G06F1/16 ,  H04M1/02 ,  H05K3/30 ,  H05K1/02 ,  H05K3/46

CPC classification number: G06F1/1652 ,  G06F1/1626 ,  G06F1/1643 ,  G06F1/1656 ,  G06F2203/04102 ,  G06F2203/04103 ,  G09F9/00 ,  G09G3/2092 ,  G09G2300/0426 ,  G09G2380/02 ,  H01L27/1225 ,  H01L27/1259 ,  H01L27/1266 ,  H04M1/0268 ,  H05K1/028 ,  H05K1/0296 ,  H05K3/30 ,  H05K3/4682

Abstract: A flexible electronic computing device is described. In one embodiment, a flexible display is formed on a flexible substrate. A plurality of electronic components are attached to the flexible substrate. A plurality of conductive signal lines are formed on the flexible substrate, the signal lines electrically coupling the electronic components to the flexible display.

Abstract translation: 描述了一种灵活的电子计算设备。 在一个实施例中，柔性显示器形成在柔性基板上。 多个电子部件附接到柔性基板。 多个导电信号线形成在柔性基板上，信号线将电子部件电耦合到柔性显示器。

公开(公告)号：US20160181085A1

公开(公告)日：2016-06-23

申请号：US14908112

申请日：2013-09-27

Applicant: INTEL CORPORATION

Inventor： Sansaptak DASGUPTA ,  Han Wui THEN ,  Seung Hoon SUNG ,  Sanaz K. GARDNER ,  Marko RADOSAVLJEVIC ,  Benjamin CHU-KUNG ,  Robert S. CHAU

IPC: H01L21/02 ,  H01L29/20 ,  H01L29/205 ,  H01L29/778

CPC classification number: H01L21/0243 ,  H01L21/02381 ,  H01L21/02433 ,  H01L21/02458 ,  H01L21/02488 ,  H01L21/02505 ,  H01L21/0254 ,  H01L21/02639 ,  H01L21/02647 ,  H01L21/8258 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/7787

Abstract: An insulating layer is conformally deposited on a plurality of mesa structures in a trench on a substrate. The insulating layer fills a space outside the mesa structures. A nucleation layer is deposited on the mesa structures. A III-V material layer is deposited on the nucleation layer. The III-V material layer is laterally grown over the insulating layer.

Abstract translation: 绝缘层被共形沉积在衬底上的沟槽中的多个台面结构上。 绝缘层填充台面结构外部的空间。 成核层沉积在台面结构上。 III-V材料层沉积在成核层上。 在绝缘层上横向生长III-V材料层。

公开(公告)号：US20240224504A1

公开(公告)日：2024-07-04

申请号：US18089957

申请日：2022-12-28

Applicant: Intel Corporation

Inventor： Abhishek Anil SHARMA ,  Han Wui THEN ,  Pushkar RANADE ,  Wilfred GOMES ,  Sagar SUTHRAM ,  Tahir GHANI ,  Anand S. MURTHY

IPC: H10B12/00

CPC classification number: H01L27/1082 ,  H01L27/10873 ,  H01L29/1608

Abstract: Embodiments described herein may be related to apparatuses, processes, systems, and/or techniques for fabricating semiconductor packages that include DRAM using wide band gap materials, such as SiC or GaN to reduce transistor leakage. In addition, transistors may be fabricated adding one or more extra layers between a source and a drain of a transistor and the contact of the source of the drain to increase the effective electrical gate length of the transistor to further reduce leakage. In addition, for these transistors, a thickness of the body below the gate may be made narrow to improve gate control. Other embodiments may be described and/or claimed.

公开(公告)号：US20240222469A1

公开(公告)日：2024-07-04

申请号：US18089966

申请日：2022-12-28

Applicant: Intel Corporation

Inventor： Abhishek Anil SHARMA ,  Han Wui THEN ,  Wilfred GOMES ,  Tahir GHANI ,  Anand S. MURTHY ,  Sagar SUTHRAM ,  Pushkar RANADE

IPC: H01L29/66 ,  H01L29/16 ,  H01L29/20

CPC classification number: H01L29/66462 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/66893

Abstract: Embodiments described herein may be related to apparatuses, processes, systems, and/or techniques for fabricating semiconductor packages that use high voltage transistors within a SiC layer that are coupled with one or more transistors in one or more other layers in a cascode format in order to switch the high voltage transistors in the SiC layer using low voltages. Other embodiments may be described and/or claimed.

公开(公告)号：US20240222440A1

公开(公告)日：2024-07-04

申请号：US18089919

申请日：2022-12-28

Applicant: Intel Corporation

Inventor： Samuel James BADER ,  Han Wui THEN ,  Ibrahim BAN ,  Heli Chetanbhai VORA ,  Marko RADOSAVLJEVIC

IPC: H01L29/267 ,  H01L21/02 ,  H01L21/18 ,  H01L21/3205 ,  H01L29/06 ,  H01L29/10 ,  H01L29/423 ,  H01L29/66 ,  H01L29/778 ,  H01L29/78

CPC classification number: H01L29/267 ,  H01L21/0254 ,  H01L21/185 ,  H01L21/32051 ,  H01L29/0607 ,  H01L29/1033 ,  H01L29/42356 ,  H01L29/42392 ,  H01L29/66522 ,  H01L29/7786 ,  H01L29/78

Abstract: Embodiments described herein may be related to apparatuses, processes, systems, and/or techniques for using layer transfer techniques to bond a silicon layer with a GaN layer, where the silicon layer includes a first portion of a device, for example a transistor, and the GaN layer includes a second portion of the device. Other embodiments may be described and/or claimed.

公开(公告)号：US20240222228A1

公开(公告)日：2024-07-04

申请号：US18089931

申请日：2022-12-28

Applicant: Intel Corporation

Inventor： Abhishek Anil SHARMA ,  Han Wui THEN ,  Wilfred GOMES ,  Anand S. MURTHY ,  Tahir GHANI ,  Sagar SUTHRAM ,  Pushkar RANADE

IPC: H01L23/48 ,  H01L21/02 ,  H01L23/00 ,  H01L23/498 ,  H01L23/522 ,  H01L25/065 ,  H01L27/088

CPC classification number: H01L23/481 ,  H01L21/02529 ,  H01L21/0254 ,  H01L21/0262 ,  H01L23/49827 ,  H01L23/5226 ,  H01L24/13 ,  H01L25/0657 ,  H01L27/088 ,  H01L2224/13022 ,  H01L2224/13025 ,  H01L2924/05032 ,  H01L2924/10272 ,  H01L2924/1033 ,  H01L2924/13091 ,  H01L2924/1431 ,  H01L2924/1436

Abstract: Embodiments described herein may be related to apparatuses, processes, systems, and/or techniques for semiconductor packages that use devices within an SiC layer coupled with devices within a GaN layer proximate to the SiC to convert a high voltage source to the package, e.g. greater than 1 kV, to 1-1.8 V used by components within the package. The devices may be transistors. The voltage conversion will allow increased power to be supplied to the package. Other embodiments may be described and/or claimed.