公开(公告)号：US08928086B2

公开(公告)日：2015-01-06

申请号：US13737089

申请日：2013-01-09

Applicant: International Business Machines Corporation

Inventor： Henry K. Utomo ,  Kangguo Cheng ,  Ramachandra Divakaruni ,  Dechao Guo ,  Myung-Hee Na ,  Ravikumar Ramachandran ,  Kern Rim ,  Huiling Shang

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L29/7855 ,  H01L21/823431 ,  H01L29/0847 ,  H01L29/1054 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

Abstract: A fin structure includes an optional doped well, a disposable single crystalline semiconductor material portion, and a top semiconductor portion formed on a substrate. A disposable gate structure straddling the fin structure is formed, and end portions of the fin structure are removed to form end cavities. Doped semiconductor material portions are formed on sides of a stack of the disposable single crystalline semiconductor material portion and a channel region including the top semiconductor portion. The disposable single crystalline semiconductor material portion may be replaced with a dielectric material portion after removal of the disposable gate structure or after formation of the stack. The gate cavity is filled with a gate dielectric and a gate electrode. The channel region is stressed by the doped semiconductor material portions, and is electrically isolated from the substrate by the dielectric material portion.

公开(公告)号：US10347752B2

公开(公告)日：2019-07-09

申请号：US15866676

申请日：2018-01-10

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Kangguo Cheng ,  Bruce B. Doris ,  Ali Khakifirooz ,  Darsen D. Lu ,  Alexander Reznicek ,  Kern Rim

IPC: H01L27/092 ,  H01L29/66 ,  H01L29/165 ,  H01L21/8238 ,  H01L21/84 ,  H01L29/78 ,  H01L21/02 ,  H01L21/033 ,  H01L21/32 ,  H01L21/324 ,  H01L29/10 ,  H01L29/161

Abstract: A method of introducing strain in a channel region of a FinFET device includes forming a fin structure on a substrate, the fin structure having a lower portion comprising a sacrificial layer and an upper portion comprising a strained semiconductor layer; and removing a portion of the sacrificial layer corresponding to a channel region of the FinFET device so as to release the upper portion of the fin structure from the substrate in the channel region.

公开(公告)号：US20180122944A1

公开(公告)日：2018-05-03

申请号：US15800740

申请日：2017-11-01

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Kangguo Cheng ,  Bruce B. Doris ,  Darsen D. Lu ,  Ali Khakifirooz ,  Kern Rim

IPC: H01L29/78 ,  H01L21/02 ,  H01L29/66 ,  H01L29/10 ,  H01L29/06 ,  H01L21/762 ,  H01L21/324 ,  H01L21/311 ,  H01L21/3105 ,  H01L21/308 ,  H01L21/306

CPC classification number: H01L29/7846 ,  H01L21/02236 ,  H01L21/30604 ,  H01L21/3086 ,  H01L21/31051 ,  H01L21/311 ,  H01L21/31111 ,  H01L21/324 ,  H01L21/76224 ,  H01L29/0653 ,  H01L29/1054 ,  H01L29/6653 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851

Abstract: A method of forming a fin structure that includes forming a plurality of fin structures from a bulk semiconductor substrate and forming a dielectric spacer on a sidewall of each fin structure in the plurality of fin structure. A semiconductor spacer is formed on a sidewall of the dielectric spacer. A dielectric fill is formed in the space between the adjacent fin structures. The semiconductor spacer and a portion of the fin structures that is present below a lower surface of the dielectric spacer are oxidized. Oxidizing a base portion of the fin structures produces a first strain and oxidizing the semiconductor spacer produces a second strain that is opposite the first strain.

公开(公告)号：US09911663B2

公开(公告)日：2018-03-06

申请号：US15423956

申请日：2017-02-03

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Kern Rim ,  Junli Wang

IPC: H01L21/84 ,  H01L21/308 ,  H01L27/12 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78 ,  H01L21/3065 ,  H01L21/02

CPC classification number: H01L29/0649 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/02189 ,  H01L21/02192 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/3081 ,  H01L21/3085 ,  H01L21/845 ,  H01L23/291 ,  H01L27/1211 ,  H01L29/66795 ,  H01L29/66818 ,  H01L29/785 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for preventing damage to the insulator layer of a semiconductor device during creation of fin field effect transistor (FinFET) includes obtaining a material stack having an active semiconductor layer, an insulator layer, and an etch stop layer between the active semiconductor layer and the insulator layer; forming a fin-array from the active semiconductor layer; patterning the fin-array; and fabricating a FinFET device from the patterned fin-array; where the etch stop layer is resistant to processes the etch stop layer is exposed to during the forming, patterning, and fabricating operations, such that the etch stop layer and the insulator layer are not damaged during the forming, patterning, and fabricating operations.

公开(公告)号：US09741722B2

公开(公告)日：2017-08-22

申请号：US14874389

申请日：2015-10-03

Applicant: International Business Machines Corporation

Inventor： John E. Barth, Jr. ,  Kangguo Cheng ,  Bruce B. Doris ,  Herbert L. Ho ,  Ali Khakifirooz ,  Babar A. Khan ,  Shom Ponoth ,  Kern Rim ,  Kehan Tian ,  Reinaldo A. Vega

IPC: H01L21/283 ,  H01L21/762 ,  H01L27/108 ,  H01L29/06 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78 ,  H01L29/94

CPC classification number: H01L27/10879 ,  H01L21/283 ,  H01L21/76224 ,  H01L27/10826 ,  H01L27/10829 ,  H01L27/10867 ,  H01L27/1087 ,  H01L29/0653 ,  H01L29/41783 ,  H01L29/41791 ,  H01L29/66181 ,  H01L29/6681 ,  H01L29/785 ,  H01L29/945

Abstract: Trench capacitors can be formed between lengthwise sidewalls of semiconductor fins, and source and drain regions of access transistors are formed in the semiconductor fins. A dummy gate structure is formed between end walls of a neighboring pair of semiconductor fins, and limits the lateral extent of raised source and drain regions that are formed by selective epitaxy. The dummy gate structure prevents electrical shorts between neighboring semiconductor fins. Gate spacers can be formed around gate structures and the dummy gate structures. The dummy gate structures can be replaced with dummy replacement gate structures or dielectric material portions, or can remain the same without substitution of any material. The dummy gate structures may consist of at least one dielectric material, or may include electrically floating conductive material portions.

公开(公告)号：US20170170323A1

公开(公告)日：2017-06-15

申请号：US15336654

申请日：2016-10-27

Applicant: International Business Machines Corporation

Inventor： Kangguo Cheng ,  Ramachandra Divakaruni ,  Johnathan E. Faltermeier ,  Edward J. Nowak ,  Kern Rim

IPC: H01L29/78 ,  H01L21/762 ,  H01L29/66 ,  H01L29/06 ,  H01L21/306

CPC classification number: H01L21/7624 ,  H01L21/02247 ,  H01L21/02252 ,  H01L21/02255 ,  H01L21/02532 ,  H01L21/0254 ,  H01L21/30604 ,  H01L21/31105 ,  H01L21/762 ,  H01L21/76202 ,  H01L29/66795 ,  H01L29/7848 ,  H01L2029/7857

Abstract: One embodiment provides a method comprising etching a fin of a fin-shaped field effect transistor (FinFET) to form a reduced fin, and laterally etching the reduced fin to form a fin channel including a first fin channel sidewall and a second fin channel sidewall opposing the first fin channel sidewall. The method further comprises forming a first thin dielectric tunnel and a second thin dielectric tunnel on the first fin channel sidewall and the second fin channel sidewall, respectively. Each thin dielectric tunnel prevents lateral epitaxial crystal growth on the fin channel. The method further comprises etching an insulator layer disposed between the fin channel and a substrate of the FinFET to expose portions of a substrate surface of the substrate. A source epitaxy and a drain epitaxy are formed from vertical epitaxial crystal growth on the exposed portions of the substrate surface after epitaxial deposition.

公开(公告)号：US09673083B2

公开(公告)日：2017-06-06

申请号：US14608729

申请日：2015-01-29

Applicant: GLOBALFOUNDRIES Inc. ,  International Business Machines Corporation

Inventor： Ajey Poovannummoottil Jacob ,  Bruce Doris ,  Kangguo Cheng ,  Ali Khakifirooz ,  Kern Rim

IPC: H01L21/76 ,  H01L21/762 ,  H01L29/66 ,  H01L21/265 ,  H01L21/3115 ,  H01L21/02 ,  H01L21/308

CPC classification number: H01L21/76213 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/26506 ,  H01L21/3083 ,  H01L21/31155 ,  H01L21/76224 ,  H01L29/66795

Abstract: One illustrative method disclosed herein includes, among other things, forming a fin in a semiconductor substrate, the fin having a lower first section that contains an oxidation-retarding implant region and an upper second section that is substantially free of the oxidation-retarding implant region, forming a sidewall spacer on opposite sides of the upper portion of the fin, forming a first layer of insulating material adjacent the sidewall spacers and the upper second section of the lower portion of the fin, and, with the first layer of insulating material in position, performing a thermal anneal process to convert the portion of the upper second section of the fin that is in contact with the first layer of insulating material into an oxide fin isolation region positioned under the fin above the lower first section of the fin.

公开(公告)号：US20170148688A1

公开(公告)日：2017-05-25

申请号：US15423956

申请日：2017-02-03

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Kern Rim ,  Junli Wang

IPC: H01L21/84 ,  H01L27/12 ,  H01L21/02 ,  H01L29/66 ,  H01L29/78 ,  H01L21/3065 ,  H01L21/308 ,  H01L29/06

CPC classification number: H01L29/0649 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/02189 ,  H01L21/02192 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/3081 ,  H01L21/3085 ,  H01L21/845 ,  H01L23/291 ,  H01L27/1211 ,  H01L29/66795 ,  H01L29/66818 ,  H01L29/785 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for preventing damage to the insulator layer of a semiconductor device during creation of fin field effect transistor (FinFET) includes obtaining a material stack having an active semiconductor layer, an insulator layer, and an etch stop layer between the active semiconductor layer and the insulator layer; forming a fin-array from the active semiconductor layer; patterning the fin-array; and fabricating a FinFET device from the patterned fin-array; where the etch stop layer is resistant to processes the etch stop layer is exposed to during the forming, patterning, and fabricating operations, such that the etch stop layer and the insulator layer are not damaged during the forming, patterning, and fabricating operations.

公开(公告)号：US20170125447A1

公开(公告)日：2017-05-04

申请号：US15407992

申请日：2017-01-17

Applicant: International Business Machines Corporation

Inventor： Kangguo Cheng ,  Bruce B. Doris ,  Ali Khakifirooz ,  Darsen D. Lu ,  Alexander Reznicek ,  Kern Rim

IPC: H01L27/12 ,  H01L27/092 ,  H01L29/10 ,  H01L29/165 ,  H01L21/324 ,  H01L21/84 ,  H01L21/02 ,  H01L21/308 ,  H01L21/311 ,  H01L21/32 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L27/1211 ,  H01L21/02532 ,  H01L21/02636 ,  H01L21/18 ,  H01L21/30604 ,  H01L21/308 ,  H01L21/31116 ,  H01L21/32 ,  H01L21/324 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0924 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/66795 ,  H01L29/7842 ,  H01L29/7845 ,  H01L29/785

Abstract: A method of forming a semiconductor structure that includes a tensily strained silicon fin extending upwards from a first portion of a substrate and in an nFET device region, and a SiGe fin structure extending upwards from a second portion of the substrate and in a pFET device region. In accordance with the present application, the SiGe fin structure comprises, from bottom to top, a lower SiGe fin that is relaxed and an upper SiGe fin, wherein the upper SiGe fin is compressively strained and has a germanium content that is greater than a germanium content of the lower SiGe fin.

公开(公告)号：US09634090B2

公开(公告)日：2017-04-25

申请号：US15142145

申请日：2016-04-29

Applicant: International Business Machines Corporation

Inventor： Kern Rim ,  Junli Wang

IPC: H01L29/06 ,  H01L21/308 ,  H01L23/29 ,  H01L21/84 ,  H01L29/66 ,  H01L29/78 ,  H01L27/12

CPC classification number: H01L29/0649 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/02189 ,  H01L21/02192 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/3081 ,  H01L21/3085 ,  H01L21/845 ,  H01L23/291 ,  H01L27/1211 ,  H01L29/66795 ,  H01L29/66818 ,  H01L29/785 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for preventing damage to the insulator layer of a semiconductor device during creation of fin field effect transistor (FinFET) includes obtaining a material stack having an active semiconductor layer, an insulator layer, and an etch stop layer between the active semiconductor layer and the insulator layer; forming a fin-array from the active semiconductor layer; patterning the fin-array; and fabricating a FinFET device from the patterned fin-array; where the etch stop layer is resistant to processes the etch stop layer is exposed to during the forming, patterning, and fabricating operations, such that the etch stop layer and the insulator layer are not damaged during the forming, patterning, and fabricating operations.