公开(公告)号：US09911597B2

公开(公告)日：2018-03-06

申请号：US15595503

申请日：2017-05-15

Applicant: International Business Machines Corporation

Inventor： Takashi Ando ,  Eduard A. Cartier ,  Michael P. Chudzik ,  Aritra Dasgupta ,  Herbert L. Ho ,  Donghun Kang ,  Rishikesh Krishnan ,  Vijay Narayanan ,  Kern Rim

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/322 ,  H01L21/20 ,  H01G4/005 ,  H01L27/108 ,  H01L49/02

CPC classification number: H01L21/02365 ,  H01G4/005 ,  H01L21/02178 ,  H01L21/02617 ,  H01L21/20 ,  H01L21/3221 ,  H01L23/26 ,  H01L27/10861 ,  H01L27/1087 ,  H01L28/60 ,  H01L28/90 ,  H01L29/66181 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method including forming an oxygen gettering layer on one side of an insulating layer of a deep trench capacitor between the insulating layer and a substrate, the oxygen gettering layer including an aluminum containing compound, and depositing an inner electrode on top of the insulating layer, the inner electrode including a metal.

公开(公告)号：US09312364B2

公开(公告)日：2016-04-12

申请号：US14287761

申请日：2014-05-27

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Eric C. Harley ,  Judson R. Holt ,  Yue Ke ,  Rishikesh Krishnan ,  Keith H. Tabakman ,  Henry K. Utomo

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/06

CPC classification number: H01L29/7848 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823878 ,  H01L27/0924 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/785

Abstract: A method forming a semiconductor device that in one embodiment includes forming a gate structure on a channel region of fin structures, and forming a flowable dielectric material on a source region portion and a drain region portion of the fin structures. The flowable dielectric material is present at least between adjacent fin structures of the plurality of fin structures filling a space between the adjacent fin structures. An upper surface of the source region portion and the drain region portion of fin structures is exposed. An epitaxial semiconductor material is formed on the upper surface of the source region portion and the drain region portion of the fin structures.

Abstract translation: 一种形成半导体器件的方法，其在一个实施例中包括在鳍结构的沟道区上形成栅极结构，并在鳍结构的源极区域和漏极区部分上形成可流动的电介质材料。 可流动介电材料至少存在于填充相邻翅片结构之间的空间的多个翅片结构的相邻翅片结构之间。 源区域部分的上表面和鳍结构的漏区部分被暴露。 外延半导体材料形成在鳍片结构的源极区域部分和漏极区域部分的上表面上。

公开(公告)号：US20150279925A1

公开(公告)日：2015-10-01

申请号：US14242092

申请日：2014-04-01

Applicant: International Business Machines Corporation

Inventor： Nicolas L. Breil ,  Ricardo A. Donaton ,  Dong Hun Kang ,  Herbert L. Ho ,  Rishikesh Krishnan

IPC: H01L49/02

CPC classification number: H01L28/91 ,  H01L21/283 ,  H01L27/1082 ,  H01L27/10832 ,  H01L27/10858 ,  H01L27/10867 ,  H01L27/1087 ,  H01L28/90

Abstract: Method of forming a deep trench capacitor are provided. The method may include forming a deep trench in a substrate; enlarging a width of a lower portion of the deep trench to be wider than a width of the rest of the deep trench; epitaxially forming a compressive stress layer in the lower portion of the deep trench; forming a metal-insulator-metal (MIM) stack within the lower portion of the deep trench; and filling a remaining portion of the deep trench with a semiconductor. Alternatively to forming the compressive stress layer or in addition thereto, a silicide may be formed by co-deposition of a refractory metal and silicon.

Abstract translation: 提供形成深沟槽电容器的方法。 该方法可以包括在衬底中形成深沟槽; 将所述深沟槽的下部的宽度扩大为比所述深沟槽的其余部分的宽度宽; 在深沟槽的下部外延形成压应力层; 在深沟槽的下部形成金属 - 绝缘体 - 金属（MIM）堆叠; 以及用半导体填充深沟槽的剩余部分。 除了形成压应力层之外，或者除此之外，还可以通过共沉积难熔金属和硅来形成硅化物。

公开(公告)号：US20150270332A1

公开(公告)日：2015-09-24

申请号：US14222780

申请日：2014-03-24

Applicant: International Business Machines Corporation

Inventor： Eric C. Harley ,  Judson R. Holt ,  Yue Ke ,  Rishikesh Krishnan ,  Timothy J. McArdle ,  Alexander Reznicek ,  Dominic J. Schepis

IPC: H01L29/04 ,  H01L29/66 ,  H01L29/16 ,  H01L29/78 ,  H01L29/167

CPC classification number: H01L29/04 ,  H01L21/823431 ,  H01L21/823821 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/16 ,  H01L29/167 ,  H01L29/66795 ,  H01L29/7851

Abstract: A method of forming a semiconductor structure includes forming a first fin and a second fin on a substrate. A gate structure is formed over a first portion of the first fin and the second fin without covering a second portion of the first fin and the second fin. Single-crystal epitaxial layers are deposited surrounding the second portion of the first fin and the second fin such that the single-crystal epitaxial layer on the first fin does not contact the single-crystal epitaxial layer on the second fin. A polycrystalline layer is then deposited surrounding the single-crystal epitaxial layers, so that the polycrystalline layer contacts the single-crystal epitaxial layer on the first fin and the single-crystal epitaxial layer on the second fin. The single-crystal epitaxial layers and the polycrystalline layer form a merged source-drain region.

Abstract translation: 形成半导体结构的方法包括在衬底上形成第一鳍片和第二鳍片。 栅极结构形成在第一鳍片和第二鳍片的第一部分上，而不覆盖第一鳍片和第二鳍片的第二部分。 围绕第一鳍片和第二鳍片的第二部分沉积单晶外延层，使得第一鳍片上的单晶外延层不接触第二鳍片上的单晶外延层。 然后沉积围绕单晶外延层的多晶层，使得多晶层接触第一鳍上的单晶外延层和第二鳍上的单晶外延层。 单晶外延层和多晶层形成合并的源 - 漏区。

公开(公告)号：US09123826B1

公开(公告)日：2015-09-01

申请号：US14222780

申请日：2014-03-24

Applicant: International Business Machines Corporation

Inventor： Eric C. Harley ,  Judson R. Holt ,  Yue Ke ,  Rishikesh Krishnan ,  Timothy J. McArdle ,  Alexander Reznicek ,  Dominic J. Schepis

IPC: H01L21/8234 ,  H01L27/092

CPC classification number: H01L29/04 ,  H01L21/823431 ,  H01L21/823821 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/16 ,  H01L29/167 ,  H01L29/66795 ,  H01L29/7851

Abstract: A method of forming a semiconductor structure includes forming a first fin and a second fin on a substrate. A gate structure is formed over a first portion of the first fin and the second fin without covering a second portion of the first fin and the second fin. Single-crystal epitaxial layers are deposited surrounding the second portion of the first fin and the second fin such that the single-crystal epitaxial layer on the first fin does not contact the single-crystal epitaxial layer on the second fin. A polycrystalline layer is then deposited surrounding the single-crystal epitaxial layers, so that the polycrystalline layer contacts the single-crystal epitaxial layer on the first fin and the single-crystal epitaxial layer on the second fin. The single-crystal epitaxial layers and the polycrystalline layer form a merged source-drain region.

Abstract translation: 形成半导体结构的方法包括在衬底上形成第一鳍片和第二鳍片。 栅极结构形成在第一鳍片和第二鳍片的第一部分上，而不覆盖第一鳍片和第二鳍片的第二部分。 围绕第一鳍片和第二鳍片的第二部分沉积单晶外延层，使得第一鳍片上的单晶外延层不接触第二鳍片上的单晶外延层。 然后沉积围绕单晶外延层的多晶层，使得多晶层接触第一鳍上的单晶外延层和第二鳍上的单晶外延层。 单晶外延层和多晶层形成合并的源 - 漏区。

公开(公告)号：US20140308821A1

公开(公告)日：2014-10-16

申请号：US13863580

申请日：2013-04-16

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Takashi Ando ,  Michael P. Chudzik ,  Min Dai ,  Martin M. Frank ,  David F. Hilscher ,  Rishikesh Krishnan ,  Barry P. Linder ,  Claude Ortolland ,  Joseph F. Shepard, JR.

IPC: H01L21/02

CPC classification number: H01L21/02301 ,  C23C16/0227 ,  C23C16/403 ,  C23C16/405 ,  C23C16/407 ,  C23C16/45525 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/02186 ,  H01L21/02189 ,  H01L21/02192 ,  H01L21/02236 ,  H01L21/02238 ,  H01L21/02247 ,  H01L21/02249 ,  H01L21/0228 ,  H01L21/02307 ,  H01L21/02312 ,  H01L21/28194 ,  H01L21/762 ,  H01L29/16 ,  H01L29/161 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518

Abstract: A surface of a semiconductor-containing dielectric material/oxynitride/nitride is treated with a basic solution in order to provide hydroxyl group termination of the surface. A dielectric metal oxide is subsequently deposited by atomic layer deposition. The hydroxyl group termination provides a uniform surface condition that facilitates nucleation and deposition of the dielectric metal oxide, and reduces interfacial defects between the oxide and the dielectric metal oxide. Further, treatment with the basic solution removes more oxide from a surface of a silicon germanium alloy with a greater atomic concentration of germanium, thereby reducing a differential in the total thickness of the combination of the oxide and the dielectric metal oxide across surfaces with different germanium concentrations.

Abstract translation: 用碱性溶液处理含半导体的电介质材料/氧氮化物/氮化物的表面，以提供表面的羟基终止。 随后通过原子层沉积沉积介电金属氧化物。 羟基终止提供了促进介电金属氧化物的成核和沉积的均匀的表面条件，并且减少了氧化物和介电金属氧化物之间的界面缺陷。 此外，用碱性溶液处理从锗锗合金的表面除去更多的锗原子浓度的锗，从而减少氧化物和电介质金属氧化物的组合的总厚度与不同锗的表面的差异 浓度

公开(公告)号：US11888048B2

公开(公告)日：2024-01-30

申请号：US17521964

申请日：2021-11-09

Applicant: International Business Machines Corporation

Inventor： Shahab Siddiqui ,  Koji Watanabe ,  Charlotte DeWan Adams ,  Kai Zhao ,  Daniel James Dechene ,  Rishikesh Krishnan

IPC: H01L29/66 ,  H01L29/417 ,  H01L21/8234 ,  H01L29/786 ,  H01L21/02 ,  H01L29/423

CPC classification number: H01L29/6675 ,  H01L21/0259 ,  H01L21/823431 ,  H01L29/41733 ,  H01L29/42384 ,  H01L29/7869

Abstract: A method of forming a semiconductor structure includes forming a first nanosheet stack and a second nanosheet stack on a semiconductor substrate. The first nanosheet stack includes a plurality of alternating first sacrificial layers and first channel layers. The first sacrificial layers each define a first sacrificial height. The second nanosheet stack includes a plurality of alternating second sacrificial layers and second channel layers. The second sacrificial layers each define a second sacrificial height greater than the first sacrificial height of the first sacrificial layers. The method further includes removing the first and second sacrificial layers respectively from the first and second nanosheet stacks. A metal gate is deposited over the first and second nanosheet stacks to form respective first and second nanosheet transistor structures.

公开(公告)号：US20230178553A1

公开(公告)日：2023-06-08

申请号：US17545610

申请日：2021-12-08

Applicant: International Business Machines Corporation

Inventor： Ruilong Xie ,  Julien Frougier ,  Junli Wang ,  Dechao Guo ,  Ruqiang Bao ,  Rishikesh Krishnan ,  Balasubramanian S. Pranatharthiharan

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/49 ,  H01L29/417 ,  H01L23/528 ,  H01L29/786 ,  H01L21/02 ,  H01L21/28 ,  H01L21/8238 ,  H01L29/66

CPC classification number: H01L27/0922 ,  H01L29/0665 ,  H01L29/42392 ,  H01L29/4908 ,  H01L29/41733 ,  H01L23/5286 ,  H01L29/78696 ,  H01L21/0259 ,  H01L21/28088 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823842 ,  H01L21/823871 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66742

Abstract: A semiconductor structure is provided that includes a first FET device stacked over a second FET device, wherein the first FET device contains a first functional gate structure containing a first work function metal and the second FET device contains a second functional gate structure containing a second work function metal. In the structure, the first work function metal is absent from an area including the second work function metal, and vice versa. Thus, no shared work functional metal is present in the semiconductor structure.

公开(公告)号：US11211474B2

公开(公告)日：2021-12-28

申请号：US16742295

申请日：2020-01-14

Applicant: International Business Machines Corporation

Inventor： Shahab Siddiqui ,  Koji Watanabe ,  Charlotte DeWan Adams ,  Kai Zhao ,  Daniel James Dechene ,  Rishikesh Krishnan

IPC: H01L29/66 ,  H01L29/417 ,  H01L21/8234 ,  H01L29/786 ,  H01L21/02 ,  H01L29/423

Abstract: A method of forming a semiconductor structure includes forming a first nanosheet stack and a second nanosheet stack on a semiconductor substrate. The first nanosheet stack includes a plurality of alternating first sacrificial layers and first channel layers. The first sacrificial layers each define a first sacrificial height. The second nanosheet stack includes a plurality of alternating second sacrificial layers and second channel layers. The second sacrificial layers each define a second sacrificial height greater than the first sacrificial height of the first sacrificial layers. The method further includes removing the first and second sacrificial layers respectively from the first and second nanosheet stacks. A metal gate is deposited over the first and second nanosheet stacks to form respective first and second nanosheet transistor structures.

公开(公告)号：US09831084B2

公开(公告)日：2017-11-28

申请号：US14874386

申请日：2015-10-03

Applicant: International Business Machines Corporation

Inventor： Takashi Ando ,  Michael P. Chudzik ,  Min Dai ,  Martin M. Frank ,  David F. Hilscher ,  Rishikesh Krishnan ,  Barry P. Linder ,  Claude Ortolland ,  Joseph F. Shepard, Jr.

IPC: H01L21/311 ,  H01L21/8238 ,  H01L29/51 ,  H01L21/02 ,  H01L21/28 ,  C23C16/02 ,  C23C16/455 ,  H01L21/762 ,  H01L29/16 ,  H01L29/161 ,  C23C16/40

CPC classification number: H01L21/02301 ,  C23C16/0227 ,  C23C16/403 ,  C23C16/405 ,  C23C16/407 ,  C23C16/45525 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/02186 ,  H01L21/02189 ,  H01L21/02192 ,  H01L21/02236 ,  H01L21/02238 ,  H01L21/02247 ,  H01L21/02249 ,  H01L21/0228 ,  H01L21/02307 ,  H01L21/02312 ,  H01L21/28194 ,  H01L21/762 ,  H01L29/16 ,  H01L29/161 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518

Abstract: A surface of a semiconductor-containing dielectric material/oxynitride/nitride is treated with a basic solution in order to provide hydroxyl group termination of the surface. A dielectric metal oxide is subsequently deposited by atomic layer deposition. The hydroxyl group termination provides a uniform surface condition that facilitates nucleation and deposition of the dielectric metal oxide, and reduces interfacial defects between the oxide and the dielectric metal oxide. Further, treatment with the basic solution removes more oxide from a surface of a silicon germanium alloy with a greater atomic concentration of germanium, thereby reducing a differential in the total thickness of the combination of the oxide and the dielectric metal oxide across surfaces with different germanium concentrations.