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    INTEGRATED LATERAL HIGH VOLTAGE MOSFET
    31.
    发明申请
    INTEGRATED LATERAL HIGH VOLTAGE MOSFET 有权
    集成式横向高压MOSFET

    公开(公告)号：US20120112277A1

    公开(公告)日：2012-05-10

    申请号：US13284011

    申请日：2011-10-28

    申请人： Marie Denison ,  Sameer Pendharkar ,  Philip L. Hower

    发明人： Marie Denison ,  Sameer Pendharkar ,  Philip L. Hower

    IPC分类号： H01L29/78 ,  H01L21/336

    CPC分类号： H01L29/7816 ,  H01L21/265 ,  H01L21/823814 ,  H01L27/0922 ,  H01L29/0696 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/1083 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7835

    摘要： An integrated circuit containing a dual drift layer extended drain MOS transistor with an upper drift layer contacting a lower drift layer along at least 75 percent of a common length of the two drift layers. An average doping density in the lower drift layer is between 2 and 10 times an average doping density in the upper drift layer. A process of forming an integrated circuit containing a dual drift layer extended drain MOS transistor with a lower drift extension under the body region and an isolation link which electrically isolates the body region, using an epitaxial process. A process of forming an integrated circuit containing a dual drift layer extended drain MOS transistor with a lower drift extension under the body region and an isolation link which electrically isolates the body region, on a monolithic substrate.

    摘要翻译： 一种包含双漂移层延伸漏极MOS晶体管的集成电路，其上部漂移层沿着两个漂移层的公共长度的至少75％与下部漂移层接触。 下漂移层中的平均掺杂密度在上漂移层中的平均掺杂密度的2至10倍。 一种形成集成电路的过程，该集成电路包含在体区内具有较低漂移延伸的双漂移层延伸漏极MOS晶体管，以及使用外延工艺电隔离体区的隔离链路。 一种形成集成电路的过程，该集成电路包含在主体区域具有较低漂移延伸的双漂移层延伸漏极MOS晶体管和在整体式衬底上电隔离体区的隔离链路。

    Trench isolation comprising process having multiple gate dielectric thicknesses and integrated circuits therefrom
    32.
    发明授权
    Trench isolation comprising process having multiple gate dielectric thicknesses and integrated circuits therefrom 有权
    包括具有多个栅介质厚度的工艺和其集成电路的沟槽隔离

    公开(公告)号：US07888196B2

    公开(公告)日：2011-02-15

    申请号：US12345072

    申请日：2008-12-29

    申请人： Seetharaman Sridhar ,  Sameer Pendharkar ,  Dan M. Mosher

    发明人： Seetharaman Sridhar ,  Sameer Pendharkar ,  Dan M. Mosher

    IPC分类号： H01L21/8238

    CPC分类号： H01L21/823462 ,  H01L21/76229 ,  H01L21/823481 ,  H01L21/823857 ,  H01L21/823878

    摘要： A method of fabricating an integrated circuit (IC) including a first plurality of MOS transistors having a first gate dielectric having a first thickness in first regions, and a second plurality of MOS transistors having a second gate dielectric having a second thickness in second regions, wherein the first thickness

    摘要翻译： 一种制造集成电路（IC）的方法，所述集成电路（IC）包括第一多个MOS晶体管，所述第一多个MOS晶体管具有在第一区域中具有第一厚度的第一栅极电介质，以及第二多个MOS晶体管， 其中所述第一厚度<所述第二厚度。 提供具有半导体表面的衬底。 具有厚度为nlE的焊盘电介质层;在包括第二区域的半导体表面上形成第二厚度，其中焊盘介电层为第二栅极电介质提供第二厚度的至少一部分。 在包括第二区域的半导体表面上形成硬掩模层。 通过蚀刻通过焊盘介电层和半导体表面的一部分形成多个沟槽隔离区域。 多个沟槽隔离区域填充有介电填充材料以形成沟槽隔离区域，然后去除硬掩模层。 在第二栅极电介质上形成图案化的栅极电极层，其中所述图案化的栅极电极层在至少一个沟槽隔离区域的表面上延伸。 然后完成第一和第二区域中的MOS晶体管的制造。

    Formation of a MOSFET Using an Angled Implant
    33.
    发明申请
    Formation of a MOSFET Using an Angled Implant 有权
    使用倾斜植入物形成MOSFET

    公开(公告)号：US20090294841A1

    公开(公告)日：2009-12-03

    申请号：US12509922

    申请日：2009-07-27

    申请人： Sameer Pendharkar ,  Binghua Hu

    发明人： Sameer Pendharkar ,  Binghua Hu

    IPC分类号： H01L29/78

    CPC分类号： H01L29/66712 ,  H01L21/26513 ,  H01L21/26586 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/086 ,  H01L29/1083 ,  H01L29/1095 ,  H01L29/66681 ,  H01L29/7809 ,  H01L29/7816

    摘要： A LDMOS transistor having a channel region located between an outer boundary of an n-type region and an inner boundary of a p-body region. A width of the LDMOS channel region is less than 80% of a distance between an outer boundary of an n+-type region and the inner boundary of a p-body region. Also, a method for making a LDMOS transistor where the n-type dopants are implanted at an angle that is greater than an angle used to implant the p-type dopants. Furthermore, a VDMOS having first and second channel regions located between an inner boundary of a first and second p-body region and an outer boundary of an n-type region of the first and second p-body regions. The width of the first and second channel regions of the VDMOS is less than 80% of a distance between the inner boundary of the first and second p-body regions and an outer boundary of an n+-type region of the first and second p-body regions. Moreover, a method for making a VDMOS transistor where the n-type dopants are implanted at an angle that is greater than an angle used to implant the p-type dopants.

    摘要翻译： 一种LDMOS晶体管，其具有位于n型区域的外边界和p体区域的内边界之间的沟道区域。 LDMOS通道区域的宽度小于n +型区域的外边界与p体区域的内边界之间的距离的80％。 此外，制造LDMOS晶体管的方法，其中n型掺杂剂以大于用于注入p型掺杂剂的角度的角度注入。 此外，VDMOS具有位于第一和第二p体区域的内边界和第一和第二p体区域的n型区域的外边界之间的第一和第二沟道区域。 VDMOS的第一和第二沟道区域的宽度小于第一和第二p体区域的内边界与第一和第二p体区域的n +型区域的外边界之间的距离的80％ 身体区域。 此外，制造VDMOS晶体管的方法，其中n型掺杂剂以大于用于注入p型掺杂剂的角度的角度注入。

    Non-uniformly doped high voltage drain-extended transistor and method of manufacture thereof
    34.
    发明授权
    Non-uniformly doped high voltage drain-extended transistor and method of manufacture thereof 有权
    非均匀掺杂高压漏极延迟晶体管及其制造方法

    公开(公告)号：US07618870B2

    公开(公告)日：2009-11-17

    申请号：US12357653

    申请日：2009-01-22

    申请人： Shanjen Pan ,  Sameer Pendharkar ,  James R. Todd

    发明人： Shanjen Pan ,  Sameer Pendharkar ,  James R. Todd

    IPC分类号： H01L21/336

    CPC分类号： H01L29/0847 ,  H01L21/266 ,  H01L27/0623 ,  H01L29/0619 ,  H01L29/0692 ,  H01L29/42368 ,  H01L29/66659 ,  H01L29/7835 ,  H01L2029/42388

    摘要： The present invention provides, in one embodiment, a transistor (100). The transistor (100) comprises a doped semiconductor substrate (105) and a gate structure (110) over the semiconductor substrate (105), the gate structure (110) having a gate corner (125). The transistor (100) also includes a drain-extended well (115) surrounded by the doped semiconductor substrate (105). The drain-extended well (115) has an opposite dopant type as the doped semiconductor substrate (105). The drain-extended well (115) also has a low-doped region (145) between high-doped regions (150), wherein an edge of the low-doped region (155) is substantially coincident with a perimeter (140) defined by the gate corner (125). Other embodiments of the present invention include a method of manufacturing a transistor (200) and an integrated circuit (300).

    摘要翻译： 本发明在一个实施例中提供一种晶体管（100）。 晶体管（100）包括半导体衬底（105）上方的掺杂半导体衬底（105）和栅极结构（110），栅极结构（110）具有栅极拐角（125）。 晶体管（100）还包括由掺杂半导体衬底（105）围绕的漏极扩展阱（115）。 漏极扩展阱（115）具有与掺杂半导体衬底（105）相反的掺杂剂类型。 漏极扩展阱（115）还在高掺杂区域（150）之间具有低掺杂区域（145），其中低掺杂区域（155）的边缘基本上与由 门角（125）。 本发明的其他实施例包括制造晶体管（200）和集成电路（300）的方法。

    Methods of fabricating high voltage devices
    36.
    发明申请
    Methods of fabricating high voltage devices 有权
    制造高压器件的方法

    公开(公告)号：US20060286741A1

    公开(公告)日：2006-12-21

    申请号：US11154431

    申请日：2005-06-16

    申请人： Shanjen Pan ,  Sameer Pendharkar ,  Pinghai Hao ,  James Todd

    发明人： Shanjen Pan ,  Sameer Pendharkar ,  Pinghai Hao ,  James Todd

    IPC分类号： H01L21/8244

    CPC分类号： H01L27/0629 ,  H01L29/1083 ,  H01L29/402 ,  H01L29/66659 ,  H01L29/7835

    摘要： Methods of fabrication and devices include field plates formed during capacitor formation. Isolation structures are formed in a semiconductor substrate. Well regions are formed in the semiconductor substrate. Drain extension regions are formed in the well regions. A gate dielectric layer is formed over the device. A gate electrode layer is formed that serves as the gate electrode and a bottom capacitor plate. The gate electrode and the gate dielectric layer are patterned to form gate structures. Source and drain regions are formed within the well regions and the drain extension regions. A silicide blocking layer is formed that also serves as a capacitor dielectric. Field plates and a top capacitor plate are formed on the blocking layer.

    摘要翻译： 制造方法和器件包括在电容器形成期间形成的场板。 在半导体衬底中形成隔离结构。 在半导体衬底中形成阱区。 在阱区域中形成漏极延伸区域。 在器件上形成栅极电介质层。 形成用作栅电极和底电容器板的栅极电极层。 对栅极电极和栅极介电层进行图案化以形成栅极结构。 源区和漏区形成在阱区和漏极延伸区内。 形成也用作电容器电介质的硅化物阻挡层。 在阻挡层上形成场板和顶部电容器板。

    Method and structure for a low voltage CMOS integrated circuit incorporating higher-voltage devices
    38.
    发明授权
    Method and structure for a low voltage CMOS integrated circuit incorporating higher-voltage devices 有权
    采用高压器件的低压CMOS集成电路的方法和结构

    公开(公告)号：US07112480B2

    公开(公告)日：2006-09-26

    申请号：US11187472

    申请日：2005-07-22

    申请人： Shanjen Pan ,  James R. Todd ,  Sameer Pendharkar

    发明人： Shanjen Pan ,  James R. Todd ,  Sameer Pendharkar

    IPC分类号： H01L21/8238

    CPC分类号： H01L29/7833 ,  H01L21/823418 ,  H01L21/823814 ,  H01L27/088 ,  H01L27/0922

    摘要： A CMOS integrated circuit (15A-B-C) includes both relatively low-power (124, 126) and high-power (132, 134) CMOS transistors on the same chip. A 20V, relatively high-power PMOS device (134) includes a heavily doped N-well drain region (70). A 20V, relatively high-power NMOS device (132) includes heavily doped P-type buried layers (76, 78) underneath the source (94) and drain regions (96) and spanning the gap between the P-well gate (90F) and adjacent P-well isolation regions (46, 50).

    摘要翻译： CMOS集成电路（15A-B-C）包括同一芯片上的相对低功率（124,126）和大功率（132,134）CMOS晶体管。 20V，相对高功率的PMOS器件（134）包括重掺杂的N阱漏极区（70）。 20V，相对高功率的NMOS器件（132）包括在源极（94）和漏极区（96）下面的重掺杂的P型掩埋层（76,78），并跨越P阱栅极（90°F）之间的间隙 ）和相邻的P阱隔离区（46,50）。

    System and method for making a LDMOS device with electrostatic discharge protection
    40.
    发明申请
    System and method for making a LDMOS device with electrostatic discharge protection 有权
    制造具有静电放电保护功能的LDMOS器件的系统和方法

    公开(公告)号：US20060186467A1

    公开(公告)日：2006-08-24

    申请号：US11063312

    申请日：2005-02-21

    申请人： Sameer Pendharkar ,  Jonathan Brodsky

    发明人： Sameer Pendharkar ,  Jonathan Brodsky

    IPC分类号： H01L29/76

    CPC分类号： H01L29/66681 ,  H01L27/088 ,  H01L29/086 ,  H01L29/42368 ,  H01L29/7436 ,  H01L29/749 ,  H01L29/7816

    摘要： A semiconductor device includes one or more LDMOS transistors and one of more SCR-LDMOS transistors. Each LDMOS transistor includes a LDMOS well of a first conductivity type, a LDMOS source region of a second conductivity type formed in the LDMOS well, and a LDMOS drain region of a second conductivity type separated from the LDMOS well by a LDMOS drift region of the second conductivity type. Each SCR-LDMOS transistor comprising a SCR-LDMOS well of the first conductivity type, a SCR-LDMOS source region of the second conductivity type formed in the SCR-LDMOS well, a SCR-LDMOS drain region of a second conductivity type, and a anode region of the first conductivity type between the SCR-LDMOS drain region and the SCR-LDMOS drift region. The anode region is separated from the SCR-LDMOS well by a SCR-LDMOS drift region of the second conductivity type.

    摘要翻译： 半导体器件包括一个或多个LDMOS晶体管和一个更多的SCR-LDMOS晶体管。 每个LDMOS晶体管包括第一导电类型的LDMOS阱，在LDMOS阱中形成的第二导电类型的LDMOS源极区，以及由LDMOS阱的LDMOS漂移区分离的第二导电类型的LDMOS漏极区， 第二导电类型。 每个SCR-LDMOS晶体管包括第一导电类型的SCR-LDMOS阱，形成在SCR-LDMOS阱中的第二导电类型的SCR-LDMOS源区，第二导电类型的SCR-LDMOS漏极区和 SCR-LDMOS漏区和SCR-LDMOS漂移区之间的第一导电类型的阳极区。 阳极区域通过第二导电类型的SCR-LDMOS漂移区与SCR-LDMOS阱分离。