High density integrated circuit packaging with chip stacking and via interconnections
    32.
    发明授权
    High density integrated circuit packaging with chip stacking and via interconnections 失效
    高密度集成电路封装,具有芯片堆叠和通孔互连

    公开(公告)号:US06187678B1

    公开(公告)日:2001-02-13

    申请号:US09379716

    申请日:1999-08-24

    IPC分类号: H01L2144

    摘要: Chip stacks with decreased conductor length and improved noise immunity are formed by laser drilling of individual chips, such as memory chips, preferably near but within the periphery thereof, and forming conductors therethrough, preferably by metallization or filling with conductive paste which may be stabilized by transient liquid phase (TLP) processes and preferably with or during metallization of conductive pads, possibly including connector patterns on both sides of at least some of the chips in the stack. At least some of the chips in the stack then have electrical and mechanical connections made therebetween, preferably with electroplated solder preforms consistent with TLP processes. The connections may be contained by a layer of resilient material surrounding the connections and which may be formed in-situ. High density circuit packages thus obtained may be mounted on a carrier by surface mount techniques or separable connectors such as a plug and socket arrangement. The carrier may be of the same material as the chip stacks to match coefficients of thermal expansion. High-density circuit packages may also be in the form of removable memory modules in generally planar or prism shaped form similar to a pen or as a thermal conduction module.

    摘要翻译: 具有降低的导体长度和改善的抗噪声性的芯片堆叠通过激光钻孔单独的芯片,例如存储芯片,优选靠近但在其周围内,并且通过其形成导体,优选地通过金属化或填充导电浆料来形成,该导电浆料可以由 瞬态液相(TLP)工艺,并且优选地在导电焊盘的金属化期间或期间,或者可能包括堆叠中的至少一些芯片的两侧上的连接器图案。 堆叠中的至少一些芯片之后具有在其间形成的电气和机械连接,优选地使用与TLP工艺一致的电镀焊料预制件。 连接可以由围绕连接的一层弹性材料容纳,并且可以在现场形成。 由此获得的高密度电路封装可以通过表面贴装技术或诸如插头和插座装置的可分离连接器安装在载体上。 载体可以具有与芯片堆叠相同的材料以匹配热膨胀系数。 高密度电路封装也可以是类似于笔或作为导热模块的大致平面或棱柱形形式的可移除存储器模块的形式。