公开(公告)号：US20200258750A1

公开(公告)日：2020-08-13

申请号：US16861740

申请日：2020-04-29

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Francis J. CARNEY ,  Michael J. SEDDON ,  Eiji KUROSE ,  Chee Hiong CHEW ,  Soon Wei WANG ,  Yusheng LIN

IPC: H01L21/302 ,  H01L21/56 ,  H01L21/78 ,  H01L23/00 ,  H01L23/12 ,  H01L21/48 ,  H01L23/31

Abstract: Implementations of a semiconductor device may include a semiconductor die comprising a first largest planar surface, a second largest planar surface and a thickness between the first largest planar surface and the second largest planar surface, and a permanent die support structure coupled to one of the first largest planar surface, the second largest planar surface, the thickness, or any combination thereof. The thickness may be between 0.1 microns and 125 microns. The warpage of the semiconductor die may be less than 200 microns.

公开(公告)号：US20190067143A1

公开(公告)日：2019-02-28

申请号：US15812591

申请日：2017-11-14

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Soon Wei WANG ,  Jin Yoong LIONG ,  Chee Hiong CHEW ,  Francis J. CARNEY

IPC: H01L23/31 ,  H01L23/492 ,  H01L23/00 ,  H01L25/07 ,  H01L25/18 ,  H01L21/78 ,  H01L21/56 ,  H01L21/3105

CPC classification number: H01L23/3114 ,  H01L21/31053 ,  H01L21/561 ,  H01L21/565 ,  H01L21/78 ,  H01L23/3107 ,  H01L23/492 ,  H01L23/49562 ,  H01L23/49575 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/32 ,  H01L24/73 ,  H01L24/94 ,  H01L24/96 ,  H01L25/0655 ,  H01L25/072 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/04105 ,  H01L2224/06181 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16245 ,  H01L2224/32245 ,  H01L2224/73153 ,  H01L2224/73253 ,  H01L2224/9202 ,  H01L2224/94 ,  H01L2224/96 ,  H01L2924/1203 ,  H01L2924/13091 ,  H01L2924/1815 ,  H01L2924/1816 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2224/11 ,  H01L2924/014

Abstract: In a general aspect, an apparatus can include a metal layer, a first semiconductor die, a second semiconductor die, a molding compound, a first electrical contact and a second electrical contact. The first semiconductor die can have a first side disposed on the metal layer. The second semiconductor die can have a first side disposed on the metal layer. The metal layer can electrically couple the first side of the first semiconductor die with the first side of the second semiconductor die. The molding compound can at least partially encapsulate the metal layer, the first semiconductor die and the second semiconductor die. The first electrical contact can be to a second side of the first semiconductor die and disposed on a surface of the apparatus. The second electrical contact can be to a second side of the second semiconductor die and disposed on the surface of the apparatus.

公开(公告)号：US20170345779A1

公开(公告)日：2017-11-30

申请号：US15168467

申请日：2016-05-31

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Yusheng LIN ,  Soon Wei WANG ,  Chee Hiong CHEW ,  Francis J. CARNEY

IPC: H01L23/00 ,  H01L21/683 ,  H01L21/78

CPC classification number: H01L24/02 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6836 ,  H01L21/78 ,  H01L23/3185 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L24/94 ,  H01L24/96 ,  H01L2223/54406 ,  H01L2223/5448 ,  H01L2224/02315 ,  H01L2224/0239 ,  H01L2224/024 ,  H01L2224/0346 ,  H01L2224/0401 ,  H01L2224/05571 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/11334 ,  H01L2224/11849 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2224/94 ,  H01L2224/96 ,  H01L2224/03 ,  H01L2224/11 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/014

Abstract: A method for fabricating a chip scale package, comprising: providing a wafer; applying a polymer resin on at least part of a first surface of the wafer and to one or more sides of the wafer; and applying a compression mold on at least part of a second surface of the wafer and to one or more sides of the wafer, said first and second surfaces opposing each other.

公开(公告)号：US20170133302A1

公开(公告)日：2017-05-11

申请号：US15415504

申请日：2017-01-25

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Darrell D. TRUHITTE ,  Soon Wei WANG ,  Chee Hiong CHEW

IPC: H01L23/495 ,  H01L23/00 ,  H01L23/31 ,  H01L21/56 ,  H01L21/48

CPC classification number: H01L23/49541 ,  H01L21/4828 ,  H01L21/561 ,  H01L21/568 ,  H01L23/3107 ,  H01L23/49548 ,  H01L23/49575 ,  H01L23/49582 ,  H01L24/48 ,  H01L24/49 ,  H01L24/85 ,  H01L24/97 ,  H01L2224/05014 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48157 ,  H01L2224/48247 ,  H01L2224/48464 ,  H01L2224/49171 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/17747 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/00012 ,  H01L2224/05599 ,  H01L2224/85399

Abstract: A leadframe includes a frame, a die pad, a contact including a flank adjacent to the frame, a first tie bar between the frame and die pad, and a second tie bar between the die pad and contact. The leadframe is disposed over a carrier. A semiconductor die is disposed over the die pad. An encapsulant is deposited over the leadframe and semiconductor die including between the carrier and half-etched portions of the leadframe. A first trench is formed in the encapsulant to remove a portion of the frame and expose the flank of the contact. A conductive layer is formed over the flank by electroplating. A second trench is formed in the encapsulant through the second tie bar after forming the conductive layer.