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公开(公告)号：US09324585B2
公开(公告)日：2016-04-26
申请号：US13654754
申请日：2012-10-18
Applicant: Siliconware Precision Industries Co., Ltd.
Inventor： Chiang-Cheng Chang , Meng-Tsung Lee , Jung-Pang Huang , Shih-Kuang Chiu , Fu-Tang Huang
CPC classification number: H01L21/568 , H01L21/561 , H01L21/6835 , H01L21/76802 , H01L21/76834 , H01L21/76877 , H01L23/3128 , H01L24/19 , H01L24/96 , H01L2221/68318 , H01L2221/68359 , H01L2221/68381 , H01L2224/0401 , H01L2224/04105 , H01L2224/05567 , H01L2224/12105 , H01L2224/131 , H01L2224/24153 , H01L2924/00014 , H01L2924/014 , H01L2224/05552
Abstract: A method of fabricating a semiconductor package is provided, including: disposing a plurality of semiconductor elements on a carrier through an adhesive layer in a manner that a portion of the carrier is exposed from the adhesive layer; forming an encapsulant to encapsulate the semiconductor elements; removing the adhesive layer and the carrier to expose the semiconductor elements; and forming a build-up structure on the semiconductor elements. Since the adhesive layer is divided into a plurality of separated portions that will not affect each other due to expansion or contraction when temperature changes, the present invention prevents positional deviations of the semiconductor elements during a molding process, thereby increasing the alignment accuracy.
Abstract translation: 提供一种制造半导体封装的方法，包括：通过粘合剂层将多个半导体元件设置在载体上，使载体的一部分从粘合剂层露出; 形成密封剂以封装半导体元件; 去除粘合剂层和载体以暴露半导体元件; 以及在半导体元件上形成积聚结构。 由于当温度变化时粘合剂层被分成多个不会由于膨胀或收缩而相互影响的分离部分，所以本发明防止了半导体元件在成型过程中的位置偏差，从而提高了对准精度。
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32.发明申请FLIP-CHIP PACKAGING SUBSTRATE, FLIP-CHIP PACKAGE AND FABRICATION METHODS THEREOF 审中-公开卷芯片包装基板，卷芯片包装及其制造方法公开(公告)号：US20150235914A1
公开(公告)日：2015-08-20
申请号：US14328092
申请日：2014-07-10
Applicant: Siliconware Precision Industries Co., Ltd.
Inventor： Chang-Fu Lin , Chin-Tsai Yao , Ming-Chin Chuang , Po-Hua Chen , Fu-Tang Huang
CPC classification number: H05K3/4661 , C25D5/02 , C25D5/48 , C25D7/00 , H01L21/4853 , H01L23/49894 , H01L24/16 , H01L24/81 , H01L2224/131 , H01L2224/16237 , H01L2224/81191 , H01L2224/81385 , H01L2224/81444 , H01L2224/81815 , H01L2924/3841 , H05K1/111 , H05K3/244 , H05K3/3436 , H05K2201/09745 , H05K2201/099 , H05K2201/10674 , H01L2924/00014 , H01L2924/014
Abstract: A flip-chip packaging substrate is provided, which includes: a substrate body; a plurality of conductive pads formed on a surface of the substrate body; an insulating layer formed on the surface of the substrate body and having a plurality of openings correspondingly exposing a portion of each of the conductive pads; and a metal layer formed on each of the conductive pads in the openings, wherein the metal layer has a top surface having a lowest point lower than a top surface of the insulating layer, and a thickness ratio of the metal layer to the insulating layer is greater than or equal to 1/4 and less than 1, thereby preventing a solder bridge or short circuit from occurring.
Abstract translation: 提供一种倒装芯片封装基板，其包括：基板主体; 形成在所述基板主体的表面上的多个导电焊盘; 绝缘层，其形成在所述基板主体的表面上并且具有多个开口，对应地暴露所述导电焊盘的每一个的一部分; 以及形成在所述开口中的每个所述导电焊盘上的金属层，其中，所述金属层具有比所述绝缘层的顶表面低的最低点的顶表面，并且所述金属层与所述绝缘层的厚度比为 大于或等于1/4且小于1，从而防止发生焊料桥或短路。
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公开(公告)号：US20150014848A1
公开(公告)日：2015-01-15
申请号：US14258361
申请日：2014-04-22
Applicant: Siliconware Precision Industries Co., Ltd.
Inventor： Chang-Fu Lin , Chin-Tsai Yao , Ming-Chin Chuang , Fu-Tang Huang
IPC: H01L23/00
CPC classification number: H01L24/81 , H01L21/4846 , H01L23/49811 , H01L24/05 , H01L24/13 , H01L24/16 , H01L24/17 , H01L2224/0401 , H01L2224/05572 , H01L2224/131 , H01L2224/13147 , H01L2224/1601 , H01L2224/16057 , H01L2224/16225 , H01L2224/16227 , H01L2224/16237 , H01L2224/17106 , H01L2224/73204 , H01L2224/81385 , H01L2224/81815 , H01L2924/01029 , H01L2924/35121 , H01L2924/00014 , H01L2924/014 , H01L2924/00012
Abstract: A semiconductor device is disclosed, which includes: a substrate having a substrate body and a plurality of conductive pads formed on the substrate body, wherein each of the conductive pads has at least an opening formed in a first surface thereof; a semiconductor component having a plurality of bonding pads; a plurality of conductive elements formed between the bonding pads and the conductive pads and in the openings of the conductive pads; and an encapsulant formed between the substrate and the semiconductor component for encapsulating the conductive elements, thereby strengthening the bonding between the conductive elements and the conductive pads and consequently increasing the product yield.
Abstract translation: 公开了一种半导体器件，其包括：具有基板主体的基板和形成在基板主体上的多个导电焊盘，其中每个导电焊盘至少形成在其第一表面中的开口; 具有多个接合焊盘的半导体部件; 在所述接合焊盘和所述导电焊盘之间以及所述导电焊盘的所述开口中形成的多个导电元件; 以及形成在衬底和半导体部件之间用于封装导电元件的密封剂，从而加强导电元件和导电焊盘之间的接合，从而提高产品产量。
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公开(公告)号：US20200212019A1
公开(公告)日：2020-07-02
申请号：US16817001
申请日：2020-03-12
Applicant: Siliconware Precision Industries Co., Ltd.
Inventor： Chi-Rui Wu , Fu-Tang Huang , Chia-Cheng Chen , Chun-Hsien Lin , Hsuan-Hao Mi , Yu-Cheng Pai
IPC: H01L25/10 , H01L23/24 , H01L23/498 , H01L25/00
Abstract: An electronic package is provided, including: a first substrate having a first insulating portion; a first electronic component disposed on the first substrate; a second substrate having a second insulating portion and stacked on the first substrate through a plurality of conductive elements; and a first encapsulant formed between the first substrate and the second substrate. The first insulating portion of the first substrate differs in rigidity from the second insulating portion of the second substrate. As such, during a high temperature process, one of the first substrate and the second substrate pulls at the other to bend toward the same direction, thereby reducing warpage deviation of the overall electronic package. The present invention further provides a method for fabricating the electronic package.
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公开(公告)号：US20190259723A1
公开(公告)日：2019-08-22
申请号：US16403877
申请日：2019-05-06
Applicant: Siliconware Precision Industries Co., Ltd.
Inventor： Yi-Cheih Chen , Sung-Huan Sun , Cheng-An Chang , Chien-Hung Wu , Fu-Tang Huang
IPC: H01L23/00
Abstract: The present invention provides a semiconductor structure and a method of fabricating the same. The method includes: providing a chip having conductive pads, forming a metal layer on the conductive pads, forming a passivation layer on a portion of the metal layer, and forming conductive pillars on the metal layer. Since the metal layer is protected by the passivation layer, the undercut problem is solved, the supporting strength of the conductive pillars is increased, and the product reliability is improved.
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Patent Agency Ranking
公开(公告)号：US20190164941A1
公开(公告)日：2019-05-30
申请号：US15938271
申请日：2018-03-28
Applicant: Siliconware Precision Industries Co., Ltd.
Inventor： Chi-Rui Wu , Fu-Tang Huang , Chia-Cheng Chen , Chun-Hsien Lin , Hsuan-Hao Mi , Yu-Cheng Pai
IPC: H01L25/10 , H01L23/498 , H01L25/00 , H01L23/24
Abstract: An electronic package is provided, including: a first substrate having a first insulating portion; a first electronic component disposed on the first substrate; a second substrate having a second insulating portion and stacked on the first substrate through a plurality of conductive elements; and a first encapsulant formed between the first substrate and the second substrate. The first insulating portion of the first substrate differs in rigidity from the second insulating portion of the second substrate. As such, during a high temperature process, one of the first substrate and the second substrate pulls at the other to bend toward the same direction, thereby reducing warpage deviation of the overall electronic package. The present invention further provides a method for fabricating the electronic package.
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公开(公告)号：US10192834B2
公开(公告)日：2019-01-29
申请号：US15669273
申请日：2017-08-04
Applicant: Siliconware Precision Industries Co., Ltd.
Inventor： Fu-Tang Huang , Chun-Chi Ke
IPC: H01L23/552 , H01L23/31 , H01L25/065 , H01L21/56 , H01L25/00 , H01L23/00
Abstract: A semiconductor package is provided, including: a substrate; a first semiconductor element disposed on the substrate and having a first conductive pad grounded to the substrate; a conductive layer formed on the first semiconductor element and electrically connected to the substrate; a second semiconductor element disposed on the first semiconductor element through the conductive layer; and an encapsulant formed on the substrate and encapsulating the first and second semiconductor elements. Therefore, the first and second semiconductor elements are protected from electromagnetic interference (EMI) shielding with the conductive layer being connected to the grounding pad of the substrate. A fabrication method of the semiconductor package is also provided.
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公开(公告)号：US20180269142A1
公开(公告)日：2018-09-20
申请号：US15590111
申请日：2017-05-09
Applicant: Siliconware Precision Industries Co., Ltd.
Inventor： Chee-Key Chung , Yu-Min Lo , Han-Hung Chen , Chang-Fu Lin , Fu-Tang Huang
IPC: H01L23/498 , H01L23/14 , H01L23/28
CPC classification number: H01L23/49827 , H01L23/147 , H01L23/28 , H01L23/3128 , H01L23/3135 , H01L23/49816 , H01L2224/32225 , H01L2224/73204 , H01L2924/181 , H01L2924/18161 , H01L2924/00012
Abstract: The disclosure provides a substrate construction applicable to a 3D package, including a silicon substrate for carrying a chip on an upper side thereof, and a circuit structure formed underneath the silicon substrate for being connected to solder balls via conductive pads of the circuit structure, thereby obtaining the same specification of the conductive pads as ball-planting pads of conventional package substrates and avoiding the manufacturing and use of conventional package substrates.
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公开(公告)号：US20180158784A1
公开(公告)日：2018-06-07
申请号：US15883808
申请日：2018-01-30
Applicant: Siliconware Precision Industries Co., Ltd.
Inventor： Meng-Tsung Lee , Fu-Tang Huang
CPC classification number: H01L23/552 , H01L21/56 , H01L21/561 , H01L21/568 , H01L23/31 , H01L23/3128 , H01L24/19 , H01L24/20 , H01L24/96 , H01L25/105 , H01L25/50 , H01L2224/04105 , H01L2224/12105 , H01L2224/16227 , H01L2224/24137 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2224/73267 , H01L2225/1035 , H01L2225/1041 , H01L2225/1058 , H01L2924/15311 , H01L2924/18162 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/00014 , H01L2924/00012 , H01L2924/00
Abstract: A method for fabricating an electronic package is provided, including steps of: providing a carrier having at least an electronic element and at least a package block disposed thereon, wherein the package block has a plurality of conductive posts bonded to the carrier; forming an encapsulant on the carrier for encapsulating the electronic element and the package block; and removing the carrier so as to expose the electronic element and the conductive posts from a surface of the encapsulant. As such, the invention dispenses with formation of through holes in the encapsulant for forming the conductive posts as in the prior art, thereby saving the fabrication cost.
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公开(公告)号：US20180063966A1
公开(公告)日：2018-03-01
申请号：US15607872
申请日：2017-05-30
Applicant: Siliconware Precision Industries Co., Ltd.
Inventor： Chih-Hsien Chiu , Chen-Wen Huang , Hsin-Lung Chung , Wen-Jung Tsai , Jia-Huei Hung , Fu-Tang Huang
IPC: H05K3/32 , H01L23/00 , H01L23/373 , H01L21/48
CPC classification number: H05K3/323 , H01L21/4853 , H01L23/373 , H01L24/73
Abstract: An electronic package structure is provided, which includes: a carrier; at least one electronic component and a plurality of conductive elements disposed on the carrier; a metal frame bonded to the conductive elements; and an encapsulant formed on the carrier and the metal frame and encapsulating the electronic component and the conductive elements. The metal frame is exposed from the encapsulant to serve as an electrical contact. As such, instead of using a mold having a particular size corresponding to the electronic package structure as in the prior art, the present disclosure can use a common mold to form the encapsulant, thereby reducing the fabrication cost. The present disclosure further provides a method for fabricating the electronic package structure.
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