公开(公告)号：US11616048B2

公开(公告)日：2023-03-28

申请号：US16897996

申请日：2020-06-10

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Thomas Dyer Bonifield

IPC: H01L25/065 ,  H01L23/58 ,  H01L23/00 ,  H01L23/31 ,  H01L21/56 ,  H01L21/78

Abstract: An integrated circuit (IC) package includes a first die with a first surface overlaying a substrate. The first die includes a first metal pad at a second surface opposing the first surface. The IC package also includes a dielectric layer having a first surface contacting the second surface of the first die. The IC package further includes a second die with a surface that contacts a second surface of the dielectric layer. The second die includes a second metal pad aligned with the first metal pad of the first die. A plane perpendicular to the second surface of the first die intersects the first metal pad and the second metal pad.

公开(公告)号：US11476189B2

公开(公告)日：2022-10-18

申请号：US17120123

申请日：2020-12-12

Applicant: Texas Instruments Incorporated

Inventor： Klaas De Haan ,  Mikhail Valeryevich Ivanov ,  Tobias Bernhard Fritz ,  Swaminathan Sankaran ,  Thomas Dyer Bonifield

IPC: H01L23/522 ,  H01L23/50 ,  H04L25/02 ,  H01L21/50

Abstract: An electronic device has a substrate and first and second metallization levels with a resonant circuit. The first metallization level has a first dielectric layer on a side of the substrate, and a first metal layer on the first dielectric layer. The second metallization level has a second dielectric layer on the first dielectric layer and the first metal layer, and a second metal layer on the second dielectric layer. The electronic device includes a first plate in the first metal layer, and a second plate spaced apart from the first plate in the second metal layer to form a capacitor. The electronic device includes a winding in one of the first and second metal layers and coupled to one of the first and second plates in a resonant circuit.

公开(公告)号：US20220148912A1

公开(公告)日：2022-05-12

申请号：US17583322

申请日：2022-01-25

Applicant: Texas Instruments Incorporated

Inventor： Scott Robert Summerfelt ,  Thomas Dyer Bonifield ,  Sreeram Subramanyam Nasum ,  Peter Smeys ,  Benjamin Stassen Cook

IPC: H01L21/762 ,  H01L49/02 ,  H01L27/12 ,  H01L23/544 ,  H01L23/00 ,  H01L21/78

Abstract: In described examples of an integrated circuit (IC) there is a substrate of semiconductor material having a first region with a first transistor formed therein and a second region with a second transistor formed therein. An isolation trench extends through the substrate and separates the first region of the substrate from the second region of the substrate. An interconnect region having layers of dielectric is disposed on a top surface of the substrate. A dielectric polymer is disposed in the isolation trench and in a layer over the backside surface of the substrate. An edge of the polymer layer is separated from the perimeter edge of the substrate by a space.

公开(公告)号：US11270930B2

公开(公告)日：2022-03-08

申请号：US16806362

申请日：2020-03-02

Applicant: Texas Instruments Incorporated

Inventor： Thomas Dyer Bonifield

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/00 ,  H01L23/64 ,  H01L49/02 ,  H01L25/065 ,  H01L25/00

Abstract: An isolator device includes a laminate die having a dielectric laminate material with a metal laminate layer on one side of the dielectric laminate material, the metal laminate layer being a patterned layer providing at least a first plate, including a dielectric layer over the first plate that includes an aperture exposing a portion of the first plate. An integrated circuit (IC) including a substrate having a semiconductor surface includes circuitry including a transmitter and/or a receiver, the IC including a top metal layer providing at least a second plate coupled to a node in the circuitry, with at least one passivation layer on the top metal layer. A non-conductive die attach (NCDA) material for attaching a side of the dielectric laminate material is opposite the metal laminate layer to the IC so that the first plate is at least partially over the second plate to provide a capacitor.

公开(公告)号：US20210020564A1

公开(公告)日：2021-01-21

申请号：US16916748

申请日：2020-06-30

Applicant: Texas Instruments Incorporated

Inventor： Jeffrey Alan West ,  Thomas Dyer Bonifield

IPC: H01L23/522 ,  H01L23/58

Abstract: An integrated circuit includes a semiconductor substrate and a plurality of dielectric layers over the semiconductor substrate, including a top dielectric layer. A metal plate or metal coil is located over the top dielectric layer; a metal ring is located over the top dielectric layer and substantially surrounds the metal plate or metal coil. A protective overcoat overlies the metal ring and overlies the metal plate or metal coil. A trench opening is formed through the protective overcoat, with the trench opening exposing the top dielectric layer between the metal plate/coil and the metal ring, the trench opening substantially surrounding the metal plate or metal coil.

公开(公告)号：US20200091048A1

公开(公告)日：2020-03-19

申请号：US16134924

申请日：2018-09-18

Applicant: Texas Instruments Incorporated

Inventor： Anindya Poddar ,  Thomas Dyer Bonifield ,  Woochan Kim ,  Vivek Kishorechand Arora

IPC: H01L23/495 ,  H01L23/532 ,  H01L21/48

Abstract: Described herein is a technology or a method for fabricating a flip-chip on lead (FOL) semiconductor package. A lead frame includes an edge on surface that has a geometric shape that provides a radial and uniform distribution of electric fields. By placing the formed geometric shape along an active die of a semiconductor chip, the electric fields that are present in between the lead frame and the semiconductor chip are uniformly concentrated.

公开(公告)号：US10366958B2

公开(公告)日：2019-07-30

申请号：US15857234

申请日：2017-12-28

Applicant: Texas Instruments Incorporated

Inventor： Thomas Dyer Bonifield ,  Jeffrey Alan West ,  Byron Lovell Williams

IPC: B81B7/00 ,  H01L23/00 ,  H01L23/64 ,  H01L25/00 ,  H01L27/07 ,  H01L49/02 ,  H01L25/065

Abstract: A packaged multichip device includes a first IC die with an isolation capacitor utilizing a top metal layer as its top plate and a lower metal layer as its bottom plate. A second IC die has a second isolation capacitor utilizing its top metal layer as its top plate and a lower metal layer as its bottom plate. A first bondwire end is coupled to one top plate and a second bondwire end is coupled to the other top plate. The second bondwire end includes a stitch bond including a wire approach angle not normal to the top plate it is bonded to and is placed so that the stitch bond's center is positioned at least 5% further from an edge of this top plate on a bondwire crossover side compared to a distance of the stitch bond's center from the side opposite the bondwire crossover side.

公开(公告)号：US20190206981A1

公开(公告)日：2019-07-04

申请号：US15857778

申请日：2017-12-29

Applicant: Texas Instruments Incorporated

Inventor： Thomas Dyer Bonifield ,  Kannan Soundarapandian

IPC: H01L49/02 ,  H01G4/30 ,  H01G4/012 ,  H01G4/08 ,  H01L29/06 ,  H01L21/283 ,  H01L21/02 ,  H01L21/762 ,  H01L23/528 ,  H01L23/522 ,  H01L23/60

CPC classification number: H01L28/60 ,  H01G4/012 ,  H01G4/08 ,  H01G4/30 ,  H01L21/02164 ,  H01L21/283 ,  H01L21/762 ,  H01L23/5223 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53257 ,  H01L23/60 ,  H01L24/45 ,  H01L27/0629 ,  H01L29/0649

Abstract: Described examples include a microelectronic device with a high voltage capacitor that includes a high voltage node, a low voltage node, a first dielectric disposed between the low voltage node and the high voltage node, a first conductive plate disposed between the first dielectric and the high voltage node, and a second dielectric disposed between the first conductive plate and the high voltage node.

公开(公告)号：US09006584B2

公开(公告)日：2015-04-14

申请号：US13960406

申请日：2013-08-06

Applicant: Texas Instruments Incorporated

Inventor： Thomas Dyer Bonifield ,  Byron Williams ,  Shrinivasan Jaganathan ,  David Larkin ,  Dhaval Atul Saraiya

IPC: H05K1/16 ,  H05K1/03 ,  H05K1/09 ,  H05K3/00

CPC classification number: H01L23/5223 ,  H01L23/49811 ,  H01L23/5227 ,  H01L23/528 ,  H01L23/53228 ,  H01L23/5329 ,  H01L23/538 ,  H01L23/62 ,  H01L24/05 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/02166 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/48137 ,  H01L2224/48227 ,  H01L2224/48233 ,  H01L2224/48463 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/49177 ,  H01L2924/00014 ,  H01L2924/10253 ,  H01L2924/1205 ,  H01L2924/1206 ,  H01L2924/14335 ,  H05K1/0256 ,  H05K1/0257 ,  H05K1/0262 ,  H05K1/0306 ,  H05K1/0346 ,  H05K1/09 ,  H05K1/112 ,  H05K1/162 ,  H05K1/165 ,  H05K3/0088 ,  H05K3/4688 ,  H05K2201/0154 ,  H05K2201/0175 ,  H05K2201/0191 ,  H05K2201/0195 ,  H05K2201/0746 ,  H05K2201/09409 ,  H05K2201/0949 ,  H05K2201/09672 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099

Abstract: An electronic isolation device is formed on a monolithic substrate and includes a plurality of passive isolation components. The isolation components are formed in three metal levels. The first metal level is separated from the monolithic substrate by an inorganic PMD layer. The second metal level is separated from the first metal level by a layer of silicon dioxide. The third metal level is separated from the second metal level by at least 20 microns of polyimide or PBO. The isolation components include bondpads on the third metal level for connections to other devices. A dielectric layer is formed over the third metal level, exposing the bondpads. The isolation device contains no transistors.

Abstract translation: 电子隔离装置形成在单片基板上并且包括多个被动隔离部件。 隔离元件形成三个金属层。 通过无机PMD层将第一金属层与整体式衬底分离。 第二金属层与第一金属层分开一层二氧化硅。 第三金属层与第二金属层相隔至少20微米的聚酰亚胺或PBO。 隔离组件包括用于连接到其他设备的第三金属层上的焊盘。 在第三金属层上形成介电层，露出粘合垫。 隔离器件不含晶体管。

公开(公告)号：US09006074B2

公开(公告)日：2015-04-14

申请号：US14504938

申请日：2014-10-02

Applicant: Texas Instruments Incorporated

Inventor： Thomas Dyer Bonifield ,  Byron Williams ,  Shrinivasan Jaganathan

IPC: H01L21/28 ,  H01L49/02 ,  H01L29/06 ,  H01L21/768 ,  H01L23/522

CPC classification number: H01L28/60 ,  H01G4/10 ,  H01G4/14 ,  H01G4/206 ,  H01L21/76802 ,  H01L21/76877 ,  H01L23/5222 ,  H01L23/5223 ,  H01L24/05 ,  H01L24/06 ,  H01L27/0288 ,  H01L28/40 ,  H01L29/0642 ,  H01L2224/02166 ,  H01L2224/04042 ,  H01L2224/05093 ,  H01L2224/0603 ,  H01L2224/48463 ,  H01L2924/13091 ,  H01L2924/00

Abstract: An integrated circuit includes isolation capacitors which include a silicon dioxide dielectric layer and a polymer dielectric layer over the layer of silicon dioxide. The silicon dioxide dielectric layer and the polymer dielectric layer extend across the integrated circuit. Top plates of the isolation capacitors have bond pads for wire bonds or bump bonds. Bottom plates of the isolation capacitors are connected to components of the integrated circuit. Other bond pads are connected to components in the integrated circuit through vias through the silicon dioxide dielectric layer and the polymer dielectric layer.

Abstract translation: 集成电路包括隔离电容器，其包括在二氧化硅层上的二氧化硅介电层和聚合物电介质层。 二氧化硅介电层和聚合物电介质层跨过集成电路延伸。 隔离电容器的顶板具有用于引线键合或凸起键的接合焊盘。 隔离电容器的底板连接到集成电路的组件。 其他接合焊盘通过通孔通过二氧化硅介电层和聚合物电介质层连接到集成电路中的组件。