公开(公告)号：US10672631B2

公开(公告)日：2020-06-02

申请号：US16103933

申请日：2018-08-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Chao Mao ,  Chin-Chuan Chang ,  Szu-Wei Lu

IPC: H01L21/67 ,  H01L23/00 ,  H01L21/683 ,  H01L21/687 ,  H01L21/56

Abstract: A method and a system for thinning a substrate are provided. The method includes at least the following steps. A liquid seal is provided at an interface between a chuck and a substrate disposed on the chuck. The substrate is thinned during the liquid seal is provided.

公开(公告)号：US20200035622A1

公开(公告)日：2020-01-30

申请号：US16595741

申请日：2019-10-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Wei Wu ,  Ying-Ching Shih ,  Szu-Wei Lu ,  Jing-Cheng Lin

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/00 ,  H01L23/14 ,  H01L23/48 ,  H01L23/498

Abstract: The present disclosure, in some embodiments, relates to an integrated chip structure. The integrated chip structure has a first conductive layer on a first substrate and a second conductive layer on a second substrate. A bonding structure is disposed between the first conductive layer and the second conductive layer. A support structure is disposed between the first substrate and the second substrate. A passivation layer covers a bottom surface of the first conductive layer and has a lower surface facing an uppermost surface of the support structure.

公开(公告)号：US20200006196A1

公开(公告)日：2020-01-02

申请号：US16431747

申请日：2019-06-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jing-Cheng Lin ,  Szu-Wei Lu

IPC: H01L23/433 ,  H01L21/56 ,  H01L23/00 ,  H01L23/367 ,  H01L25/10 ,  H01L25/18 ,  H01L23/31

Abstract: Semiconductor packages are provided. One of the semiconductor package includes a semiconductor die, a thermal conductive pattern, an encapsulant and a thermal conductive layer. The thermal conductive pattern is disposed aside the semiconductor die. The encapsulant encapsulates the semiconductor die and the thermal conductive pattern. The thermal conductive layer covers a rear surface of the semiconductor die, wherein the thermal conductive pattern is thermally coupled to the semiconductor die through the thermal conductive layer and electrically insulated from the semiconductor die.

公开(公告)号：US20170103954A1

公开(公告)日：2017-04-13

申请号：US15389738

申请日：2016-12-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Wei Wu ,  Ying-Ching Shih ,  Szu-Wei Lu ,  Jing-Cheng Lin

IPC: H01L23/00 ,  H01L23/48 ,  H01L25/065

CPC classification number: H01L23/562 ,  H01L23/145 ,  H01L23/147 ,  H01L23/3171 ,  H01L23/3192 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/92 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/10135 ,  H01L2224/11464 ,  H01L2224/13012 ,  H01L2224/13017 ,  H01L2224/13022 ,  H01L2224/13025 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13562 ,  H01L2224/13582 ,  H01L2224/13644 ,  H01L2224/13664 ,  H01L2224/1403 ,  H01L2224/14181 ,  H01L2224/16146 ,  H01L2224/16235 ,  H01L2224/17181 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81007 ,  H01L2224/81139 ,  H01L2224/81203 ,  H01L2224/81815 ,  H01L2224/92125 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2225/06555 ,  H01L2225/06572 ,  H01L2225/06582 ,  H01L2924/10253 ,  H01L2924/10271 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/1421 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/1437 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/15787 ,  H01L2924/15788 ,  H01L2924/1579 ,  H01L2924/3511 ,  H01L2924/3512 ,  H01L2924/37001 ,  H01L2924/014 ,  H01L2924/00012

Abstract: Some embodiments of the present disclosure relate to a three dimensional integrated circuit (3DIC) structure. The 3DIC structure has a first die and a second die that is bonded to the first die by one or more bonding structures. The one or more bonding structures respectively have a first metal pad arranged on the first die and a second metal pad arranged on the second die. A first plurality of support structures are disposed between the first die and the second die. The first plurality of support structures include polymers and are laterally spaced apart from a closest one of the one or more bonding structures. The first plurality of support structures extend below an upper surface of the second metal pad.

公开(公告)号：US20240371725A1

公开(公告)日：2024-11-07

申请号：US18775879

申请日：2024-07-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Hao Chen ,  Hung-Yu Chen ,  Pu Wang ,  Li-Hui Cheng ,  Szu-Wei Lu

IPC: H01L23/373 ,  H01L21/48 ,  H01L23/04 ,  H01L23/31 ,  H01L23/40

Abstract: A method of forming a semiconductor structure includes: attaching a semiconductor device to a first surface of a substrate; placing a thermal interface material (TIM) film over a first side of the semiconductor device distal from the substrate, where the TIM film is pre-formed before the placing, where after the placing, a peripheral portion of the TIM film extends laterally beyond sidewalls of the semiconductor device; and attaching a lid to the first surface of the substrate to form an enclosed space between the lid and the substrate, where after attaching the lid, the semiconductor device and the TIM film are disposed in the enclosed space, where a first side of the TIM film distal from the substrate contacts the lid.

公开(公告)号：US20240222242A1

公开(公告)日：2024-07-04

申请号：US18609836

申请日：2024-03-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shang-Yun Hou ,  Hsien-Pin Hu ,  Sao-Ling Chiu ,  Wen-Hsin Wei ,  Ping-Kang Huang ,  Chih-Ta Shen ,  Szu-Wei Lu ,  Ying-Ching Shih ,  Wen-Chih Chiou ,  Chi-Hsi Wu ,  Chen-Hua Yu

IPC: H01L23/498 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/538

CPC classification number: H01L23/49816 ,  H01L21/4853 ,  H01L21/56 ,  H01L23/3121 ,  H01L23/49861 ,  H01L24/13 ,  H01L23/5385 ,  H01L2224/023 ,  H01L2225/107

Abstract: A semiconductor structure includes a first interposer; a second interposer laterally adjacent to the first interposer, where the second interposer is spaced apart from the first interposer; and a first die attached to a first side of the first interposer and attached to a first side of the second interposer, where the first side of the first interposer and the first side of the second interposer face the first die.

公开(公告)号：US20240128157A9

公开(公告)日：2024-04-18

申请号：US17872750

申请日：2022-07-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chin-Chuan Chang ,  Szu-Wei Lu ,  Chen-Hua Yu

IPC: H01L23/48 ,  H01L21/56 ,  H01L21/768 ,  H01L23/00 ,  H01L23/498 ,  H01L25/065 ,  H01L25/10

CPC classification number: H01L23/481 ,  H01L21/561 ,  H01L21/563 ,  H01L21/76898 ,  H01L23/49816 ,  H01L23/49833 ,  H01L23/49838 ,  H01L24/08 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/94 ,  H01L24/96 ,  H01L24/97 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/105 ,  H01L23/49822 ,  H01L24/48 ,  H01L2224/08235 ,  H01L2224/16148 ,  H01L2224/32145 ,  H01L2224/48229 ,  H01L2224/73204 ,  H01L2224/95001 ,  H01L2225/06513 ,  H01L2225/06524 ,  H01L2225/06544 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/182 ,  H01L2924/37001

Abstract: A method includes forming a set of through-vias in a substrate, the set of through-vias partially penetrating a thickness of the substrate. First connectors are formed over the set of through-vias on a first side of the substrate. The first side of the substrate is attached to a carrier. The substrate is thinned from the second side to expose the set of through-vias. Second connectors are formed over the set of through-vias on the second side of the substrate. A device die is bonded to the second connectors. The substrate is singulated into multiple packages.

公开(公告)号：US20240077669A1

公开(公告)日：2024-03-07

申请号：US18111290

申请日：2023-02-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Jiun Yi Wu ,  Szu-Wei Lu

IPC: G02B6/12 ,  G02B6/26 ,  G02B6/42

CPC classification number: G02B6/12004 ,  G02B6/262 ,  G02B6/4239 ,  G02B2006/12102 ,  G02B2006/12104

Abstract: An embodiment is a package including a package substrate and a package component bonded to the package substrate, the package component including an interposer, an optical die bonded to the interposer, the optical die including an optical coupler, an integrated circuit die bonded to the interposer adjacent the optical die, a lens adapter adhered to the optical die with a first optical glue, a mirror adhered to the lens adapter with a second optical glue, the mirror being aligned with the optical coupler of the optical die, and an optical fiber on the lens adapter, a first end of the optical fiber facing the mirror, the optical fiber being configured such that an optical data path extends from the first end of the optical fiber through the mirror, the second optical glue, the lens adapter, and the first optical glue to the optical coupler of the optical die.

公开(公告)号：US20240006270A1

公开(公告)日：2024-01-04

申请号：US17856689

申请日：2022-07-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hung-Yi Kuo ,  Chen-Hua Yu ,  Kuo-Chung Yee ,  Cheng-Chieh Hsieh ,  Chung-Ju Lee ,  Szu-Wei Lu

IPC: H01L23/473 ,  H01L23/31 ,  H01L25/18 ,  H01L25/065 ,  H01L25/00 ,  H01L21/56

CPC classification number: H01L23/473 ,  H01L23/3135 ,  H01L25/18 ,  H01L25/0655 ,  H01L25/50 ,  H01L21/563 ,  H01L24/94

Abstract: In an embodiment, a package includes an interposer; a first integrated circuit device attached to the interposer, wherein the first integrated circuit device includes a die and a heat dissipation structure, the die having an active surface facing the interposer and an inactive surface opposite to the active surface, the heat dissipation structure attached to the inactive surface of the die and including a plurality of channels recessed from a first surface of the heat dissipation structure, the first surface of the heat dissipation structure facing away from the die; and an encapsulant disposed on the interposer and laterally around the die and the heat dissipation structure, wherein a top surface of the encapsulant is coplanar with the top surface of the heat dissipation structure.

公开(公告)号：US11830821B2

公开(公告)日：2023-11-28

申请号：US17150300

申请日：2021-01-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Hao Chen ,  Pu Wang ,  Li-Hui Cheng ,  Szu-Wei Lu

IPC: H01L23/538 ,  H01L25/10 ,  H01L23/00 ,  H01L23/31 ,  H01L21/683 ,  H01L21/48 ,  H01L21/56 ,  H01L25/00 ,  H01L25/065

CPC classification number: H01L23/5389 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3128 ,  H01L23/5383 ,  H01L23/5386 ,  H01L24/19 ,  H01L24/20 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2221/68372 ,  H01L2224/214 ,  H01L2225/0651 ,  H01L2225/1035 ,  H01L2225/1058

Abstract: Semiconductor devices and methods of manufacture are provided, in which an adhesive is removed from a semiconductor die embedded within an encapsulant, and an interface material is utilized to remove heat from the semiconductor device. The removal of the adhesive leaves behind a recess adjacent to a sidewall of the semiconductor, and the recess is filled.