公开(公告)号：US12002799B2

公开(公告)日：2024-06-04

申请号：US17814766

申请日：2022-07-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Hung-Yi Kuo ,  Chung-Shi Liu ,  Hao-Yi Tsai ,  Cheng-Chieh Hsieh ,  Tsung-Yuan Yu ,  Ming Hung Tseng

IPC: H01L23/498 ,  H01L21/56 ,  H01L21/66 ,  H01L21/768 ,  H01L23/00 ,  H01L25/00 ,  H01L25/065 ,  H01L25/18

CPC classification number: H01L25/50 ,  H01L21/561 ,  H01L21/563 ,  H01L21/76898 ,  H01L22/14 ,  H01L22/32 ,  H01L24/03 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/0231 ,  H01L2224/02331 ,  H01L2224/02379 ,  H01L2224/13024 ,  H01L2224/16145 ,  H01L2224/17181 ,  H01L2225/06513 ,  H01L2225/06541

Abstract: A method includes bonding a first device die to a second device die, encapsulating the first device die in a first encapsulant, performing a backside grinding process on the second device die to reveal through-vias in the second device die, and forming first electrical connectors on the second device die to form a package. The package includes the first device die and the second device die. The method further includes encapsulating the first package in a second encapsulant, and forming an interconnect structure overlapping the first package and the second encapsulant. The interconnect structure comprises second electrical connectors.

公开(公告)号：US11984374B2

公开(公告)日：2024-05-14

申请号：US17650932

申请日：2022-02-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jiun Yi Wu ,  Chen-Hua Yu ,  Chung-Shi Liu

IPC: H01L23/31 ,  H01L21/56

CPC classification number: H01L23/3114 ,  H01L21/568

Abstract: A method includes placing a package component over a carrier. The package component includes a device die. A core frame is placed over the carrier. The core frame forms a ring encircling the package component. The method further includes encapsulating the core frame and the package component in an encapsulant, forming redistribution lines over the core frame and the package component, and forming electrical connectors over and electrically coupling to the package component through the redistribution lines.

公开(公告)号：US20240153881A1

公开(公告)日：2024-05-09

申请号：US18402061

申请日：2024-01-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Tzuan-Horng Liu ,  Ming-Fa Chen ,  Chao-Wen Shih ,  Sung-Feng Yeh

IPC: H01L23/538 ,  H01L21/48 ,  H01L21/56 ,  H01L21/66 ,  H01L21/78 ,  H01L23/00 ,  H01L23/31 ,  H01L23/367 ,  H01L25/10

CPC classification number: H01L23/5389 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/4871 ,  H01L21/565 ,  H01L21/78 ,  H01L22/12 ,  H01L23/3128 ,  H01L23/3675 ,  H01L23/5383 ,  H01L23/5386 ,  H01L24/19 ,  H01L24/20 ,  H01L25/105 ,  H01L2224/214 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/19103

Abstract: A method of forming semiconductor structure includes attaching backsides of top dies to a front side of a bottom wafer, the bottom wafer comprising a plurality of bottom dies; forming first conductive pillars on the front side of the bottom wafer adjacent to the top dies; forming a first dielectric material on the front side of the bottom wafer around the top dies and around the first conductive pillars; and dicing the bottom wafer to form a plurality of structures, each of the plurality of structures comprising at least one of the top dies and at least one of the bottom dies.

公开(公告)号：US11973055B2

公开(公告)日：2024-04-30

申请号：US17869977

申请日：2022-07-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yung-Chi Lin ,  Tsang-Jiuh Wu ,  Wen-Chih Chiou ,  Chen-Hua Yu

IPC: H01L25/065 ,  B23K26/362 ,  H01L21/3213 ,  H01L23/00 ,  H01L25/00

CPC classification number: H01L24/80 ,  B23K26/362 ,  H01L21/32136 ,  H01L24/03 ,  H01L24/08 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/08146 ,  H01L2224/80201 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2924/37001

Abstract: In an embodiment, a device includes: a first wafer including a first substrate and a first interconnect structure, a sidewall of the first interconnect structure forming an obtuse angle with a sidewall of the first substrate; and a second wafer bonded to the first wafer, the second wafer including a second substrate and a second interconnect structure, the sidewall of the first substrate being laterally offset from a sidewall of the second substrate and a sidewall of the second interconnect structure.

公开(公告)号：US20240136203A1

公开(公告)日：2024-04-25

申请号：US18401811

申请日：2024-01-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  An-Jhih Su ,  Wei-Yu Chen

IPC: H01L21/56 ,  G02B6/122 ,  G02B6/136 ,  G02B6/30 ,  H01L23/00 ,  H01L23/31 ,  H01L23/522 ,  H01L23/528 ,  H01L23/538

CPC classification number: H01L21/561 ,  G02B6/1225 ,  G02B6/136 ,  G02B6/30 ,  H01L23/3121 ,  H01L23/3171 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/5383 ,  H01L23/5386 ,  H01L24/09 ,  H01L24/17 ,  H01L24/32 ,  H01L24/73 ,  H01L2224/0231 ,  H01L2224/02373 ,  H01L2924/1433

Abstract: A method includes placing an electronic die and a photonic die over a carrier, with a back surface of the electronic die and a front surface of the photonic die facing the carrier. The method further includes encapsulating the electronic die and the photonic die in an encapsulant, planarizing the encapsulant until an electrical connector of the electronic die and a conductive feature of the photonic die are revealed, and forming redistribution lines over the encapsulant. The redistribution lines electrically connect the electronic die to the photonic die. An optical coupler is attached to the photonic die. An optical fiber attached to the optical coupler is configured to optically couple to the photonic die.

公开(公告)号：US20240128157A9

公开(公告)日：2024-04-18

申请号：US17872750

申请日：2022-07-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chin-Chuan Chang ,  Szu-Wei Lu ,  Chen-Hua Yu

IPC: H01L23/48 ,  H01L21/56 ,  H01L21/768 ,  H01L23/00 ,  H01L23/498 ,  H01L25/065 ,  H01L25/10

CPC classification number: H01L23/481 ,  H01L21/561 ,  H01L21/563 ,  H01L21/76898 ,  H01L23/49816 ,  H01L23/49833 ,  H01L23/49838 ,  H01L24/08 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/94 ,  H01L24/96 ,  H01L24/97 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/105 ,  H01L23/49822 ,  H01L24/48 ,  H01L2224/08235 ,  H01L2224/16148 ,  H01L2224/32145 ,  H01L2224/48229 ,  H01L2224/73204 ,  H01L2224/95001 ,  H01L2225/06513 ,  H01L2225/06524 ,  H01L2225/06544 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/182 ,  H01L2924/37001

Abstract: A method includes forming a set of through-vias in a substrate, the set of through-vias partially penetrating a thickness of the substrate. First connectors are formed over the set of through-vias on a first side of the substrate. The first side of the substrate is attached to a carrier. The substrate is thinned from the second side to expose the set of through-vias. Second connectors are formed over the set of through-vias on the second side of the substrate. A device die is bonded to the second connectors. The substrate is singulated into multiple packages.

公开(公告)号：US20240105632A1

公开(公告)日：2024-03-28

申请号：US18525966

申请日：2023-12-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsien-Pin Hu ,  Chen-Hua Yu ,  Ming-Fa Chen ,  Jing-Cheng Lin ,  Jiun Ren Lai ,  Yung-Chi Lin

IPC: H01L23/538 ,  H01L21/56 ,  H01L21/683 ,  H01L23/00 ,  H01L23/14 ,  H01L23/31 ,  H01L23/498

CPC classification number: H01L23/5389 ,  H01L21/563 ,  H01L21/6835 ,  H01L23/147 ,  H01L23/3121 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L24/81 ,  H01L24/97 ,  H01L24/16 ,  H01L25/0652

Abstract: A device includes an interposer, which includes a substrate having a top surface. An interconnect structure is formed over the top surface of the substrate, wherein the interconnect structure includes at least one dielectric layer, and metal features in the at least one dielectric layer. A plurality of through-substrate vias (TSVs) is in the substrate and electrically coupled to the interconnect structure. A first die is over and bonded onto the interposer. A second die is bonded onto the interposer, wherein the second die is under the interconnect structure.

公开(公告)号：US20240103218A1

公开(公告)日：2024-03-28

申请号：US18153661

申请日：2023-01-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsing-Kuo Hsia ,  Jui Lin Chao ,  Chen-Hua Yu ,  Chih-Hao Yu ,  Shih-Peng Tai

IPC: G02B6/122 ,  G02B6/13

CPC classification number: G02B6/122 ,  G02B6/13 ,  G02B2006/12121

Abstract: Optical devices and methods of manufacture are presented in which a laser die or other heterogeneous device is embedded within an optical device and evanescently coupled to other devices. The evanescent coupling can be performed either from the laser die to a waveguide, to an external cavity, to an external coupler, or to an interposer substrate.

公开(公告)号：US20240088123A1

公开(公告)日：2024-03-14

申请号：US18518187

申请日：2023-11-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Yung-Chi Lin ,  Wen-Chih Chiou

IPC: H01L25/00 ,  H01L23/00 ,  H01L25/065 ,  H01L25/18

CPC classification number: H01L25/50 ,  H01L24/33 ,  H01L24/83 ,  H01L24/92 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/08146 ,  H01L2224/33181 ,  H01L2224/33505 ,  H01L2224/33519 ,  H01L2224/80006 ,  H01L2224/8083 ,  H01L2224/83005 ,  H01L2224/8383 ,  H01L2224/83896 ,  H01L2224/92142 ,  H01L2225/06541 ,  H01L2225/06589

Abstract: A device package includes a first die directly bonded to a second die at an interface, wherein the interface comprises a conductor-to-conductor bond. The device package further includes an encapsulant surrounding the first die and the second die and a plurality of through vias extending through the encapsulant. The plurality of through vias are disposed adjacent the first die and the second die. The device package further includes a plurality of thermal vias extending through the encapsulant and a redistribution structure electrically connected to the first die, the second die, and the plurality of through vias. The plurality of thermal vias is disposed on a surface of the second die and adjacent the first die.

公开(公告)号：US20240088077A1

公开(公告)日：2024-03-14

申请号：US18517774

申请日：2023-11-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd

Inventor： Chen-Hua Yu ,  Kuo-Chung Yee

IPC: H01L23/00 ,  H01L23/48

CPC classification number: H01L24/05 ,  H01L23/481 ,  H01L24/03 ,  H01L24/19 ,  H01L24/20 ,  H01L24/82 ,  H01L2224/05009

Abstract: A method includes forming integrated circuits on a front side of a first chip, performing a backside grinding on the first chip to reveal a plurality of through-vias in the first chip, and forming a first bridge structure on a backside of the first chip using a damascene process. The bridge structure has a first bond pad, a second bond pad, and a conductive trace electrically connecting the first bond pad to the second bond pad. The method further includes bonding a second chip and a third chip to the first chip through face-to-back bonding. A third bond pad of the second chip is bonded to the first bond pad of the first chip. A fourth bond pad of the third chip is bonded to the second bond pad of the first chip.