公开(公告)号：US06533906B2

公开(公告)日：2003-03-18

申请号：US09795479

申请日：2001-03-01

申请人： Takashi Kawakubo ,  Takaaki Yasumoto ,  Kazuhide Abe ,  Naoko Yanase

发明人： Takashi Kawakubo ,  Takaaki Yasumoto ,  Kazuhide Abe ,  Naoko Yanase

IPC分类号： C23C1434

CPC分类号： C23C14/345 ,  C23C14/0068 ,  C23C14/088 ,  C23C14/3407 ,  C23C14/352 ,  C30B23/02 ,  C30B29/22 ,  C30B29/32 ,  H01L21/02197 ,  H01L21/02266 ,  H01L21/31691 ,  H01L28/55

摘要： A method of manufacturing an epitaxially-strained lattice film of an oxide, in which epitaxially-strained lattices having a good crystalline property are formed by applying RF power to a substrate holder and irradiating positive ions having a moderate energy while preventing damage to the strained lattice film to be stacked by oxygen negative ions. This method simultaneously overcomes both the problem of damage to the film by irradiation of oxygen negative ions, which is peculiar to sputtering of oxides, and the problem of failure to strain due to relaxation of the strain during deposition.

摘要翻译： 制造具有良好结晶特性的外延应变晶格的氧化物的外延应变晶格膜的方法通过向衬底保持器施加RF功率并照射具有中等能量的正离子而形成，同时防止对应变晶格的损伤 膜由氧负离子堆叠。 该方法同时克服了通过照射氧负离子（这是氧化物溅射所特有的）对膜的损坏的问题，以及由于沉积期间的应变松弛而导致的不能应变的问题。

公开(公告)号：US20050104204A1

公开(公告)日：2005-05-19

申请号：US10951868

申请日：2004-09-29

申请人： Takashi Kawakubo ,  Takaaki Yasumoto ,  Kazuhiko Itaya

发明人： Takashi Kawakubo ,  Takaaki Yasumoto ,  Kazuhiko Itaya

IPC分类号： H01L23/12 ,  H01L21/48 ,  H01L21/60 ,  H01L23/055 ,  H01L23/14 ,  H01L23/498 ,  H01L25/065 ,  H01L25/07 ,  H01L25/18 ,  H03H3/02 ,  H03H9/02 ,  H03H9/10 ,  H03H9/17 ,  H01L23/34

CPC分类号： B81C1/00301 ,  B81B2207/096 ,  H01L21/486 ,  H01L23/055 ,  H01L23/147 ,  H01L23/49827 ,  H01L24/29 ,  H01L24/81 ,  H01L24/83 ,  H01L24/94 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/05624 ,  H01L2224/14051 ,  H01L2224/16 ,  H01L2224/16235 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/81801 ,  H01L2224/83191 ,  H01L2224/838 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0781 ,  H01L2924/15313 ,  H01L2924/163 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/30107 ,  H03H9/0547 ,  H03H9/105 ,  H01L2924/00014

摘要： A wafer-level package comprises: a first substrate; an electric element provided on the first substrate; a second substrate; an internal electrode pad; a well; and an external electrode pad. The second substrate is opposed to the first substrate with a predetermined gap therebetween. The electric element is provided between the first and second substrates. The internal electrode pad extends onto a first surface of one of the first and the second substrates. The inner electrode pad is connected to the electric element. The well penetrates the one of the first and the second substrates to the internal electrode. The external electrode pad is provided on a second surface of the one of the first and the second substrates and extends onto an inner wall of the well and being connected with the internal electrode pad.

摘要翻译： 晶片级封装包括：第一衬底; 设置在所述第一基板上的电气元件; 第二基板; 内部电极焊盘; 一口井; 和外部电极焊盘。 第二基板与其间具有预定间隙的第一基板相对。 电元件设置在第一和第二基板之间。 内部电极焊盘延伸到第一和第二衬底之一的第一表面上。 内部电极焊盘连接到电气元件。 井将第一和第二基板中的一个穿透到内部电极。 外部电极焊盘设置在第一和第二基板之一的第二表面上并且延伸到阱的内壁并与内部电极焊盘连接。

公开(公告)号：US5041700A

公开(公告)日：1991-08-20

申请号：US588928

申请日：1990-09-27

申请人： Kiyoshi Iyogi ,  Takaaki Yasumoto ,  Toshirou Yanazawa ,  Nobuo Iwase

发明人： Kiyoshi Iyogi ,  Takaaki Yasumoto ,  Toshirou Yanazawa ,  Nobuo Iwase

IPC分类号： C04B37/02 ,  C04B41/52 ,  C04B41/89 ,  H01L23/15 ,  H01L23/498 ,  H05K1/03 ,  H05K3/38

CPC分类号： C04B41/009 ,  C04B41/52 ,  C04B41/89 ,  H01L23/15 ,  H01L23/49866 ,  H01L2924/0002 ,  H01L2924/15312 ,  H05K1/0306 ,  H05K3/38

摘要： A circuit board includes an aluminum nitride substrate, and a circuit pattern formed on the substrate and having a multilayered structure in which a metal oxynitride layer represented by formula Al.sub.u Ml.sub.v M2.sub.x O.sub.y N.sub.z (wherein M1 represents a metal selected from the group consisting of Ti, Cr, Ta, and Zr, M2 represents a metal selected from the group consisting of Ni, Pt, Pd, W, Nb, and Mo, u represents 3 to 50 atm %, v represents 3 to 78 atm %, x represents 0 to 50 atm %, y represents 0.005 to 25 atm %, and z represents 5 to 70 atm %), a bonding layer consisting essentially of a metal represented by M1, a barrier layer consisting essentially of a metal represented by M2, and a conductor layer consisting essentially of Au are stacked in the order named.

摘要翻译： 电路板包括氮化铝衬底和形成在衬底上并具有多层结构的电路图案，其中由式AluMlvM2xOyNz表示的金属氧氮化物层（其中M1表示选自Ti，Cr，Ta， Zr，M2表示选自Ni，Pt，Pd，W，Nb和Mo的金属，u表示3〜50atm％，v表示3〜78atm％，x表示0〜50atm％ y表示0.005〜25atm％，z表示5〜70atm％），基本上由M1表示的金属构成的接合层，基本上由M2表示的金属构成的阻挡层和基本上由Au构成的导体层 按照命名的顺序堆叠。

公开(公告)号：US4963701A

公开(公告)日：1990-10-16

申请号：US300944

申请日：1989-01-24

申请人： Takaaki Yasumoto ,  Nobuo Iwase

发明人： Takaaki Yasumoto ,  Nobuo Iwase

IPC分类号： H01L23/15 ,  H01L23/498 ,  H05K1/03 ,  H05K3/38

CPC分类号： H05K3/388 ,  H01L23/15 ,  H01L23/49866 ,  H01L2924/0002 ,  H05K1/0306

摘要： Disclosed is an aluminum nitride thin film circuit board having an aluminum nitride substrate and a conductive thin film pattern formed on the substrate. The conductive thin film pattern has a multi-layer structure selected from the group consisting of Ti/Ni/Au, Ti/Pd/Au, Ti/Pt/Au, Ni/Au, Cr/Au, and Cr/Cu/Au, and a boundary layer of Al-N-M-O (M is Ti, Ni, or Cr) is formed between the substrate and the conductive thin film pattern. Since the boundary layer is formed, bonding properties between the substrate and the conductive thin film pattern are improved. In particular, when the boundary layer contains 0.02 to 30 atomic % of oxygen, a higher bonding strength can be obtained.

公开(公告)号：US4882652A

公开(公告)日：1989-11-21

申请号：US115908

申请日：1987-11-02

申请人： Osamu Furukawa ,  Mitsuo Harata ,  Takaaki Yasumoto ,  Motomasa Imai

发明人： Osamu Furukawa ,  Mitsuo Harata ,  Takaaki Yasumoto ,  Motomasa Imai

IPC分类号： H01G4/12 ,  C04B35/00 ,  C04B35/46 ,  C04B35/499 ,  H01B3/12

CPC分类号： C04B35/499

摘要： When a portion of the Pb of a Pb(Zn.sub.1/3 Nb.sub.2/3)O.sub.3 -based ceramic composition within the region bounded by lines connecting a, b, c, d, e and f points in the ternary composition diagram of the accompanying FIG. 1 is substituted by a small amount of Ca, a high dielectric constant type ceramic composition is obtained which has a small temperature coefficient of dielectric constant and which is effective as a material for multilayer ceramic capacitors.

摘要翻译： 当Pb（Zn1 / 3Nb2 / 3）O3系陶瓷组合物的Pb的一部分在连接a，b，c，d，e和f的线所界定的区域内时，在图3的三元组成图中指出。 1被少量的Ca代替，获得了介电常数较小温度系数高的介电常数型陶瓷组合物，作为多层陶瓷电容器的材料是有效的。

公开(公告)号：US4772985A

公开(公告)日：1988-09-20

申请号：US98240

申请日：1987-09-18

申请人： Takaaki Yasumoto ,  Osamu Furukawa ,  Nobuo Iwase ,  Mitsuo Harata ,  Masao Segawa

发明人： Takaaki Yasumoto ,  Osamu Furukawa ,  Nobuo Iwase ,  Mitsuo Harata ,  Masao Segawa

IPC分类号： C04B35/497 ,  C04B35/499 ,  H01G4/12 ,  H01G4/30 ,  C04B35/46 ,  H01G4/10 ,  H01G7/00

CPC分类号： C04B35/499 ,  C04B35/497 ,  H01G4/129 ,  H01G4/30 ,  Y10T29/435

摘要： Disclosed is a thick film capacitor comprising (a) a sintered layer of a ferroelectric material mainly consisting of one or more ferroelectric inorganic compounds having a perovskite structure and an inorganic binder having a eutectic composition which experiences a liquid phase at a temperature lower than the sintering temperature of the ferroelectric inorganic compounds, and (b) at least two electrodes formed on both surfaces of the sintered layer of the ferroelectric material. In the thick film capacitor of this invention, the perovskite structure of the ferroelectric inorganic compounds is not destroyed upon sintering. Therefore, a high degree of sintering, a good dielectric characteristic and high moisture and migration resistances can be obtained.

摘要翻译： 公开了一种厚膜电容器，其包括（a）主要由具有钙钛矿结构的一种或多种铁电无机化合物和具有在低于烧结温度的温度下经历液相的共晶组成的无机粘合剂的铁电体材料的烧结层 铁电体无机化合物的温度，（b）形成在铁电体的烧结层的两面的至少两个电极。 在本发明的厚膜电容器中，铁电体无机化合物的钙钛矿结构在烧结时不破坏。 因此，可以获得高度的烧结，良好的介电特性和高的湿度和迁移电阻。

公开(公告)号：US20070065639A1

公开(公告)日：2007-03-22

申请号：US11443282

申请日：2006-05-31

申请人： Atsuko Iida ,  Koichi Ishii ,  Yasushi Shinjiyo ,  Takaaki Yasumoto ,  Naoko Yanase

发明人： Atsuko Iida ,  Koichi Ishii ,  Yasushi Shinjiyo ,  Takaaki Yasumoto ,  Naoko Yanase

IPC分类号： G11B5/64

CPC分类号： H05K3/246 ,  G03G15/224 ,  G03G15/6585 ,  G03G15/6591 ,  H05K1/095 ,  H05K3/1266 ,  H05K3/182 ,  H05K2201/0212 ,  H05K2201/0347 ,  H05K2203/0517 ,  H05K2203/095 ,  Y10T428/24355

摘要： A circuit board includes a substrate, a nonconductive resin layer selectively formed on the substrate and containing fine metal particles, and a conductive metal layer formed on the resin layer, in contact with the fine metal particles which are exposed from the resin layer. A surface of the resin layer has irregularities, in an interface between the resin layer and the conductive metal layer. In a roughness curve of a section of the resin layer, in a case of an wavelength (λc) at the boundary of a roughness component and a waviness component is 1 μm, a maximum height (Rz) per reference length (1r) of 1 μm is 20 nm to 500 nm.

摘要翻译： 电路板包括基板，选择性地形成在基板上并且含有金属微粒的非导电树脂层，以及形成在树脂层上的与从树脂层露出的金属微粒接触的导电金属层。 在树脂层和导电金属层之间的界面处，树脂层的表面具有凹凸。 在树脂层的一部分的粗糙度曲线中，在粗糙度成分的边界处的波长（lambdac）和波纹成分为1μm的情况下，每个参考长度（1 r）的最大高度（Rz） 1μm为20nm〜500nm。

公开(公告)号：US5070393A

公开(公告)日：1991-12-03

申请号：US454903

申请日：1989-12-22

申请人： Noriko Nakagawa ,  Takaaki Yasumoto ,  Toshio Nakai

发明人： Noriko Nakagawa ,  Takaaki Yasumoto ,  Toshio Nakai

IPC分类号： H01L21/60 ,  H01L23/15

CPC分类号： H01L23/15 ,  H01L2224/48227 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/01014 ,  H01L2924/0102 ,  H01L2924/01039 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/10253 ,  H01L2924/15153 ,  H01L2924/1517

摘要： An overcoat layer possessing an insulating property is formed only in the necessary part on a ceramic substrate formed of a sintered aluminum nitride. An aluminum nitride substrate for the formation of a thin-film conductor layer thereon is composed of the ceramic substrate and the overcoat layer both mentioned above. The overcoat layer serves the purpose of alleviating the jogging contour of the surface of the sintered aluminum nitrate and enhancing the smoothness of this surface. A semiconductor device is produced by forming a thin-film conductor layer destined to constitute a circuit part on the overcoat layer. The excellence in the surface smoothness of the overcoat layer enhances the reliability of the thin-film conductor layer in a great measure. Semiconductor elements are mounted on the exposed part of the sintered aluminum nitride where the overcoat layer is absent.

摘要翻译： 仅在由烧结氮化铝形成的陶瓷基板上的必要部分形成具有绝缘性的外涂层。 用于在其上形成薄膜导体层的氮化铝衬底由上述陶瓷衬底和外涂层组成。 外涂层的目的是减轻烧结的硝酸铝的表面的慢跑轮廓并提高该表面的平滑度。 通过在外涂层上形成目的地构成电路部分的薄膜导体层来制造半导体器件。 外涂层的表面平滑度的优异性能很大程度上提高了薄膜导体层的可靠性。 半导体元件安装在不存在外涂层的烧结氮化铝的暴露部分上。

公开(公告)号：US5907187A

公开(公告)日：1999-05-25

申请号：US502587

申请日：1995-07-14

申请人： Kaoru Koiwa ,  Koji Yamakawa ,  Kiyoshi Iyogi ,  Takaaki Yasumoto ,  Nobuo Iwase

发明人： Kaoru Koiwa ,  Koji Yamakawa ,  Kiyoshi Iyogi ,  Takaaki Yasumoto ,  Nobuo Iwase

IPC分类号： H01L23/498 ,  H05K3/34 ,  H01L23/48 ,  H01L23/06 ,  H01L23/52 ,  H01L29/40

CPC分类号： H05K3/3436 ,  H01L23/49816 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48472 ,  H01L2224/73265 ,  H01L2924/15311 ,  H01L2924/30107 ,  H01L2924/3011 ,  H05K2201/094 ,  H05K2201/10992 ,  H05K2203/041 ,  H05K3/3463 ,  H05K3/3484 ,  Y02P70/613

摘要： In such electronic components as semiconductor packages and semiconductor chips which are possessed of groups of connecting bumps as input and output terminals, the groups of connecting bumps comprise not less than two kinds of connecting bumps different in melting point or not less than two kinds of connecting bumps different in mechanical strength. The groups of connecting bumps comprise connecting bumps made of high temperature solder or connecting bumps made of a high strength In type solder in the part of formation thereof. The connecting bumps made of high temperature solder are not directly affected by the influence of displacement because they retain the shape of a ball even after the step of connection such as solder reflow. The connecting bumps made of In type solder form connecting parts of high strength. These groups of connecting bumps contribute to exalt the reliability of the connecting parts without decreasing the number of input and output terminals.

摘要翻译： 在具有作为输入和输出端子的连接凸块组的半导体封装和半导体芯片的这种电子部件中，连接凸块组包括不少于两种不同熔点的连接凸块或不少于两种连接 不同的机械强度凸起。 连接凸块的组包括在其形成部分中由高温焊料或由高强度In型焊料制成的连接凸块形成的连接凸块。 由高温焊料制成的连接凸块不受位移影响的直接影响，因为即使在诸如焊料回流的连接步骤之后，它们保持了球的形状。 由In型焊料形成的连接凸块形成高强度的连接部件。 这些连接凸块组有助于提高连接部件的可靠性，而不会减少输入和输出端子的数量。

公开(公告)号：US5821627A

公开(公告)日：1998-10-13

申请号：US962882

申请日：1997-11-05

申请人： Miki Mori ,  Yukio Kizaki ,  Takaaki Yasumoto ,  Koji Yamakawa ,  Masayuki Saito ,  Tatsuro Uchida ,  Takasi Togasaki ,  Takashi Yebisuya ,  Taijun Murakami

发明人： Miki Mori ,  Yukio Kizaki ,  Takaaki Yasumoto ,  Koji Yamakawa ,  Masayuki Saito ,  Tatsuro Uchida ,  Takasi Togasaki ,  Takashi Yebisuya ,  Taijun Murakami

IPC分类号： H05K3/32 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H05K3/328 ,  H01L2224/1134 ,  H01L2224/13109 ,  H01L2224/13144 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48227 ,  H01L2924/01004 ,  H01L2924/01019 ,  H01L2924/01025 ,  H01L2924/01039 ,  H01L2924/01046 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/16152 ,  H01L2924/19041 ,  H05K2201/10636 ,  H05K2201/10734 ,  Y02P70/611

摘要： An electronic circuit device includes a substrate, a wiring layer formed on the surface of the substrate and essentially consisting of at least one metal selected from the group consisting of gold, copper, tin, and aluminum, a bump formed on the wiring layer and essentially consisting of at least one metal selected from the group consisting of gold, copper, and aluminum, and a micro electronic element formed on the bump, wherein solid-phase diffusion bonding is performed at least either between the wiring layer and the bump or between the bump and an electrode of the micro electronic element.

摘要翻译： 电子电路装置包括：基板，形成在基板的表面上的基本上由布线层形成的凸块和基本上由金，铜，锡和铝组成的组中的至少一种金属组成的布线层; 由选自金，铜和铝的至少一种金属和形成在凸块上的微电子元件组成，其中固定相扩散接合至少在布线层和凸块之间或者在 凸块和微电子元件的电极。