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115 条记录 (耗时 0.026 秒)

    Apparatus and methods to clean copper contamination on wafer edge
    31.
    发明授权
    Apparatus and methods to clean copper contamination on wafer edge 失效
    清洁晶圆边缘铜污染的设备和方法

    公开(公告)号：US06813796B2

    公开(公告)日：2004-11-09

    申请号：US10357137

    申请日：2003-02-03

    申请人： Sudipto Ranendra Roy ,  Subhash Gupta ,  Simon Chooi ,  Xu Yi ,  Yakub Aliyu ,  Mei Sheng Zhou ,  John Leonard Sudijono ,  Paul Kwok Keung Ho

    发明人： Sudipto Ranendra Roy ,  Subhash Gupta ,  Simon Chooi ,  Xu Yi ,  Yakub Aliyu ,  Mei Sheng Zhou ,  John Leonard Sudijono ,  Paul Kwok Keung Ho

    IPC分类号： B08B700

    CPC分类号： B08B1/04 ,  B08B3/04

    摘要： A new apparatus is provided that can be applied to clean outer edges of semiconductor substrates. Under the first embodiment of the invention, a brush is mounted on the surface of the substrate around the periphery of the substrate, chemicals are fed to the surface that is being cleaned by means of a hollow core on which the cleaning brush is mounted. The surface that is being cleaned rotates at a relatively high speed thereby causing the chemicals that are deposited on this surface (by the brush) to remain in the edge of the surface. Under the second embodiment of the invention, a porous roller is mounted between a chemical reservoir and the surface that is being cleaned, the surface that is being cleaned rotates at a relatively high speed. The chemicals that are deposited by the interfacing porous roller onto the surface that is being cleaned therefore remain at the edge of this surface thereby causing optimum cleaning action of the edge of the surface. After contaminants have been removed in this manner from the surface, the surface can be further cleaned by applying DI water.

    摘要翻译： 提供了可用于清洁半导体衬底的外边缘的新设备。 在本发明的第一实施例中，刷子安装在基板周围的基板的表面上，化学品通过其上安装有清洁刷的中空芯被供给到被清洁的表面。 待清洁的表面以相对高的速度旋转，从而使沉积在该表面（由刷子）上的化学物质残留在表面的边缘。 在本发明的第二实施例中，多孔辊安装在化学容器和待清洁的表面之间，待清洁的表面以相对较高的速度旋转。 因此，由界面多孔辊沉积在待清洗的表面上的化学物质保留在该表面的边缘，从而引起表面边缘的最佳清洁作用。 污染物以这种方式从表面除去后，可以通过加入去离子水进一步清洁表面。

    Method for cleaning semiconductor structures using hydrocarbon and solvents in a repetitive vapor phase/liquid phase sequence
    33.
    发明授权
    Method for cleaning semiconductor structures using hydrocarbon and solvents in a repetitive vapor phase/liquid phase sequence 失效
    在重复气相/液相序列中使用烃和溶剂清洗半导体结构的方法

    公开(公告)号：US06692579B2

    公开(公告)日：2004-02-17

    申请号：US09764244

    申请日：2001-01-19

    申请人： Sudipto Ranendra Roy ,  Yi Xu ,  Simon Chooi ,  Yakub Aliyu ,  Mei Sheng Zhou ,  John Leonard Sudijono ,  Paul Kwok Keung Ho ,  Subhash Gupta

    发明人： Sudipto Ranendra Roy ,  Yi Xu ,  Simon Chooi ,  Yakub Aliyu ,  Mei Sheng Zhou ,  John Leonard Sudijono ,  Paul Kwok Keung Ho ,  Subhash Gupta

    IPC分类号： B08B300

    CPC分类号： H01L21/02057 ,  B08B3/00 ,  C11D7/24 ,  C11D7/5027 ,  C11D11/0047 ,  H01L21/02063 ,  H01L21/6704

    摘要： A method for cleaning a semiconductor structure using vapor phase condensation with a thermally vaporized cleaning agent, a hydrocarbon vaporized by pressure variation, or a combination of the two. In the thermally vaporized cleaning agent process, a semiconductor structure is lowered into a vapor blanket in a thermal gradient cleaning chamber at atmospheric pressure formed by heating a liquid cleaning agent below the vapor blanket and cooling the liquid cleaning agent above the vapor blanket causing it to condense and return to the bottom of the thermal gradient cleaning chamber. The semiconductor structure is then raised above the vapor blanket and the cleaning agent condenses on all of the surfaces of the semiconductor structure removing contaminants and is returned to the bottom of the chamber by gravity. In the pressurized hydrocarbon process, a semiconductor structure is placed into a variable pressure cleaning chamber, having a piston which changes the pressure by reducing or increasing the volume of the chamber. The semiconductor structure first exposed to the hydrocarbon in vapor phase, then the piston is lowered to condense the hydrocarbon. A semiconductor structure can be cleaned by either or both of these processes by repetitive vaporization/condensation cycles.

    摘要翻译： 一种使用与气相清洗剂进行气相冷凝的半导体结构，通过压力变化蒸发的烃或两者的组合来清洗半导体结构的方法。 在热蒸发清洗剂方法中，半导体结构在大气压力的热梯度清洗室内被降低成蒸气层，所述热梯度清洗室通过将蒸气层下方的液体清洗剂加热而形成，并将该液体清洁剂冷却至蒸气层以上 冷凝并返回到热梯度清洗室的底部。 然后将半导体结构升高到蒸气层上方，并且清洁剂在半导体结构的所有表面上冷凝除去杂质，并通过重力返回到室的底部。 在加压烃工艺中，将半导体结构放置在可变压力清洁室中，其具有通过减小或增加室的体积来改变压力的活塞。 半导体结构首先暴露于气相中的烃，然后降低活塞以使烃冷凝。 半导体结构可以通过这些过程中的任一个或两者通过重复的蒸发/冷凝循环进行清洁。

    Method of fabricating variable length vertical transistors
    34.
    发明授权
    Method of fabricating variable length vertical transistors 失效
    制造可变长度垂直晶体管的方法

    公开(公告)号：US06632712B1

    公开(公告)日：2003-10-14

    申请号：US10263895

    申请日：2002-10-03

    申请人： Chew-Hoe Ang ,  Eng Hua Lim ,  Randall Cha ,  Jia Zhen Zheng ,  Elgin Quek ,  Mei Sheng Zhou ,  Daniel Yen

    发明人： Chew-Hoe Ang ,  Eng Hua Lim ,  Randall Cha ,  Jia Zhen Zheng ,  Elgin Quek ,  Mei Sheng Zhou ,  Daniel Yen

    IPC分类号： H01L218238

    CPC分类号： H01L29/66666 ,  H01L21/823885 ,  H01L29/7827

    摘要： A process for fabricating vertical CMOS devices, featuring variable channel lengths, has been developed. Channel region openings are defined in composite insulator stacks, with the channel length of specific devices determined by the thickness of the composite insulator stack. Selective removal of specific components of the composite insulator stack, in a specific region, allows the depth of the channel openings to be varied. A subsequent epitaxial silicon growth procedure fills the variable depth channel openings, providing the variable length, channel regions for the vertical CMOS devices.

    摘要翻译： 已经开发了用于制造具有可变通道长度的垂直CMOS器件的工艺。 通道区域开口限定在复合绝缘体堆叠中，特定器件的通道长度由复合绝缘子堆叠的厚度确定。 在特定区域中选择性去除复合绝缘子堆叠的特定部件允许沟道开口的深度变化。 随后的外延硅生长过程填充可变深度通道开口，为垂直CMOS器件提供可变长度的沟道区。

    Method to form an asymmetrical non-volatile memory device using small in-situ doped polysilicon spacers
    35.
    发明授权
    Method to form an asymmetrical non-volatile memory device using small in-situ doped polysilicon spacers 失效
    使用小的原位掺杂多晶硅间隔物形成非对称非易失性存储器件的方法

    公开(公告)号：US06544848B1

    公开(公告)日：2003-04-08

    申请号：US10224212

    申请日：2002-08-20

    申请人： Chew Hoe Ang ,  Eng Hua Lim ,  Randall Cha ,  Jia Zhen Zheng ,  Elgin Quek ,  Mei Sheng Zhou ,  Daniel Yen

    发明人： Chew Hoe Ang ,  Eng Hua Lim ,  Randall Cha ,  Jia Zhen Zheng ,  Elgin Quek ,  Mei Sheng Zhou ,  Daniel Yen

    IPC分类号： H01L218247

    CPC分类号： H01L29/66825 ,  H01L21/28273

    摘要： A new method of forming a sharp tip on a floating gate in the fabrication of a EEPROM memory cell is described. A first gate dielectric layer is provided on a substrate. A second gate dielectric layer is deposited overlying the first gate dielectric layer. A floating gate/control gate stack is formed overlying the second gate dielectric layer. One sidewall portion of the floating gate is covered with a mask. The second gate dielectric layer not covered by the mask is etched away whereby an undercut of the floating gate is formed in the second gate dielectric layer. The mask is removed. Polysilicon spacers are formed on sidewalls of the floating gate wherein one of the polysilicon spacers fills the undercut thereby forming a sharp polysilicon tip to improve the erase efficiency of the memory cell.

    摘要翻译： 描述了在EEPROM存储器单元的制造中在浮动栅极上形成尖端尖端的新方法。 第一栅介质层设置在基板上。 第二栅介质层沉积在第一栅介质层上。 形成覆盖在第二栅极电介质层上的浮栅/控制栅叠层。 浮动栅极的一个侧壁部分被掩模覆盖。 被掩模未被覆盖的第二栅极电介质层被蚀刻掉，从而在第二栅极介质层中形成浮栅的底切。 去除面具。 多晶硅间隔物形成在浮置栅极的侧壁上，其中多晶硅间隔物中的一个填充底切，从而形成尖锐的多晶硅尖端，以提高存储单元的擦除效率。

    Endpoint detection and novel chemicals in copper stripping
    37.
    发明授权
    Endpoint detection and novel chemicals in copper stripping 失效
    铜剥离中的端点检测和新型化学品

    公开(公告)号：US06419754B1

    公开(公告)日：2002-07-16

    申请号：US09376426

    申请日：1999-08-18

    申请人： Simon Chooi ,  Mei Sheng Zhou

    发明人： Simon Chooi ,  Mei Sheng Zhou

    IPC分类号： C23G116

    CPC分类号： G01N21/31 ,  C23F1/00 ,  G01N21/85 ,  H01L21/32134 ,  H01L22/26 ,  Y10T436/12

    摘要： An endpoint detection system for copper stripping using a colorimetric analysis of the change in concentration of a component is described. Wet copper stripping chemicals are used to strip copper from a wafer whereby an eluent is produced. The eluent is continuously analyzed by colorimetric analysis for the presence of copper. The copper stripping process is stopped when the presence of copper is no longer detected. Also novel compounds or chemicals for use in an endpoint detection system for copper stripping using a colorimetric analysis of the change in concentration of the novel compounds or chemicals are described. A composition of matter that serves as an indicator of the presence of copper by colorimetric analysis comprises: 1) Fast Sulphon Black F indicator and an ammonium ion-containing solution or 2) a complexing agent, comprising a diamine, an amine macrocycle, or a monoamine.

    摘要翻译： 描述了使用对组分浓度变化的比色分析进行铜剥离的端点检测系统。 湿铜剥离化学品用于从晶片剥离铜，从而产生洗脱液。 通过比色分析连续分析洗脱液是否存在铜。 当不再检测到铜的存在时，铜剥离过程停止。 还描述了用于铜剥离终点检测系统的新型化合物或化学品，其使用对新化合物或化学品的浓度变化的比色分析。 通过比色分析作为铜存在指标的物质组成包括：1）快速磺化黑F指示剂和含铵离子的溶液或2）络合剂，其包含二胺，胺大环化合物或 单胺

    Thermal stability improvement of CoSi2 film by stuffing in titanium
    38.
    发明授权
    Thermal stability improvement of CoSi2 film by stuffing in titanium 失效
    CoSi2薄膜通过填充钛的热稳定性提高

    公开(公告)号：US06383922B1

    公开(公告)日：2002-05-07

    申请号：US09872558

    申请日：2001-06-04

    申请人： Bei Chao Zhang ,  Chung Woh Lai ,  Eng Hua Lim ,  Mei Sheng Zhou ,  Peter Chew ,  Arthur Ang

    发明人： Bei Chao Zhang ,  Chung Woh Lai ,  Eng Hua Lim ,  Mei Sheng Zhou ,  Peter Chew ,  Arthur Ang

    IPC分类号： H01L21336

    CPC分类号： H01L29/665 ,  H01L21/28052 ,  H01L21/28518 ,  H01L29/4933

    摘要： A method for forming a thermally stable cobalt disilicide film in the fabrication of an integrated circuit is described. A semiconductor substrate is provided having silicon regions to be silicided. A cobalt layer is deposited overlying the silicon regions to be silicided. A capping layer is deposited overlying the cobalt layer. The substrate is subjected to a first rapid thermal anneal whereby the cobalt is transformed to cobalt monosilicide where it overlies the silicon regions and wherein the cobalt not overlying the silicon regions is unreacted. The unreacted cobalt layer and the capping layer are removed. A titanium layer is deposited overlying the cobalt monosilicide layer. Thereafter the substrate is subjected to a second rapid thermal anneal whereby the cobalt monosilicide is transformed to cobalt disilicide. The titanium layer provides titanium atoms which diffuse into the cobalt disilicide thereby increasing its thermal stability. The titanium layer is removed to complete formation of a thermally stable cobalt disilicide film in the manufacture of an integrated circuit.

    摘要翻译： 描述了在制造集成电路中形成热稳定性二硅化二硅膜的方法。 提供具有要被硅化的硅区域的半导体衬底。 覆盖待硅化硅的区域上沉积钴层。 覆盖在钴层上的覆盖层。 对衬底进行第一快速热退火，由此将钴转化为单硅硅酸盐，其中它覆盖在硅区域上，并且其中不覆盖硅区域的钴是未反应的。 去除未反应的钴层和覆盖层。 沉积在一氧化硅钴层上的钛层。 此后，将衬底进行第二次快速热退火，由此使一价硅酸钴转化为二硅化钴。 钛层提供扩散到二硅化钴中的钛原子，从而增加其热稳定性。 去除钛层以在制造集成电路中完成热稳定的二硅化硅膜的形成。

    CMP process utilizing dummy plugs in damascene process
    39.
    发明授权
    CMP process utilizing dummy plugs in damascene process 有权
    在镶嵌工艺中使用假插头的CMP工艺

    公开(公告)号：US06380087B1

    公开(公告)日：2002-04-30

    申请号：US09596901

    申请日：2000-06-19

    申请人： Subhash Gupta ,  Mei Sheng Zhou ,  Ramasamy Chockalingam

    发明人： Subhash Gupta ,  Mei Sheng Zhou ,  Ramasamy Chockalingam

    IPC分类号： H01L21302

    CPC分类号： H01L24/02 ,  H01L21/7684 ,  H01L21/76877 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01082 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/14 ,  Y10S438/926

    摘要： A method of fabricating a semiconductor wafer having at least one integrated circuit, the method comprising the following steps. A semiconductor wafer structure having at least an upper and a lower dielectric layer is provided. The semiconductor wafer structure having a bonding pad area and an interconnect area. At least one active interconnect having a first width is formed in the interconnect area, through the dielectric layers. A plurality of adjacent dummy plugs each having a second width is formed in the bonding pad area, through a portion of the dielectric layers. The semiconductor wafer structure is patterned and etched to form trenches through the upper dielectric layer. The trenches surround each of the at least one active interconnect and the dummy plugs whereby the upper dielectric level between the adjacent dummy plugs is removed. A metallization layer is deposited over the lower dielectric layer, filling the trenches at least to the upper surface of the remaining upper dielectric layer. The metallization layer is planarized to remove the excess of the metallization layer forming a continuous bonding pad within the bonding pad area and including the plurality of adjacent dummy plugs, thus forming at least one damascene structure including the at least one respective active interconnect.

    摘要翻译： 一种制造具有至少一个集成电路的半导体晶片的方法，所述方法包括以下步骤。 提供了至少具有上介电层和下电介质层的半导体晶片结构。 该半导体晶片结构具有焊盘区域和互连区域。 具有第一宽度的至少一个有源互连通过电介质层形成在互连区域中。 通过电介质层的一部分，在焊盘区域中形成多个具有第二宽度的相邻虚拟插头。 对半导体晶片结构进行图案化和蚀刻，以形成通过上部电介质层的沟槽。 沟槽围绕至少一个有源互连和虚拟插头中的每一个，由此相邻虚拟插头之间的上部电介质层被去除。 金属化层沉积在下电介质层上，至少填充到剩余的上电介质层的上表面上的沟槽。 金属化层被平坦化以去除在焊盘区域内形成连续接合焊盘的多余的金属化层，并且包括多个相邻的虚设插头，从而形成包括至少一个相应的有源互连的至少一个镶嵌结构。