公开(公告)号：US20240138139A1

公开(公告)日：2024-04-25

申请号：US18223166

申请日：2023-07-17

申请人： NANYA TECHNOLOGY CORPORATION

发明人： SHIH-FAN KUAN ,  WEI-CHEN PAN ,  YU-TING LIN ,  HUEI-RU LIN

IPC分类号： H10B12/00 ,  G11C5/06

CPC分类号： H10B12/00 ,  G11C5/063

摘要： A semiconductor device and a method of manufacturing the same are provided. The semiconductor device includes a substrate, a plurality of capacitors, and a first supporting layer. The plurality of capacitors are disposed on the substrate. Each of the capacitors extends along a first direction. Each of the plurality of capacitors includes a first capacitor electrode, a second capacitor electrode, and a capacitor dielectric separating the first capacitor electrode from the second capacitor electrode. The first supporting layer is disposed on the substrate. The first supporting layer extends along a second direction different from the first direction. The capacitor dielectric includes a first surface and a second surface which are disposed on two opposite sides along the first direction. The second surface is exposed by the first capacitor electrode. The first supporting layer is disposed between the first surface and the second surface of the capacitor dielectric.

公开(公告)号：US20240138138A1

公开(公告)日：2024-04-25

申请号：US17973202

申请日：2022-10-24

申请人： NANYA TECHNOLOGY CORPORATION

发明人： SHIH-FAN KUAN ,  WEI-CHEN PAN ,  YU-TING LIN ,  HUEI-RU LIN

IPC分类号： H01L27/108 ,  G11C5/06

CPC分类号： H01L27/108 ,  G11C5/063

摘要： A semiconductor device and a method of manufacturing the same are provided. The semiconductor device includes a substrate, a plurality of capacitors, and a first supporting layer. The plurality of capacitors are disposed on the substrate. Each of the capacitors extends along a first direction. Each of the plurality of capacitors includes a first capacitor electrode, a second capacitor electrode, and a capacitor dielectric separating the first capacitor electrode from the second capacitor electrode. The first supporting layer is disposed on the substrate. The first supporting layer extends along a second direction different from the first direction. The capacitor dielectric includes a first surface and a second surface which are disposed on two opposite sides along the first direction. The second surface is exposed by the first capacitor electrode. The first supporting layer is disposed between the first surface and the second surface of the capacitor dielectric.

公开(公告)号：US20240130127A1

公开(公告)日：2024-04-18

申请号：US18450969

申请日：2023-08-16

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Beyong Hyun KOH ,  Ho Jin KIM ,  Geun Won LIM ,  Jung Ho LEE ,  Hyun Gun JANG

IPC分类号： H10B43/27 ,  G11C5/06 ,  G11C16/04 ,  H01L23/528 ,  H01L29/08 ,  H10B43/10 ,  H10B43/35

CPC分类号： H10B43/27 ,  G11C5/063 ,  G11C16/0483 ,  H01L23/5283 ,  H01L29/0847 ,  H10B43/10 ,  H10B43/35

摘要： A semiconductor memory device comprises a substrate; a mold structure on the substrate; a plurality of channel structures extending in the mold structure; a source layer and a source sacrificial layer between the substrate and the mold structure, wherein the source sacrificial layer is spaced apart from the source layer; and a source support layer on the source layer and the source sacrificial layer, wherein the source support layer is between the source layer and the source sacrificial layer, wherein an upper surface of the source support layer includes first and second portions extending parallel to the substrate, and a third portion that connects the first and second portions, wherein a vertical distance from an upper surface of the source layer to the first portion is smaller than a vertical distance from an upper surface of the substrate to the second portion.

公开(公告)号：US20240105242A1

公开(公告)日：2024-03-28

申请号：US18214466

申请日：2023-06-26

申请人： Rambus Inc.

发明人： Ian Shaeffer ,  Kyung Suk Oh

IPC分类号： G11C7/22 ,  G11C5/06 ,  G11C11/4063 ,  G11C29/02

CPC分类号： G11C7/22 ,  G11C5/063 ,  G11C11/4063 ,  G11C29/02 ,  G11C29/022 ,  G11C29/025 ,  G11C29/028 ,  G11C5/04

摘要： A memory device includes a set of inputs, and a first register that includes a first register field to store a value for enabling application of one of a plurality of command/address (CA) on-die termination (ODT) impedance values to first inputs that receive the CA signals; and a second register field to store a value for enabling application of one of a plurality of chip select (CS) ODT impedance values to a second input that receives the CS signal. A third register field may store a value for enabling application of a clock (CK) ODT impedance value to third inputs that receive the CK signal.

公开(公告)号：US20240096387A1

公开(公告)日：2024-03-21

申请号：US18460413

申请日：2023-09-01

申请人： Rambus Inc.

发明人： Ian Shaeffer ,  Lawrence Lai ,  Fan Ho ,  David A. Secker ,  Wayne S. Richardson ,  Akash Bansal ,  Brian S. Leibowitz ,  Kyung Suk Oh

IPC分类号： G11C8/12 ,  G11C5/02 ,  G11C5/04 ,  G11C5/06 ,  G11C7/10 ,  G11C8/18 ,  H01L23/00 ,  H01L25/065

CPC分类号： G11C8/12 ,  G11C5/02 ,  G11C5/04 ,  G11C5/06 ,  G11C5/063 ,  G11C7/1012 ,  G11C7/1045 ,  G11C8/18 ,  H01L24/49 ,  H01L25/0657 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45099 ,  H01L2224/48095 ,  H01L2224/48227 ,  H01L2224/48471 ,  H01L2224/49171 ,  H01L2224/49433 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/181

摘要： A memory device comprising a programmable command-and-address (CA) interface and/or a programmable data interface is described. In an operational mode, two or more CA interfaces may be active. In another operational mode, at least one, but not all, CA interfaces may be active. In an operational mode, all of the data interfaces may be active. In another operational mode, at least one, but not all, data interfaces may be active. The memory device can include circuitry to select: an operational mode; a sub-mode within an operational mode; one or more CA interfaces as the active CA interface(s); a main CA interface from multiple active CA interfaces; and/or one or more data interfaces as the active data interfaces. The circuitry may perform these selection(s) based on one or more bits in one or more registers and/or one or more signals received on one or more pins.

公开(公告)号：US20240087616A1

公开(公告)日：2024-03-14

申请号：US18463686

申请日：2023-09-08

申请人： Kioxia Corporation

发明人： Takafumi MASUDA ,  Nobuyoshi SAITO ,  Mutsumi OKAJIMA ,  Keiji IKEDA

IPC分类号： G11C5/06 ,  G11C5/10

CPC分类号： G11C5/063 ,  G11C5/10

摘要： A semiconductor memory device comprises: memory layers arranged in a first direction; and a first and a second via wirings having different positions in a second direction. The memory layer comprises: a first transistor electrically connected to the first via wiring; a memory portion electrically connected to the first transistor; a wiring electrically connected to the first transistor; a second transistor electrically connected to the second via wiring; and an electrode provided in a current path between the second transistor and the wiring. The second transistor comprises: a semiconductor layer electrically connected to the electrode and the second via wiring; and a gate electrode facing the semiconductor layer. The semiconductor layer faces at least one of surfaces on one side or the other side in the first direction of the gate electrode. The electrode includes a portion arranged with the second via wiring in a third direction.

公开(公告)号：US20240081037A1

公开(公告)日：2024-03-07

申请号：US17930096

申请日：2022-09-07

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Brent A. Anderson ,  Albert M. Chu ,  Junli Wang ,  Carl Radens ,  Ruilong Xie

IPC分类号： H01L27/11 ,  G11C5/06

CPC分类号： H01L27/1112 ,  G11C5/063

摘要： A field effect transistor (FET) cell structure of an integrated circuit (IC) is provided. The FET cell structure includes first and second adjacent cells. Each of the first and second adjacent cells spans a first layer and a second layer. The second layer is vertically stacked on the first layer. The first cell includes n-doped FETs (NFETs) on one of the first and second layers and p-doped FETs (PFETs) on another of the first and second layers. The second cell includes at least one of a number of NFETs on the one of the first and second layers differing from a number of the NFETs in the first cell and a number of PFETs on the another of the first and second layers differing from a number of the PFETs in the first cell.

公开(公告)号：US20240079060A1

公开(公告)日：2024-03-07

申请号：US18337115

申请日：2023-06-19

申请人： Kioxia Corporation

发明人： Mitsunori MASAKI

IPC分类号： G11C16/04 ,  G11C5/06 ,  H01L23/528 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

CPC分类号： G11C16/0483 ,  G11C5/063 ,  H01L23/5283 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

摘要： A semiconductor memory device includes: wiring layers; a semiconductor column opposed to the wiring layers; a gate insulating film disposed between the wiring layers and the semiconductor column; and an insulating member in contact with the gate insulating film. A first wiring layer includes: a first wiring disposed on a gate insulating film side with respect to the insulating member; a second wiring disposed on a side opposite the first wiring; and a metal oxide film covering surfaces on one side and the other side in the stacking direction and not covering a contact surface with the insulating member of the second wiring. The second wiring includes a first conductive layer and a second conductive layer spaced apart in the stacking direction, and a first conductive portion connected to the first conductive layer and the second conductive layer. The first conductive portion includes the contact surface with the insulating member.

公开(公告)号：US20240074211A1

公开(公告)日：2024-02-29

申请号：US18238291

申请日：2023-08-25

申请人： Micron Technology, Inc.

发明人： Kamal M. Karda ,  Chandra Mouli ,  Haitao Liu ,  Durai Vishak Nirmal Ramaswamy

IPC分类号： H10B63/00 ,  G11C5/06 ,  H10B63/10 ,  H10N70/00

CPC分类号： H10B63/34 ,  G11C5/063 ,  H10B63/10 ,  H10B63/845 ,  H10N70/883

摘要： Some embodiments include apparatuses and methods of operating the apparatuses. One of the apparatuses includes a conductive region; a memory cell including a memory element, a first portion, a second portion, a dielectric portion, and a third portion; and a data line formed over the second and third portions of the memory cell. The memory element is formed over the conductive region. The first portion is formed over the memory element and includes a first conductive material. The second portion is formed over the first portion and includes a second conductive material. The dielectric portion includes a first side adjacent the memory element, the first portion, and the second portion. The third portion includes a third conductive material and is adjacent a second side of the dielectric portion and separated from the memory element, the first portion, and the second portion by the dielectric portion.

公开(公告)号：US11915764B2

公开(公告)日：2024-02-27

申请号：US17704154

申请日：2022-03-25

申请人： MICRON TECHNOLOGY, INC.

发明人： Jeremy Binfet ,  Kishore Kumar Muchherla

IPC分类号： G11C5/06 ,  G11C16/04 ,  G11C16/10 ,  G11C16/26 ,  G11C16/32

CPC分类号： G11C16/10 ,  G11C16/0483 ,  G11C16/26 ,  G11C16/32 ,  G11C5/063

摘要： Memories might include an array of memory cells and a controller for access of the array of memory cells. The controller might be configured to cause the memory to initiate an array operation on the array of memory cells, indicate an unavailability to initiate a next array operation, append a delay interval to an array access time of the array operation, and indicate an availability to initiate a next array operation in response to a completion of the delay interval. The delay interval might have a duration determined in response to an indication of temperature.