公开(公告)号：US09698151B2

公开(公告)日：2017-07-04

申请号：US15179068

申请日：2016-06-10

Applicant: Seung-Min Lee ,  Hoo-Sung Cho ,  Jeong-Seok Nam ,  Jong-Min Lee ,  Yong-Joon Choi

Inventor： Seung-Min Lee ,  Hoo-Sung Cho ,  Jeong-Seok Nam ,  Jong-Min Lee ,  Yong-Joon Choi

IPC: H01L27/115 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11582 ,  H01L23/528 ,  H01L23/522 ,  H01L21/768

CPC classification number: H01L27/11565 ,  H01L21/76816 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/544 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11582 ,  H01L2223/5442 ,  H01L2223/54433 ,  H01L2223/54453

Abstract: A vertical memory device includes a substrate, a plurality of channels on the substrate and extending in a first direction that is vertical to a top surface of the substrate, a plurality of gate lines stacked on top of each other on the substrate, a plurality of wiring over the gate lines and electrically connected to the gate lines, and an identification pattern on the substrate at the same level as a level of at least one of the wirings. The gate lines surround the channels. The gate lines are spaced apart from each other along the first direction.

公开(公告)号：US20170186695A1

公开(公告)日：2017-06-29

申请号：US15379533

申请日：2016-12-15

Applicant: Infineon Technologies Austria AG

Inventor： Andreas Moser ,  Hans Weber ,  Michael Treu ,  Johannes Baumgartl ,  Gabor Mezoesi

IPC: H01L23/544 ,  H01L21/308 ,  H01L29/06 ,  H01L21/266

CPC classification number: H01L23/544 ,  G03F9/7076 ,  H01L21/266 ,  H01L21/308 ,  H01L29/0634 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/5446

Abstract: An alignment mark in a process surface of a semiconductor layer includes a groove with a minimum width of at least 100 μm and a vertical extension in a range 100 nm to 1 μm. The alignment mark further includes at least one fin within the groove at a distance of at least 60 μm to a closest one of inner corners of the groove.

公开(公告)号：US20170186646A1

公开(公告)日：2017-06-29

申请号：US15388062

申请日：2016-12-22

Applicant: DISCO CORPORATION

Inventor： Hironari Ohkubo ,  Taku Iwamoto

IPC: H01L21/78 ,  H01L21/66 ,  H01L23/544 ,  H01L21/304

CPC classification number: H01L21/78 ,  B28D5/0058 ,  B28D5/022 ,  H01L21/3043 ,  H01L21/6836 ,  H01L22/12 ,  H01L23/544 ,  H01L2221/68327 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/54453

Abstract: A wafer processing method including the steps of storing information on the intervals and positions of metal patterns formed on part of division lines on a wafer into a storage unit of a cutting apparatus, detecting the division lines, forming a cut groove along each division line by using a cutting blade, imaging an area including the cut groove at any position where the metal patterns are not formed, by using an imaging unit included in the cutting apparatus, according to the information on the intervals and positions of the metal patterns previously stored, during the step of forming the cut grooves, and measuring the positional relation between the position of the cut groove and a preset cutting position. Accordingly, kerf check can be performed without being influenced by burrs produced from the metal patterns in cutting the wafer, so that the wafer can be cut with high accuracy.

公开(公告)号：US09671215B2

公开(公告)日：2017-06-06

申请号：US14576072

申请日：2014-12-18

Applicant: International Business Machines Corporation

Inventor： Mukta G. Farooq ,  John A. Fitzsimmons ,  Spyridon Skordas

IPC: G01B7/31 ,  H01L21/66 ,  H01L23/544

CPC classification number: G01B7/31 ,  H01L22/34 ,  H01L23/544 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/5446

Abstract: Wafer to wafer alignment which includes a first semiconductor wafer and a second semiconductor wafer. The first and second semiconductor wafers have selectively-activated alignment arrays for aligning the first semiconductor wafer with the second semiconductor wafer. Each of the alignment arrays include an alignment structure which includes an antenna connected to a semiconductor device. The antenna in each of the alignment arrays is selectively activated to act as a charge source or as a charge sensing receptor. The alignment arrays are located in the kerf areas of the semiconductor wafers. The semiconductor wafers are aligned when the charge sources on one semiconductor wafer match with the charge sensing receptors on the other semiconductor wafer.

公开(公告)号：US09666537B2

公开(公告)日：2017-05-30

申请号：US14698187

申请日：2015-04-28

Applicant: Texas Instruments Incorporated

Inventor： Simon Y S Chang ,  Arnold C. Conway

IPC: H01L21/78 ,  H01L23/544

CPC classification number: H01L23/544 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/5446 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods and apparatus for front-to-back alignment using narrow scribe lines are disclosed. An apparatus is disclosed that includes a semiconductor wafer comprising a plurality of areas for the fabrication of integrated circuit devices on a device side, the integrated circuit devices arranged in rows and columns and spaced from one another by a plurality of scribe lines disposed on the semiconductor wafer in areas between the integrated circuit devices and free from integrated circuit devices; and one or more alignment marks disposed on the semiconductor wafer, the alignment marks positioned in an intersection of two of the scribe lines; wherein the scribe lines have a first minimum dimension and the one or more alignment marks have a second minimum dimension that is greater than the first minimum dimension. Methods and additional apparatus are disclosed.

公开(公告)号：US09666522B2

公开(公告)日：2017-05-30

申请号：US14465474

申请日：2014-08-21

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Li-Hsien Huang ,  Hsien-Wei Chen ,  Ching-Wen Hsiao ,  Der-Chyang Yeh ,  Shin-Puu Jeng ,  Chen-Hua Yu

IPC: H01L21/56 ,  H01L21/768 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L23/522 ,  H01L23/544 ,  H01L21/48 ,  H01L23/538 ,  H01L21/683 ,  H01L25/10 ,  H01L25/00 ,  H01L25/065

CPC classification number: H01L23/544 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/56 ,  H01L21/561 ,  H01L21/565 ,  H01L21/6835 ,  H01L21/76802 ,  H01L21/76877 ,  H01L21/78 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/5226 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L24/92 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2221/68318 ,  H01L2221/68372 ,  H01L2221/68381 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/54433 ,  H01L2223/54486 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/83005 ,  H01L2224/83132 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06568 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2225/1082 ,  H01L2924/00014 ,  H01L2924/1431 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A package includes a device die, a molding material molding the device die therein, a through-via penetrating through the molding material, and an alignment mark penetrating through the molding material. A redistribution line is on a side of the molding material. The redistribution line is electrically coupled to the through-via.

公开(公告)号：US20170141343A1

公开(公告)日：2017-05-18

申请号：US15421608

申请日：2017-02-01

Applicant: Samsung Display Co., Ltd.

Inventor： Sangshin LEE

IPC: H01L51/52 ,  H01L27/32 ,  H01L23/544

CPC classification number: H01L51/524 ,  H01L23/544 ,  H01L27/3244 ,  H01L51/0011 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/54486

Abstract: A display apparatus including a substrate having an active area and a sealing area surrounding the active area; a display unit disposed on the active area of the substrate; a sealing member including a recess, which is formed in the sealing area of the substrate and is concave in a direction from an edge of the substrate to the active area of the substrate or from the active area of the substrate to the edge of the substrate; and an alignment mark disposed between the recess and the edge of the substrate or between the recess and the active area of the substrate.

公开(公告)号：US20170125300A1

公开(公告)日：2017-05-04

申请号：US15184315

申请日：2016-06-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JONG-SU KIM

IPC: H01L21/8234 ,  H01L23/544 ,  H01L21/311 ,  H01L21/3105 ,  H01L21/02 ,  H01L21/308

CPC classification number: H01L21/823431 ,  H01L21/02532 ,  H01L21/3081 ,  H01L21/3086 ,  H01L21/31051 ,  H01L21/31111 ,  H01L21/32139 ,  H01L21/823437 ,  H01L23/544 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/54453

Abstract: A method of fabricating a semiconductor device is provided as follows. A target layer is formed. A hard mask layer is formed on the target layer. The hard mask layer is patterned to form an overlay mask pattern including a first mask pattern and a plateau-shaped mask pattern. The first mask pattern encloses the plateau-shaped mask pattern. The first mask pattern is spaced apart from the plateau-shaped mask pattern. The target layer is patterned using the overlay mask pattern to form a redundant fin and a plateau-shaped overlay mark. The redundant fin is removed.

公开(公告)号：US09640727B2

公开(公告)日：2017-05-02

申请号：US14976611

申请日：2015-12-21

Applicant: NICHIA CORPORATION

Inventor： Hiroshi Kobayashi

IPC: H01L33/38 ,  H01L33/50 ,  H01L33/36 ,  H01L23/544 ,  H01L33/62 ,  H01L33/60 ,  H01L25/16 ,  H01L33/48 ,  H01L33/54

CPC classification number: H01L33/38 ,  H01L23/544 ,  H01L25/167 ,  H01L33/36 ,  H01L33/486 ,  H01L33/507 ,  H01L33/54 ,  H01L33/60 ,  H01L33/62 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/54486 ,  H01L2933/0041

Abstract: A light emitting device includes a light emitting element having electrodes, a support, at least one pair of conductive wires that are formed on a surface of the support with a space from each other, and on which the electrodes of the light emitting element are disposed, distance between the pair of conductive wires under an outer edge of the light emitting element being shorter than the distance between the pair of conductive wires at other portions under the light emitting element, and a phosphor layer that continuously covers the outer edge of the light emitting element and a surface of the conductive wires around a region where the light emitting element is disposed.

公开(公告)号：US09633925B1

公开(公告)日：2017-04-25

申请号：US15081403

申请日：2016-03-25

Applicant: GLOBALFOUNDRIES INC.

Inventor： Katsuyuki Sakuma ,  Mukta G. Farooq ,  Jae-Woong Nah

IPC: H01L23/544 ,  H01L23/31 ,  H01L21/56 ,  H01L21/768 ,  H01L23/29

CPC classification number: H01L21/76864 ,  H01L21/563 ,  H01L23/544 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/54473

Abstract: Structures and methods for improving the visualization of alignment marks on an underfill-covered chip. A feature is formed on a chip, and an underfill material is applied to the chip at a wafer level so that the feature is covered the feature. The feature includes a first structural element comprised of a first material and a second structural element comprised of a second material that is electrochemically dissimilar from the first material to provide a galvanic cell effect. Filler particles in the underfill material are caused by the galvanic cell effect to distribute with a first density in a first region over the first structural element and a second region of a second density over the second structural element. The first density in the first region is less than the second density in the second region such that the first region has a lower opacity than the second region.