公开(公告)号：US20150109057A1

公开(公告)日：2015-04-23

申请号：US14515342

申请日：2014-10-15

Applicant: STMicroelectronics SA

Inventor： Emmanuel Rouat

IPC: H03G3/30 ,  H03F3/45

CPC classification number: H03G3/30 ,  H03F3/45071 ,  H03F2203/45178 ,  H03F2203/45202 ,  H03F2203/45336 ,  H03F2203/45528 ,  H03G1/0088 ,  H03G3/001

Abstract: A resistive ladder has first, second and third resistors coupled in series between first and second voltage terminals. A first node of the first resistor is coupled to the first voltage terminal and a first node of the third resistor is coupled to the second voltage terminal. A voltage selection unit has a first input coupled to a first node of the second resistor and a second input coupled to a second node of the second resistor and is adapted to selectively couple one of the first and second inputs to an output node of said resistive ladder. The resistive ladder also includes a first switch coupled between a second node of the third resistor and the second voltage terminal.

Abstract translation: 电阻梯具有在第一和第二电压端子之间串联耦合的第一，第二和第三电阻器。 第一电阻器的第一节点耦合到第一电压端子，并且第三电阻器的第一节点耦合到第二电压端子。 电压选择单元具有耦合到第二电阻器的第一节点的第一输入和耦合到第二电阻器的第二节点的第二输入，并且适于选择性地将第一和第二输入中的一个耦合到所述电阻的输出节点 阶梯。 电阻梯还包括耦合在第三电阻器的第二节点和第二电压端子之间的第一开关。

公开(公告)号：US09000964B2

公开(公告)日：2015-04-07

申请号：US14294300

申请日：2014-06-03

Applicant: STMicroelectronics SA ,  STMicroelectronics International N.V.

Inventor： Stéphane Le Tual ,  Pratap Narayan Singh

IPC: H03M1/00 ,  H03M1/08 ,  H03K3/013 ,  G11C27/02 ,  H03K19/0185

CPC classification number: H03M1/08 ,  G11C27/024 ,  G11C27/026 ,  H03K3/013 ,  H03K19/018528

Abstract: The invention concerns a circuit comprising: a first transistor (202) having a first main current node coupled to a first voltage signal (CNVDD), a control node coupled to a second voltage signal (CPVDD) and a second main current node coupled to an output node (206) of the circuit; a second transistor (204) having a first main current node coupled to a third voltage signal (CNGND), a control node coupled to a fourth voltage signal (CPGND) and a second main current node coupled to said output node of the circuit; and circuitry (210, 212) adapted to generate said first, second, third and fourth voltage signals based on a pair of differential input signals (CP, CN), wherein said first and second voltage signals are both referenced to a first supply voltage (VDD) and wherein said third and fourth voltage signals are both referenced to a second supply voltage (GND).

Abstract translation: 本发明涉及一种电路，包括：具有耦合到第一电压信号（CNVDD）的第一主电流节点的第一晶体管（202），耦合到第二电压信号（CPVDD）的控制节点和耦合到第一电流信号 输出节点（206）; 第二晶体管（204），其具有耦合到第三电压信号（CNGND）的第一主电流节点，耦合到第四电压信号（CPGND）的控制节点和耦合到所述电路的所述输出节点的第二主电流节点; 以及适于基于一对差分输入信号（CP，CN）产生所述第一，第二，第三和第四电压信号的电路（210,212），其中所述第一和第二电压信号都参考第一电源电压 VDD），并且其中所述第三和第四电压信号都参考第二电源电压（GND）。

公开(公告)号：US20150091089A1

公开(公告)日：2015-04-02

申请号：US14499545

申请日：2014-09-29

Applicant: STMICROELECTRONICS (CROLLES 2) SAS ,  STMICROELECTRONICS SA ,  Commissariat A L'Energie Atomique et aux Energies Alternatives

Inventor： Heimanu Niebojewski ,  Yves Morand ,  Cyrille Le Royer ,  Olivier Rozeau

IPC: H01L29/51 ,  H01L29/66 ,  H01L29/08 ,  H01L29/78

CPC classification number: H01L29/515 ,  H01L29/0843 ,  H01L29/4983 ,  H01L29/4991 ,  H01L29/51 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66575 ,  H01L29/66628 ,  H01L29/78

Abstract: A MOS transistor has a gate insulator layer that is made of a material of high dielectric constant deposited on a substrate. The gate insulator layer extends, with a constant thickness, under and beyond a gate stack. Spacers of low dielectric constant are formed on either side of the gate stack and vertically separated from the substrate by the extension of the gate insulator layer beyond the sides of the gate stack. The spacers of low dielectric constant are preferably air spacers.

Abstract translation: MOS晶体管具有由沉积在衬底上的高介电常数材料制成的栅极绝缘体层。 栅极绝缘体层以恒定的厚度延伸到栅极堆叠之下和之外。 通过栅极绝缘体层的延伸超过栅极叠层的侧面，在栅极叠层的任一侧上形成具有低介电常数的隔板并与衬底垂直分离。 低介电常数的间隔物优选为空气间隔物。

公开(公告)号：US08980702B2

公开(公告)日：2015-03-17

申请号：US14177614

申请日：2014-02-11

Applicant: Commissariat a l'Energie Atomique et aux ene Alt ,  STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics SA

Inventor： Heimanu Niebojewski ,  Yves Morand ,  Maud Vinet

IPC: H01L21/00 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/6656 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/66636 ,  H01L29/66772 ,  H01L29/78603

Abstract: A method for manufacturing a transistor includes forming a stack of semiconductor on insulator type layers including at least one substrate, surmounted by a first insulating layer and an active layer to form a channel for the transistor; forming a gate stack on the active layer; producing a source and a drain including forming, on either side of the gate stack, cavities by at least one step of etching the active layer, the first insulating layer, and part of the substrate selectively to the gate stack to remove the active layer, the first insulating layer, and a portion of the substrate outside regions situated below the gate stack; forming a second insulating layer on the bared surfaces of the substrate, to form a continuous insulating layer with the first insulating layer; baring of the lateral ends of the channel; and the filling of the cavities by epitaxy.

Abstract translation: 一种制造晶体管的方法，包括：形成绝缘体上半导体层的叠层，其包括至少一个衬底，其被第一绝缘层和有源层所覆盖以形成晶体管的沟道; 在有源层上形成栅叠层; 产生源极和漏极，包括在栅叠层的任一侧通过至少一个步骤，至少一个步骤，将有源层，第一绝缘层和衬底的一部分选择性地栅极堆叠以形成去除有源层， 所述第一绝缘层和位于所述栅叠层下方的所述衬底外部区域的一部分; 在所述基板的裸露表面上形成第二绝缘层，以形成具有所述第一绝缘层的连续绝缘层; 通道的横向端部露出; 并通过外延填充空腔。

公开(公告)号：US20150061023A1

公开(公告)日：2015-03-05

申请号：US14450597

申请日：2014-08-04

Applicant: Commissariat à l'énergie atomique et aux énergies alternatives ,  STMicroelectronics SA ,  Centre National de la Recherche Scientifique

Inventor： Yohann Solaro ,  Sorin Cristoloveanu ,  Claire Fenouillet-Beranger ,  Pascal Fonteneau

IPC: H01L27/02 ,  H01L29/66 ,  H01L27/12 ,  H01L29/747 ,  H01L29/78

CPC classification number: H01L27/0262 ,  H01L27/1203 ,  H01L29/1012 ,  H01L29/42308 ,  H01L29/66477 ,  H01L29/7436 ,  H01L29/747 ,  H01L29/749 ,  H01L29/78 ,  H01L29/7833

Abstract: The invention relates to an IC with an electrostatic discharge protection device. There is a buried insulant layer 50 nm or less in thickness and first and second bipolar transistors on the insulant layer, one being an npn transistor and the other a pnp transistor. The base of the first transistor is merged with the collector of the second transistor and the base of the second transistor is merged with the collector of the first transistor. The first and second bipolar transistors are configured to selectively conduct a discharge current between two electrodes of the protection device. There is a first semiconductor ground plane under the insulant layer, being electrically biased, extending until it is plumb with the base of the first bipolar transistor, exhibiting a first type of doping identical to that of the base of the first bipolar transistor with a doping density at least ten times greater.

Abstract translation: 本发明涉及具有静电放电保护装置的IC。 在绝缘层上存在厚度为50nm以下的绝缘绝缘层和第一和第二双极晶体管，一个为npn晶体管，另一个为pnp晶体管。 第一晶体管的基极与第二晶体管的集电极合并，第二晶体管的基极与第一晶体管的集电极合并。 第一和第二双极晶体管被配置为选择性地在保护装置的两个电极之间传导放电电流。 在绝缘层下方存在第一半导体接地层，被电偏压，延伸直到其与第一双极晶体管的基极相连，表现出与第一双极晶体管的基极相同的第一类掺杂，掺杂 密度至少十倍以上。

公开(公告)号：US20150028488A1

公开(公告)日：2015-01-29

申请号：US14339630

申请日：2014-07-24

Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENE ALT ,  STMICROELECTRONICS SA

Inventor： Jean-Philippe COLONNA ,  Perceval COUDRAIN

IPC: H01L23/00 ,  H01L21/306 ,  H01L21/768

CPC classification number: H01L24/19 ,  H01L21/30604 ,  H01L21/4853 ,  H01L21/6836 ,  H01L21/7685 ,  H01L21/76898 ,  H01L23/3171 ,  H01L23/481 ,  H01L24/11 ,  H01L24/13 ,  H01L24/20 ,  H01L2224/11462 ,  H01L2224/11472 ,  H01L2224/13009 ,  H01L2224/13076 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/13084 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13166 ,  H01L2224/13171 ,  H01L2224/13181 ,  H01L2224/13186 ,  H01L2224/1356 ,  H01L2224/13565 ,  H01L2224/13582 ,  H01L2224/13583 ,  H01L2224/13644 ,  H01L2224/13647 ,  H01L2224/13666 ,  H01L2224/13671 ,  H01L2224/13681 ,  H01L2224/13686 ,  H01L2224/14181 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01073 ,  H01L2924/01079 ,  H01L2924/15788 ,  H01L2924/00014 ,  H01L2924/01074 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/00012 ,  H01L2924/00

Abstract: The invention relates to a method for producing an interconnection pad on a conducting element comprising an upper face and a side wall; the method being executed from a substrate at least the upper face of which is insulating; the conducting element going through at least an insulating portion of the substrate, the method being characterized in that it comprises the sequence of the following steps: a step of embossing the conducting element, a step of forming, above the upper insulating face of the substrate, a stack of layers comprising at least one electrically conducting layer and one electrically resistive layer, a step of partially removing the electrically resistive layer, a step of electrolytic growth on the portion of the electrically conducting layer so as to form at least one interconnection pad on said conducting element.

Abstract translation: 本发明涉及一种用于在导电元件上制造互连焊盘的方法，包括上表面和侧壁; 所述方法从至少其上表面绝缘的衬底执行; 所述导电元件至少穿过所述基板的绝缘部分，所述方法的特征在于，其包括以下步骤的顺序：对所述导电元件进行压花的步骤，在所述基板的上绝缘面上方形成步骤 ，包括至少一个导电层和一个电阻层的层叠层，部分去除所述电阻层的步骤，在所述导电层的所述部分上的电解生长步骤，以便形成至少一个互连衬垫 在所述导电元件上。

公开(公告)号：US08913457B2

公开(公告)日：2014-12-16

申请号：US14271165

申请日：2014-05-06

Applicant: STMicroelectronics International N.V. ,  STMicroelectronics, SA

Inventor： Nishu Kohli ,  Robin M. Wilson

IPC: G11C8/00 ,  G11C8/18

CPC classification number: G11C8/18 ,  G11C7/1072 ,  G11C7/22 ,  G11C7/222

Abstract: Memory circuitry includes memory components operable in response to first edges of an internal clock. The memory circuitry also includes internal clock generating circuitry to generate the internal clock in response to a system clock. The first edges of the internal clock are generated in response to both a rising and a falling edge of the system clock.

Abstract translation: 存储器电路包括响应于内部时钟的第一边缘可操作的存储器组件。 存储电路还包括响应系统时钟产生内部时钟的内部时钟产生电路。 响应于系统时钟的上升沿和下降沿都产生内部时钟的第一个边沿。

公开(公告)号：US20140354276A1

公开(公告)日：2014-12-04

申请号：US14286431

申请日：2014-05-23

Applicant: STMicroelectronics SA

Inventor： Severin Trochut ,  Eric Remond

IPC: G01R33/07 ,  H01L43/06 ,  H01L43/04

CPC classification number: G01R33/072 ,  H01L43/04 ,  H01L43/065

Abstract: The generation of a Hall voltage within a semiconductor film of an integrated Hall effect sensor uses the flow of a current within the semiconductor film when subjected to a magnetic field. The film is disposed on top of an insulating layer, referred to as buried layer, which is itself disposed on top of a carrier substrate containing a buried electrode that is situated under the insulating layer. A biasing voltage is applied to the buried electrode.

Abstract translation: 集成的霍尔效应传感器的半导体膜内的霍尔电压的产生在受到磁场时使用半导体膜内的电流的流动。 膜被设置在绝缘层的顶部，被称为掩埋层，其本身设置在包含位于绝缘层下方的掩埋电极的载体衬底的顶部上。 偏置电压施加到埋入电极。

公开(公告)号：US20140341498A1

公开(公告)日：2014-11-20

申请号：US14271641

申请日：2014-05-07

Applicant: STMICROELECTRONICS SA

Inventor： Jean-Robert MANOUVRIER

IPC: G02F1/225 ,  G02F1/015 ,  G02F1/025 ,  H01L31/18

CPC classification number: G02F1/025 ,  G02B2006/12142 ,  G02F1/0123 ,  G02F1/2257 ,  G02F2001/212

Abstract: A semiconductor electro-optical phase shifter may include a first optical action zone having a minimum doping level, a first lateral zone and a central zone flanking the first optical action zone along a first axis, doped respectively at first and second conductivity types so as to form a P-I-N junction between the first lateral zone and the central zone. The phase shifter may include a second optical action zone having a threshold doping level, and a second lateral zone flanking the second optical action zone with the central zone along the first axis doped at the first conductivity type so as to form a P-I-N junction between the second lateral zone and the central zone.

Abstract translation: 半导体电光移相器可以包括分别以第一和第二导电类型掺杂的具有最小掺杂水平的第一光学作用区域，第一横向区域和沿着第一轴线的第一光学作用区域的侧面的中心区域，以便 在第一侧向区域和中心区域之间形成PIN结。 移相器可以包括具有阈值掺杂水平的第二光学作用区域和位于第二光学作用区域的第二侧向区域，其中中心区域沿着以第一导电类型掺杂的第一轴线形成PIN结， 第二横向区域和中心区域。

公开(公告)号：US20140197448A1

公开(公告)日：2014-07-17

申请号：US14155891

申请日：2014-01-15

Applicant: STMicroelectronics SA

Inventor： Philippe Galy ,  Johan Bourgeat

IPC: H01L27/02 ,  H01L21/8249

CPC classification number: H01L21/8249 ,  H01L27/0262 ,  H01L29/0692 ,  H01L29/747 ,  H01L29/87

Abstract: An integrated circuit is produced on a bulk semiconductor substrate in a given CMOS technology and includes a semiconductor device for protection against electrostatic discharges. The semiconductor device has a doublet of floating-gate thyristors coupled in parallel and head-to-tail. Each thyristor has a pair of electrode regions. The two thyristors respectively have two separate gates and a common semiconductor gate region. The product of the current gains of the two transistors of each thyristor is greater than 1. Each electrode region of at least one of the thyristors has a dimension, measured perpendicularly to the spacing direction of the two electrodes of the corresponding pair, which is adjusted so as to impart to the thyristor an intrinsic triggering voltage less than the breakdown voltage of a transistor to be protected, and produced in the CMOS technology.

Abstract translation: 在给定的CMOS技术中在体半导体衬底上制造集成电路，并且包括用于防止静电放电的半导体器件。 半导体器件具有并联和头对尾耦合的双栅极晶闸管。 每个晶闸管都有一对电极区域。 两个晶闸管分别具有两个单独的栅极和公共半导体栅极区域。 每个晶闸管的两个晶体管的电流增益的乘积大于1.至少一个晶闸管的每个电极区域具有垂直于相应对的两个电极的间隔方向测量的尺寸，该尺寸被调整 以便使可控硅的本征触发电压小于要保护的晶体管的击穿电压，并且在CMOS技术中产生。