公开(公告)号：US20160042812A1

公开(公告)日：2016-02-11

申请号：US14918148

申请日：2015-10-20

Applicant: RAMBUS INC.

Inventor： Adrian E. Ong ,  Fan Ho

IPC: G11C29/00 ,  G11C29/12 ,  G11C11/401

CPC classification number: G11C29/76 ,  G11C11/401 ,  G11C11/4085 ,  G11C29/027 ,  G11C29/04 ,  G11C29/12 ,  G11C29/4401 ,  G11C29/48 ,  G11C29/78 ,  G11C29/789 ,  G11C29/802 ,  G11C2229/743

Abstract: A controller includes an internal memory to store an address and a memory control unit operatively coupled with the internal memory. The memory control unit includes logic to identify a malfunctioning address of primary data storage elements within an external memory device, the external memory device being another semiconductor device separate from the controller, store the malfunctioning address in the internal memory, and transmit, to the external memory device, a command to initiate a repair of the malfunctioning address using redundant data storage elements and an indication of an address associated with the malfunctioning address.

Abstract translation: 控制器包括用于存储地址的内部存储器和与内部存储器可操作地耦合的存储器控​​制单元。 存储器控制单元包括用于识别外部存储器件内的主要数据存储元件的故障地址的逻辑，外部存储器件是与控制器分离的另一个半导体器件，将故障地址存储在内部存储器中，并传输到外部存储器 存储器装置，使用冗余数据存储元件发起故障地址的修复的命令以及与故障地址相关联的地址的指示。

公开(公告)号：US09257151B2

公开(公告)日：2016-02-09

申请号：US14306304

申请日：2014-06-17

Applicant: Rambus Inc.

Inventor： Richard E. Perego ,  Donald C. Stark ,  Frederick A. Ware ,  Ely K. Tsern ,  Craig E. Hampel

IPC: G06F12/00 ,  G11C5/04 ,  G06F12/06 ,  G06F12/04 ,  G06F13/16 ,  G11C5/02 ,  G11C5/06 ,  G11C7/10 ,  G11C11/408 ,  G11C11/4097 ,  H05K1/14 ,  G11C8/06 ,  H05K1/11

CPC classification number: G06F13/1678 ,  G06F12/04 ,  G06F12/06 ,  G06F12/0646 ,  G06F13/1657 ,  G06F13/4022 ,  G11C5/02 ,  G11C5/025 ,  G11C5/04 ,  G11C5/06 ,  G11C5/063 ,  G11C7/1006 ,  G11C7/1045 ,  G11C7/1048 ,  G11C7/106 ,  G11C7/1072 ,  G11C7/1087 ,  G11C8/06 ,  G11C11/4087 ,  G11C11/4097 ,  G11C2207/105 ,  G11C2207/108 ,  H05K1/117 ,  H05K1/14 ,  H05K2201/09954 ,  H05K2201/10189 ,  Y02D10/14

Abstract: Described is a printed-circuit board (PCB) that supports memory systems in which the memory core organization changes with device width. The PCB includes a memory-controller mounting location and module connectors to receive respective memory modules. Each module connector connects directly to the controller mounting location via a respective set of system data lines that does not connect to any other module connector. System data lines also extend directly between module connectors to support memory configurations with different numbers of modules. The memory systems support one memory module of a wide data width or multiple memory modules of narrower data widths. The number of physical memory banks accessed reduces with device data width, resulting in reduced power usage for relatively narrow memory configurations. Increasing the number of logic memory banks for narrow memory widths reduces the likelihood of bank conflicts, and consequently improves speed performance.

Abstract translation: 描述了支持存储器系统的印刷电路板（PCB），其中存储器核心组织随设备宽度而变化。 PCB包括存储器控制器安装位置和模块连接器以接收相应的存储器模块。 每个模块连接器通过不连接到任何其他模块连接器的相应的一组系统数据线直接连接到控制器安装位置。 系统数据线也直接在模块连接器之间扩展，以支持具有不同数量模块的存储器配置。 存储器系统支持宽数据宽度的一个存储器模块或较窄数据宽度的多个存储器模块。 访问的物理存储器组的数量随设备数据宽度而减少，导致相对较窄的存储器配置的功率消耗减少。 增加用于窄内存宽度的逻辑内存库的数量可以减少存储体冲突的可能性，从而提高速度性能。

公开(公告)号：US09256376B2

公开(公告)日：2016-02-09

申请号：US14452373

申请日：2014-08-05

Applicant: Rambus Inc.

Inventor： Ely Tsern ,  Thomas Vogelsang ,  Craig Hampel ,  Scott C. Best

IPC: G11C7/00 ,  G06F3/06 ,  G11C11/4074 ,  G06F1/26 ,  G11C5/14

CPC classification number: G06F3/0625 ,  G06F1/266 ,  G06F3/0634 ,  G06F3/0673 ,  G11C5/147 ,  G11C11/4074 ,  G11C2207/2227

Abstract: A memory system supports high-performance and low-power modes. The memory system includes a memory core and a core interface. The memory core employs core supply voltages that remain the same in both modes. Supply voltages and signaling rates for the core interface may be scaled down to save power. Level shifters between the memory core and core interface level shift signals as needed to accommodate the signaling voltages used by the core interface in the different modes.

Abstract translation: 内存系统支持高性能和低功耗模式。 存储器系统包括存储器核和核心接口。 存储器内核采用在两种模式下保持相同的核心电源电压。 核心接口的电源电压和信号速率可以缩小以节省功耗。 存储器核心和核心接口电平之间的电平移位器根据需要移位信号以适应不同模式下核心接口所使用的信令电压。

公开(公告)号：US20160036605A1

公开(公告)日：2016-02-04

申请号：US14789832

申请日：2015-07-01

Applicant: Rambus Inc.

Inventor： Jared L. Zerbe ,  Vladimir M. Stojanovic ,  Fred F. Chen

IPC: H04L25/03

CPC classification number: H04L25/03019 ,  H04B1/1081 ,  H04L7/0058 ,  H04L7/0087 ,  H04L7/0331 ,  H04L25/03025 ,  H04L25/03038 ,  H04L25/03057 ,  H04L25/03343 ,  H04L25/03885

Abstract: A signaling circuit having a selectable-tap equalizer. The signaling circuit includes a buffer, a select circuit and an equalizing circuit. The buffer is used to store a plurality of data values that correspond to data signals transmitted on a signaling path during a first time interval. The select circuit is coupled to the buffer to select a subset of data values from the plurality of data values according to a select value. The equalizing circuit is coupled to receive the subset of data values from the select circuit and is adapted to adjust, according to the subset of data values, a signal level that corresponds to a data signal transmitted on the signaling path during a second time interval.

公开(公告)号：US20160026583A1

公开(公告)日：2016-01-28

申请号：US14871754

申请日：2015-09-30

Applicant: Rambus Inc.

Inventor： Ian Shaeffer ,  Frederick A. Ware

IPC: G06F12/14 ,  G06F13/16 ,  G06F12/02

CPC classification number: G06F12/1458 ,  G06F12/023 ,  G06F13/16 ,  G06F13/1657 ,  G06F13/1684 ,  G06F13/1694 ,  G06F2212/1044 ,  G06F2212/1052

Abstract: A multi-rank memory system in which calibration operations are performed between a memory controller and one rank of memory while data is transferred between the controller and other ranks of memory. A memory controller performs a calibration operation that calibrates parameters pertaining to transmission of data via a first data bus between the memory controller and a memory device in a first rank of memory. While the controller performs the calibration operation, the controller also transfers data with a memory device in a second rank of memory via a second data bus.

Abstract translation: 一种多级存储器系统，其中在存储器控制器和一级存储器之间执行校准操作，同时数据在控制器和其他等级的存储器之间传送。 存储器控制器执行校准操作，其校准与存储器控制器和存储器的第一等级中的存储器件之间经由第一数据总线的数据传输有关的参数。 当控制器执行校准操作时，控制器还经由第二数据总线将存储器件中的数据与第二等级的存储器传送数据。

公开(公告)号：US09241118B2

公开(公告)日：2016-01-19

申请号：US14094077

申请日：2013-12-02

Applicant: Rambus Inc.

Inventor： Michael Guidash

IPC: H01L27/00 ,  H04N5/353 ,  H04N5/355 ,  H04N5/3745

CPC classification number: H04N5/3535 ,  H04N5/355 ,  H04N5/3745

Abstract: An image sensor architecture is implemented within an image sensor system. Image sensor pixels include pixel regions, and each pixel region includes a photosensor, a reset circuit, and a readout circuit. The readout circuit receives enable signals from an enable signal line, and outputs a pixel signal representative of light captured by the photosensor on a combination input/output line. The reset circuit resets the photosensor in response to receiving a first reset signal on a reset line and a second reset signal on the combination input/output line.

Abstract translation: 在图像传感器系统内实现图像传感器架构。 图像传感器像素包括像素区域，并且每个像素区域包括光电传感器，复位电路和读出电路。 读出电路从使能信号线接收使能信号，并将表示由光电传感器捕获的光的像素信号输出到组合输入/输出线上。 复位电路响应于在复位线路上接收到第一复位信号和组合输入/输出线路上的第二复位信号来复位光电传感器。

公开(公告)号：US20160013955A1

公开(公告)日：2016-01-14

申请号：US14789794

申请日：2015-07-01

Applicant: Rambus Inc.

Inventor： Yikui Jen Dong

IPC: H04L25/03 ,  H04L25/06

CPC classification number: H04L25/03019 ,  H03K5/007 ,  H04L25/0292 ,  H04L25/0296 ,  H04L25/06 ,  H04L47/50

Abstract: An on-chip AC coupled receiver with baseline wander compensation. The receiver may be used for either single ended or differential signals. The receiver includes an input terminal to receive an input signal. AC coupling circuitry is between the input terminal and a node and couples the input signal into a coupled signal at the node. A control loop senses low frequency signal content at the node and uses a linear buffer in adjusting the coupled signal at the node based on the low frequency signal content. The operation of the control loop compensates for potential baseline wander in the coupled signal. An input stage to recovers data from the coupled signal at the node.

Abstract translation: 具有基线漂移补偿的片上AC耦合接收器。 接收机可以用于单端或差分信号。 接收机包括用于接收输入信号的输入端。 AC耦合电路位于输入端和节点之间，并将输入信号耦合到节点处的耦合信号。 控制回路感测节点处的低频信号内容，并且基于低频信号内容使用线性缓冲器来调整节点处的耦合信号。 控制环路的操作补偿了耦合信号中潜在的基线漂移。 用于从节点处的耦合信号恢复数据的输入级。

公开(公告)号：US09236409B2

公开(公告)日：2016-01-12

申请号：US13961842

申请日：2013-08-07

Applicant: Rambus Inc.

Inventor： Marko Aleksić

IPC: H01L27/146 ,  H04N5/335 ,  H04N5/3745

CPC classification number: H01L27/14609 ,  H04N5/3355 ,  H04N5/37455

Abstract: An integrated-circuit image sensor that includes an array of pixel regions composed of binary pixel circuits. Each binary pixel circuit includes a binary amplifier having an input and an output. The binary amplifier generates a binary signal at the output in response to whether an input voltage at the input exceeds a switching threshold voltage level of the binary amplifier. A light-detecting element of the binary pixel circuit is coupled to the input of the binary amplifier. Initialization circuitry of the binary pixel circuit is coupled to the input of the binary amplifier. The initialization circuitry sets the input voltage to a level that is offset relative to the switching threshold voltage level of the binary amplifier by an offset voltage amount, the offset voltage amount representing a threshold amount of light incident on the light detecting element.

Abstract translation: 一种集成电路图像传感器，包括由二进制像素电路组成的像素区域阵列。 每个二进制像素电路包括具有输入和输出的二进制放大器。 二进制放大器响应于输入端的输入电压是否超过二进制放大器的开关阈值电压电平，在输出端产生二进制信号。 二进制像素电路的光检测元件耦合到二进制放大器的输入端。 二进制像素电路的初始化电路耦合到二进制放大器的输入端。 初始化电路将输入电压设置为相对于二进制放大器的开关阈值电压电平偏移偏移电压量的电平，偏移电压量表示入射在光检测元件上的阈值光量。

公开(公告)号：US20160005489A1

公开(公告)日：2016-01-07

申请号：US14857794

申请日：2015-09-17

Applicant: Rambus Inc.

Inventor： Kyung Suk Oh ,  Ian P. Shaeffer

IPC: G11C16/32 ,  G11C16/26

CPC classification number: H03K19/0005 ,  G06F3/0605 ,  G06F3/0659 ,  G06F3/0685 ,  G06F13/4086 ,  G11C11/401 ,  G11C11/4063 ,  G11C11/4093 ,  G11C11/41 ,  G11C11/413 ,  G11C11/417 ,  G11C11/419 ,  G11C16/06 ,  G11C16/26 ,  G11C16/32 ,  H03K19/017545

Abstract: An IC die transmits command signals, address signals and data signals to a flash memory device at respective times via a time-multiplexed external signaling line, the data signals representing data to be stored within an array of non-volatile storage elements of the flash memory device. The IC die additionally transmits a control signal to the flash memory device via one or more external control signal lines, the control signal directing the flash memory device to switchably couple an on-die termination element to the time-multiplexed signaling line.

Abstract translation: IC芯片经由时间复用的外部信号线在各自的时间将命令信号，地址信号和数据信号发送到闪速存储器件，数据信号表示要存储在闪速存储器的非易失性存储元件阵列内的数据 设备。 IC芯片还经由一个或多个外部控制信号线将控制信号发送到闪速存储器件，该控制信号指示闪速存储器件可切换地将片上端接元件耦合到时分多路信号线。

公开(公告)号：US20160003994A1

公开(公告)日：2016-01-07

申请号：US14770080

申请日：2014-03-03

Applicant: RAMBUS INC.

Inventor： Patrick R. Gill ,  David G. Stork

IPC: G02B5/30 ,  H04N5/232 ,  G02B5/18

CPC classification number: G02B5/3083 ,  G02B5/1842 ,  G02B5/1871 ,  G02B27/4205 ,  G02B27/46 ,  H01L27/14625 ,  H01L27/14685 ,  H04N5/23232 ,  H04N5/335

Abstract: Image-sensing devices include odd-symmetry gratings that cast interference patterns over a photodetector array. Grating features offer considerable insensitivity to the wavelength of incident light, and also to the manufactured distance between the grating and the photodetector array. Photographs and other image information can be extracted from interference patterns captured by the photodetector array. Images can be captured without a lens, and cameras can be made smaller than those that are reliant on lenses and ray-optical focusing.

Abstract translation: 图像感测装置包括在光电检测器阵列上投射干涉图案的奇对称光栅。 光栅特征对入射光的波长以及光栅与光电检测器阵列之间的制造距离有相当大的不敏感性。 可以从由光电检测器阵列捕获的干涉图案中提取照片和其它图像信息。 图像可以在没有镜头的情况下被捕获，并且相机可以比依赖于镜头和射线光学聚焦的照相机更小。