公开(公告)号：US5861324A

公开(公告)日：1999-01-19

申请号：US764301

申请日：1996-12-12

Applicant: Hirofumi Ichinose ,  Akio Hasebe ,  Tsutomu Murakami ,  Satoshi Shinkura ,  Yukie Ueno

Inventor： Hirofumi Ichinose ,  Akio Hasebe ,  Tsutomu Murakami ,  Satoshi Shinkura ,  Yukie Ueno

IPC: H01L31/04 ,  H01L31/0224 ,  H01L31/075

CPC classification number: H01L31/076 ,  H01L31/022425 ,  H01L31/022466 ,  H01L31/075 ,  Y02E10/548

Abstract: A photovoltaic element comprising an electrode comprising an electrically conductive core member which is coated with a conductive adhesive fixed on the light incident surface of a photoactive semiconductor layer, via the conductive adhesive, is disclosed.The conductive adhesive is composed of at least two layers. The softening point of the conductive adhesive layer nearer to the core member is higher than the highest temperature encountered in the manufacture of the photovoltaic element.

Abstract translation: 公开了一种光电元件，其包括通过导电粘合剂包括固定在光活性半导体层的光入射表面上的导电粘合剂的导电芯体的电极。 导电粘合剂由至少两层组成。 导电粘合剂层更靠近核心部件的软化点高于制造光电元件时遇到的最高温度。

公开(公告)号：US5859397A

公开(公告)日：1999-01-12

申请号：US857905

申请日：1997-05-16

Applicant: Hirofumi Ichinose ,  Akio Hasebe ,  Tsutomu Murakami ,  Satoshi Shinkura ,  Yukie Ueno

Inventor： Hirofumi Ichinose ,  Akio Hasebe ,  Tsutomu Murakami ,  Satoshi Shinkura ,  Yukie Ueno

IPC: H01L31/0392 ,  H01L31/076 ,  H01L31/20 ,  C07C1/00 ,  C23F13/00 ,  C25F1/00 ,  C30B30/02

CPC classification number: H01L31/076 ,  H01L31/03921 ,  H01L31/208 ,  Y02E10/548 ,  Y02P70/521

Abstract: A process for producing a photovoltaic element, said process comprising the steps of: providing a photovoltaic element comprising a lower electrode layer comprising a metallic layer comprising aluminum or an aluminum compound and a transparent and electrically conductive layer, a photoelectric conversion semiconductor layer, and a transparent electrode layer stacked in the named order on an electrically conductive surface of a substrate, and immersing said photovoltaic element in an electrolyte solution to passivate an short-circuited current path defect present in said photovoltaic element by the action of an electric field, wherein said electrolyte solution has a chlorine ion content of 0.03 mol/l or less.

Abstract translation: 一种制造光伏元件的方法，所述方法包括以下步骤：提供包括下电极层的光电元件，该下电极层包括由铝或铝化合物构成的金属层和透明导电层，光电转换半导体层和 透明电极层按照所述顺序层叠在基板的导电表面上，并将所述光电元件浸入电解液中，以通过电场的作用钝化存在于所述光电元件中的短路电流路径缺陷，其中所述 电解质溶液的氯离子含量为0.03mol / l以下。

公开(公告)号：US5821606A

公开(公告)日：1998-10-13

申请号：US790985

申请日：1997-01-29

Applicant: Gen Murakami ,  Kunihiro Tsubosaki ,  Masahiro Ichitani ,  Kunihiko Nishi ,  Ichiro Anjo ,  Asao Nishimura ,  Makoto Kitano ,  Akihiro Yaguchi ,  Sueo Kawai ,  Masatsugu Ogata ,  Syuuji Eguchi ,  Hiroyoshi Kokaku ,  Masanori Segawa ,  Hiroshi Hozoji ,  Takashi Yokoyama ,  Noriyuki Kinjo ,  Aizo Kaneda ,  Junichi Saeki ,  Shozo Nakamura ,  Akio Hasebe ,  Hiroshi Kikuchi ,  Isamu Yoshida ,  Takashi Yamazaki ,  Kazuyoshi Oshima ,  Tetsurou Matsumoto

Inventor： Gen Murakami ,  Kunihiro Tsubosaki ,  Masahiro Ichitani ,  Kunihiko Nishi ,  Ichiro Anjo ,  Asao Nishimura ,  Makoto Kitano ,  Akihiro Yaguchi ,  Sueo Kawai ,  Masatsugu Ogata ,  Syuuji Eguchi ,  Hiroyoshi Kokaku ,  Masanori Segawa ,  Hiroshi Hozoji ,  Takashi Yokoyama ,  Noriyuki Kinjo ,  Aizo Kaneda ,  Junichi Saeki ,  Shozo Nakamura ,  Akio Hasebe ,  Hiroshi Kikuchi ,  Isamu Yoshida ,  Takashi Yamazaki ,  Kazuyoshi Oshima ,  Tetsurou Matsumoto

IPC: H01L21/44 ,  H01L21/48 ,  H01L21/50 ,  H01L23/31 ,  H01L23/495 ,  H01L25/10 ,  H01L29/06 ,  H05K1/14 ,  H05K1/18 ,  H05K3/34

CPC classification number: H01L24/32 ,  H01L23/3107 ,  H01L23/4951 ,  H01L23/49555 ,  H01L23/49558 ,  H01L23/49568 ,  H01L23/49586 ,  H01L24/05 ,  H01L24/06 ,  H01L25/105 ,  H01L29/0657 ,  H01L2224/02166 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/05556 ,  H01L2224/05599 ,  H01L2224/05624 ,  H01L2224/06136 ,  H01L2224/16 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/32245 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45565 ,  H01L2224/4569 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/48465 ,  H01L2224/48624 ,  H01L2224/48724 ,  H01L2224/48799 ,  H01L2224/73215 ,  H01L2224/85205 ,  H01L2224/8592 ,  H01L2225/1005 ,  H01L2225/1029 ,  H01L2225/107 ,  H01L24/45 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01043 ,  H01L2924/01045 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01058 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01092 ,  H01L2924/0132 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15738 ,  H01L2924/15747 ,  H01L2924/1576 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/3025 ,  H01L2924/3511 ,  H05K1/144 ,  H05K1/181 ,  H05K3/3421 ,  Y10T29/49121

Abstract: As the semiconductor chip is large-sized, highly integrated and speeded up, it becomes difficult to pack the semiconductor chip together with leads in a package. In view of this difficulty, there has been adopted the package structure called the "Lead-On-Chip" or "Chip-On-Lead" structure in which the semiconductor and the leads are stacked and packed. In the package of this structure, according to the present invention, the gap between the leading end portions of the inner leads and the semiconductor chip is made wider than that between the inner lead portions except the leading end portions and the semiconductor chip thereby to reduce the stray capacity, to improve the signal transmission rate and to reduce the electrical noises.

公开(公告)号：US5530286A

公开(公告)日：1996-06-25

申请号：US293555

申请日：1994-08-22

Applicant: Gen Murakami ,  Kunihiro Tsubosaki ,  Masahiro Ichitani ,  Kunihiko Nishi ,  Ichiro Anjoh ,  Asao Nishimura ,  Makoto Kitano ,  Akihiro Yaguchi ,  Sueo Kawai ,  Masatsugu Ogata ,  Syuuji Eguchi ,  Hiroyoshi Kokaku ,  Masanori Segawa ,  Hiroshi Hozoji ,  Takashi Yokoyama ,  Noriyuki Kinjo ,  Aizo Kaneda ,  Junichi Saeki ,  Shozo Nakamura ,  Akio Hasebe ,  Hiroshi Kikuchi ,  Isamu Yoshida ,  Takashi Yamazaki ,  Kazuyoshi Oshima ,  Tetsurou Matsumoto

Inventor： Gen Murakami ,  Kunihiro Tsubosaki ,  Masahiro Ichitani ,  Kunihiko Nishi ,  Ichiro Anjoh ,  Asao Nishimura ,  Makoto Kitano ,  Akihiro Yaguchi ,  Sueo Kawai ,  Masatsugu Ogata ,  Syuuji Eguchi ,  Hiroyoshi Kokaku ,  Masanori Segawa ,  Hiroshi Hozoji ,  Takashi Yokoyama ,  Noriyuki Kinjo ,  Aizo Kaneda ,  Junichi Saeki ,  Shozo Nakamura ,  Akio Hasebe ,  Hiroshi Kikuchi ,  Isamu Yoshida ,  Takashi Yamazaki ,  Kazuyoshi Oshima ,  Tetsurou Matsumoto

IPC: H01L21/44 ,  H01L21/48 ,  H01L21/50 ,  H01L23/31 ,  H01L23/495 ,  H01L25/10 ,  H01L29/06 ,  H05K1/14 ,  H05K1/18 ,  H05K3/34 ,  H01L23/48 ,  H01L23/52

CPC classification number: H01L24/32 ,  H01L23/3107 ,  H01L23/4951 ,  H01L23/49555 ,  H01L23/49558 ,  H01L23/49568 ,  H01L23/49586 ,  H01L24/05 ,  H01L24/06 ,  H01L25/105 ,  H01L29/0657 ,  H01L2224/02166 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/05556 ,  H01L2224/05599 ,  H01L2224/05624 ,  H01L2224/06136 ,  H01L2224/16 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/32245 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45565 ,  H01L2224/4569 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/48465 ,  H01L2224/48624 ,  H01L2224/48724 ,  H01L2224/48799 ,  H01L2224/73215 ,  H01L2224/85205 ,  H01L2224/8592 ,  H01L2225/1005 ,  H01L2225/1029 ,  H01L2225/107 ,  H01L24/45 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01043 ,  H01L2924/01045 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01058 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01092 ,  H01L2924/0132 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15738 ,  H01L2924/15747 ,  H01L2924/1576 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/3025 ,  H01L2924/3511 ,  H05K1/144 ,  H05K1/181 ,  H05K3/3421 ,  Y10T29/49121

Abstract: As the semiconductor chip is large-sized, highly integrated and speeded up, it becomes difficult to pack the semiconductor chip together with leads in a package. In view of this difficulty, there has been adopted the package structure called the "Lead-On-Chip" or "Chip-On-Lead" structure in which the semiconductor and the leads are stacked and packed. In the package of this structure, according to the present invention, the gap between the leading end portions of the inner leads and the semiconductor chip is made wider than that between the inner lead portions except the leading end portions and the semiconductor chip thereby to reduce the stray capacity, to improve the signal transmission rate and to reduce the electrical noises.

公开(公告)号：US08062911B2

公开(公告)日：2011-11-22

申请号：US11958369

申请日：2007-12-17

Applicant: Akio Hasebe ,  Yasuhiro Motoyama ,  Yasunori Narizuka ,  Seigo Nakamura ,  Kenji Kawakami

Inventor： Akio Hasebe ,  Yasuhiro Motoyama ,  Yasunori Narizuka ,  Seigo Nakamura ,  Kenji Kawakami

IPC: H01L21/66 ,  G01R31/26

CPC classification number: G01R3/00 ,  G01R1/07342

Abstract: A probe having a sufficient height is manufactured by selectively depositing, over the main surface of a wafer, a copper film in a region in which a metal film is to be formed and a region which will be outside an adhesion ring when a probe card is fabricated; forming the metal film, polyimide film, interconnect, another polyimide film, another interconnect and a further polyimide film; and then removing the wafer and copper film. According to the present invention, when probe testing is performed using a prober (thin film probe) having the probe formed in the above-described manner while utilizing the manufacturing technology of semiconductor integrated circuit devices, it is possible to prevent breakage of the prober and a wafer to be tested.

Abstract translation: 通过选择性地在晶片的主表面上沉积在要形成金属膜的区域中的铜膜和当探针卡是在粘合环外部时将在粘合环外部的区域，制造具有足够高度的探针 制造的 形成金属膜，聚酰亚胺膜，互连，另一聚酰亚胺膜，另一互连和另外的聚酰亚胺膜; 然后取出晶片和铜膜。 根据本发明，在利用半导体集成电路器件的制造技术的情况下，使用具有以上述方式形成的探针的探测器（薄膜探针）进行探针测试时，可以防止探测器的破损， 待测试的晶圆。

公开(公告)号：US20100301884A1

公开(公告)日：2010-12-02

申请号：US12787869

申请日：2010-05-26

Applicant: Etsuko Takane ,  Yasunori Narizuka ,  Akira Yabushita ,  Kenji Kawakami ,  Akio Hasebe

Inventor： Etsuko Takane ,  Yasunori Narizuka ,  Akira Yabushita ,  Kenji Kawakami ,  Akio Hasebe

IPC: G01R31/02 ,  H01R13/02 ,  H01R43/00

CPC classification number: H05K3/4007 ,  G01R1/06733 ,  G01R1/0735 ,  G01R3/00 ,  H05K3/06 ,  H05K3/205 ,  H05K2201/0367 ,  H05K2201/09845 ,  H05K2203/0574 ,  Y10T29/49224

Abstract: A semiconductor chip inspection apparatus largely reduces occurrence of damage due to foreign matter in an inspection process and improves durability at the same time of miniaturization is provided. As to a highly accurate thin-film probe sheet which performs: a contact to electrode pads arranged at a narrow pitch and a high density along with integration of semiconductor chip; and an inspection of semiconductor chips, by providing two layers of metal films selectively removable in a step-like shape in a periphery region of fine contact terminal having sharp tips and arranged at a high density and a narrow pitch at the same level as electrode pads, an upper periphery of the contact terminals is covered with an insulating film, and a large space region is formed.

Abstract translation: 半导体芯片检查装置大大减少了检查过程中由于异物引起的损坏的发生，并提供了同时小型化的耐久性。 对于高精度的薄膜探针片，其执行：与半导体芯片的集成一起以窄间距和高密度布置的电极焊盘的接触; 以及对半导体芯片的检查，通过在具有尖锐尖端的精细接触端子的周边区域中提供两级可选择性地以阶梯状形式移除的金属膜，并以与电极焊盘相同的高度密度和窄间距排列 接触端子的上周边被绝缘膜覆盖，形成大的空间区域。

公开(公告)号：US07598100B2

公开(公告)日：2009-10-06

申请号：US11719112

申请日：2004-11-18

Applicant: Hideyuki Matsumoto ,  Shingo Yorisaki ,  Akio Hasebe ,  Yasuhiro Motoyama ,  Masayoshi Okamoto ,  Yasunori Narizuka

Inventor： Hideyuki Matsumoto ,  Shingo Yorisaki ,  Akio Hasebe ,  Yasuhiro Motoyama ,  Masayoshi Okamoto ,  Yasunori Narizuka

IPC: H01L21/00 ,  H01L31/26 ,  H01L21/66 ,  H01L21/82

CPC classification number: G01R1/0735 ,  G01R3/00

Abstract: As the thickness of the card holder for preventing warping of a multilayered wiring substrate 1 is increased, there occurs a problem that a thin film sheet 2 is buried in a card holder and secure contact between probes 7 and test pads cannot be realized. For its prevention, the thin film sheet 2 and a bonding ring 6 are bonded in a state where a tensile force is applied only to the central region IA of the thin film sheet 2, and a tensile force is not applied to an outer peripheral region OA. Then, the height of the bonding ring 6 defining the height up to the probe surface of the thin film sheet 2 is increased, thereby increasing the height up to the probe surface of the thin film sheet 2.

Abstract translation: 随着用于防止多层布线基板1翘曲的卡夹的厚度增加，存在薄膜片2被埋在卡夹中并且不能实现探针7和测试垫之间的牢固接触的​​问题。 为了防止，薄膜片2和接合环6在仅向薄膜片2的中心区域IA施加张力的状态下接合，并且拉伸力不施加到外围区域 OA。 然后，限定高达薄膜片2的探针表面的高度的接合环6的高度增加，从而增加高达薄膜片2的探针表面的高度。

公开(公告)号：US07537943B2

公开(公告)日：2009-05-26

申请号：US11866301

申请日：2007-10-02

Applicant: Akio Hasebe ,  Yasuhiro Motoyama ,  Yasunori Narizuka ,  Seigo Nakamura

Inventor： Akio Hasebe ,  Yasuhiro Motoyama ,  Yasunori Narizuka ,  Seigo Nakamura

IPC: H01L21/66 ,  G01R31/26

CPC classification number: H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A technique of manufacturing a semiconductor integrated circuit device is provided for reducing the possibility of attachment of foreign matter to a membrane probe when performing probe inspection using the membrane probe formed by the manufacturing technique. A pressing member for pressing a membrane sheet includes a pressing pin receiving portion relatively disposed above for receiving the tip of a pressing pin of the plunger in a recess, and a membrane sheet pressing portion relatively disposed below. The membrane sheet pressing portion in contact with the membrane sheet has the minimum plane size to enable pressing of the entire surface of one chip of interest to be subjected to the probe inspection.

Abstract translation: 提供一种制造半导体集成电路器件的技术，用于在使用由该制造技术形成的膜探针进行探针检查时，减少将异物附着于膜探针的可能性。 用于挤压薄膜片的按压部件包括相对设置在上侧的压接销接收部，用于接收凹部中的柱塞的按压销的前端，以及相对设置在下方的膜片按压部。 与膜片接触的膜片按压部具有最小的平面尺寸，能够对要进行探头检查的一个感兴趣的芯片的整个表面进行按压。

公开(公告)号：US20090017565A1

公开(公告)日：2009-01-15

申请号：US11816369

申请日：2005-03-11

Applicant: Akio Hasebe ,  Hideyuki Matsumoto ,  Shingo Yorisaki ,  Yasuhiro Motoyama ,  Masayoshi Okamoto ,  Yasunori Narizuka ,  Naoki Okamoto

Inventor： Akio Hasebe ,  Hideyuki Matsumoto ,  Shingo Yorisaki ,  Yasuhiro Motoyama ,  Masayoshi Okamoto ,  Yasunori Narizuka ,  Naoki Okamoto

IPC: H01L21/66

CPC classification number: H01L24/10 ,  G01R31/2889 ,  H01L24/13 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05085 ,  H01L2224/05124 ,  H01L2224/05144 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05572 ,  H01L2224/056 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01045 ,  H01L2924/01046 ,  H01L2924/01057 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/04941 ,  H01L2924/12036 ,  H01L2924/12041 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15788 ,  H01L2924/00 ,  H01L2924/00014

Abstract: A probe is contacted to a test pad, without destroying the circuit formed in the chip at the time of a probe test. Therefore, a load jig, a pressing tool, an elastomer, an adhesion ring, and a plunger are made into one by fixation with a nut and a bolt. The elastic force of the spring installed between the spring retaining jig and the load jig acts so that the member used as these one may be depressed toward pad PD. The thrust transmitted from the spring in a plunger to a thin films sheet is used only for the extension of a thin films sheet.

Abstract translation: 在探针测试时，探针与测试垫接触，而不会破坏芯片中形成的电路。 因此，通过用螺母和螺栓固定，将装载夹具，压制工具，弹性体，粘合环和柱塞制成一体。 安装在弹簧保持夹具和负载夹具之间的弹簧的弹力用于使得用作这些弹簧的构件可以朝向垫PD压下。 从弹簧传递到柱塞到薄膜片的推力仅用于薄膜片的延伸。

公开(公告)号：US20080096295A1

公开(公告)日：2008-04-24

申请号：US11866301

申请日：2007-10-02

Applicant: Akio HASEBE ,  Yasuhiro Motoyama ,  Yasunori Narizuka ,  Seigo Nakamura

Inventor： Akio HASEBE ,  Yasuhiro Motoyama ,  Yasunori Narizuka ,  Seigo Nakamura

IPC: H01L21/66

CPC classification number: H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A technique of manufacturing a semiconductor integrated circuit device is provided for reducing the possibility of attachment of foreign matter to a membrane probe when performing probe inspection using the membrane probe formed by the manufacturing technique. A pressing member for pressing a membrane sheet includes a pressing pin receiving portion relatively disposed above for receiving the tip of a pressing pin of the plunger in a recess, and a membrane sheet pressing portion relatively disposed below. The membrane sheet pressing portion in contact with the membrane sheet has the minimum plane size to enable pressing of the entire surface of one chip of interest to be subjected to the probe inspection.

Abstract translation: 提供一种制造半导体集成电路器件的技术，用于在使用由该制造技术形成的膜探针进行探针检查时，减少将异物附着于膜探针的可能性。 用于挤压薄膜片的按压部件包括相对设置在上侧的压接销接收部，用于接收凹部中的柱塞的按压销的前端，以及相对设置在下方的膜片按压部。 与膜片接触的膜片按压部具有最小的平面尺寸，能够对要进行探头检查的一个感兴趣的芯片的整个表面进行按压。