公开(公告)号：US20060114934A1

公开(公告)日：2006-06-01

申请号：US11193763

申请日：2005-07-28

Applicant: Minsu Shin ,  Deock-Gil Oh ,  Ho-Jin Lee

Inventor： Minsu Shin ,  Deock-Gil Oh ,  Ho-Jin Lee

IPC: H04J3/22 ,  H04J3/16 ,  H04Q7/24 ,  H04B7/185

CPC classification number: H04B7/18584

Abstract: A network operation method in an interactive satellite communications system interworking with an external network without modifying a network setting is provided. The network operation method in a base station of the interactive satellite communications system includes the steps of: receiving a data request packet from a user; converting a private internet protocol (IP) address of the user into a public IP address; transmitting the data request packet to an external server; receiving a response packet to the data request packet from the external server and converting the converted public IP address into the private IP address; and transmitting the received response packet to the user by using information on a mapping table.

Abstract translation: 提供了在不修改网络设置的情况下与外部网络相互配合的交互式卫星通信系统中的网络操作方法。 交互式卫星通信系统的基站中的网络操作方法包括以下步骤：从用户接收数据请求分组; 将用户的私人网际协议（IP）地址转换为公共IP地址; 将数据请求包发送到外部服务器; 从所述外部服务器接收到所述数据请求分组的响应分组，并将所转换的公共IP地址转换成所述专用IP地址; 以及通过使用关于映射表的信息将接收到的响应分组发送给用户。

公开(公告)号：US20050141472A1

公开(公告)日：2005-06-30

申请号：US10892679

申请日：2004-07-15

Applicant: Minsu Shin ,  Joon-Gyn Ryu ,  Hoon Jeong ,  Ho-Jin Lee

Inventor： Minsu Shin ,  Joon-Gyn Ryu ,  Hoon Jeong ,  Ho-Jin Lee

IPC: H04B7/185 ,  H04L1/00 ,  H04L12/56 ,  H04Q7/00

CPC classification number: H04B7/18513 ,  H04L1/0003 ,  H04L1/0009 ,  H04W4/18 ,  H04W84/06

Abstract: Provided are a forward link rain attenuation compensating apparatus using an adaptive transmission scheme in an interactive satellite communication system and a method thereof. The apparatus separates the mobile stations into clear-sky mobile stations and mobile stations in the state of rain attenuation and makes the clear-sky mobile stations receive data having a high data transmission efficiency at a high-speed while making the rain attenuation mobile stations receive the data continuously although the data transmit rate is low by making each of the two kinds of mobile stations receive data frames of a different transmission method, and provides a method therefor. The apparatus includes: a resource manager, a transmitting data format converter, a forward modulator, a backward demodulator, a receiving data format converter.

Abstract translation: 提供一种在交互式卫星通信系统中使用自适应传输方案的前向链路雨衰补偿装置及其方法。 该装置将移动台分为处于雨衰状态的空中移动台和移动台，使得天空清晰的移动台高速接收高数据传输效率的数据，同时使雨衰移移动站接收 通过使两种移动站中的每一个接收到不同传输方式的数据帧，数据传输速率低，并且提供了一种方法。 该装置包括：资源管理器，发送数据格式转换器，前向调制器，反向解调器，接收数据格式转换器。

公开(公告)号：US06885668B1

公开(公告)日：2005-04-26

申请号：US09543822

申请日：2000-04-05

Applicant: Ho-Jin Lee ,  Chae-Moon Lee ,  Duck-Young Seo ,  Jin-Hyung Yang

Inventor： Ho-Jin Lee ,  Chae-Moon Lee ,  Duck-Young Seo ,  Jin-Hyung Yang

IPC: H04L12/28 ,  H04L12/70 ,  H04W36/18 ,  H04W88/08 ,  H04W88/12 ,  H04W88/14 ,  H04L12/56

CPC classification number: H04L12/5601 ,  H04L49/606 ,  H04L2012/5607 ,  H04L2012/5676 ,  H04W36/18 ,  H04W88/08 ,  H04W88/12 ,  H04W88/14

Abstract: Disclosed is an apparatus and a method capable of processing low-speed circuit data lower than 64 kbps and high-speed packet data higher than 64 kbps in which a high-speed data network is constructed by converting an LCIN (local CDMA (code division multiple access) interconnection network) for supplying a communication path of packet data among sub-systems in a BSC (base station controller) of CDMA system to an ATM (asynchronous transfer mode) for processing high-speed data, installing a TSB (transcoder selector bank) or an SDU (selector distribution unit) for processing high-speed packet data higher than 64 kbps in the BSC, and linking an ATM switch to an MSC (mobile switching center) to provide a high-speed data service with respect to other network. The TSB for processing voice data and low-speed data lower than 64 kbps and high-speed data higher than 64 kbps, or the TSB for processing high-speed data higher than 64 kbps is provided to the BSC, thus allowing high-speed data processing up to 2 mbps, high-speed data service, multimedia service like a video service, and high-speed Internet service.

Abstract translation: 公开了一种能够处理低于64kbps的低速电路数据和高于64kbps的高速分组数据的装置和方法，其中高速数据网络通过转换LCIN（本地CDMA（码分多址） 接入）互连网络），用于将CDMA系统的BSC（基站控制器）中的子系统之间的分组数据的通信路径提供给用于处理高速数据的ATM（异步传输模式），安装TSB（代码转换器选择器组 ）或用于在BSC中处理高于64kbps的高速分组数据的SDU（选择器分配单元），以及将ATM交换机链接到MSC（移动交换中心）以提供关于其他网络的高速数据服务 。 用于处理语音数据和低于64kbps的低速数据的TSB和高于64kbps的高速数据，或用于处理高于64kbps的高速数据的TSB提供给BSC，从而允许高速数据 处理高达2 Mbps，高速数据服务，视频服务等多媒体服务，高速上网服务。

公开(公告)号：US20050069055A1

公开(公告)日：2005-03-31

申请号：US10839383

申请日：2004-05-04

Applicant: Yun-Jeong Song ,  PanSoo Kim ,  Ho-Jin Lee

Inventor： Yun-Jeong Song ,  PanSoo Kim ,  Ho-Jin Lee

IPC: H04L27/06 ,  H04L27/00 ,  H04L27/22 ,  H04L27/38

CPC classification number: H04L27/22 ,  H04L27/3809 ,  H04L2027/0016 ,  H04L2027/0024

Abstract: An apparatus and method for compensating an imbalance of phase and gain between I-channel and Q-channel by using variable loop gains is disclosed. The apparatus includes: a phase error generator for generating a phase error signal by using the I-channel signal and the Q-channel signal; an average value calculator for calculating an average value of the phase error signal; a comparator for comparing the average value with a predetermined threshold; a selector for selecting a loop gain value among a set of loop gains based on the comparison result; a phase imbalance generator for generating a phase imbalance by using the selected loop gain value; and a compensator for compensating the Q-channel signal based on the phase imbalance.

Abstract translation: 公开了一种用于通过使用可变环路增益来补偿I信道和Q信道之间的相位和增益不平衡的装置和方法。 该装置包括：相位误差发生器，用于通过使用I信道信号和Q信道信号产生相位误差信号; 用于计算相位误差信号的平均值的平均值计算器; 用于将所述平均值与预定阈值进行比较的比较器; 用于根据比较结果在一组循环增益中选择一个环路增益值的选择器; 相位不平衡发生器，用于通过使用所选择的环路增益值来产生相位不平衡; 以及用于基于相位不平衡来补偿Q通道信号的补偿器。

公开(公告)号：US09941196B2

公开(公告)日：2018-04-10

申请号：US15130904

申请日：2016-04-15

Applicant: Ho-Jin Lee ,  Tae-Je Cho ,  Dong-Hyeon Jang ,  Ho-Geon Song ,  Se-Young Jeong ,  Un-Byoung Kang ,  Min-Seung Yoon

Inventor： Ho-Jin Lee ,  Tae-Je Cho ,  Dong-Hyeon Jang ,  Ho-Geon Song ,  Se-Young Jeong ,  Un-Byoung Kang ,  Min-Seung Yoon

IPC: H01L21/768 ,  H01L23/498 ,  H01L23/48 ,  H01L25/065 ,  H01L23/525

CPC classification number: H01L23/49844 ,  H01L21/76831 ,  H01L21/76844 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/525 ,  H01L25/0657 ,  H01L2224/02372 ,  H01L2224/05009 ,  H01L2224/13025 ,  H01L2224/16 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2225/06513 ,  H01L2225/06544 ,  H01L2924/15311

Abstract: In one embodiment, a semiconductor device includes a semiconductor substrate having a first surface, and a second surface opposite to the first surface. The second surface defines a redistribution trench. The substrate has a via hole extending therethrough. The semiconductor device also includes a through via disposed in the via hole. The through via may include a via hole insulating layer, a barrier layer, sequentially formed on an inner wall of the via hole. The through via may further include a conductive connector adjacent the barrier layer. The semiconductor device additionally includes an insulation layer pattern formed on the second surface of the substrate. The insulation layer pattern defines an opening that exposes a region of a top surface of the through via. The semiconductor devices includes a redistribution layer disposed in the trench and electrically connected to the through via. The insulation layer pattern overlaps a region of the conductive connector.

公开(公告)号：US09852965B2

公开(公告)日：2017-12-26

申请号：US15204632

申请日：2016-07-07

Applicant: Ho-Jin Lee ,  Byung Lyul Park ,  Kwangjin Moon ,  Jisoon Park ,  Jin Ho An

Inventor： Ho-Jin Lee ,  Byung Lyul Park ,  Kwangjin Moon ,  Jisoon Park ,  Jin Ho An

IPC: H01L23/48 ,  H01L21/768

CPC classification number: H01L23/481 ,  H01L21/76898 ,  H01L2224/11 ,  H01L2224/16145 ,  H01L2924/181 ,  H01L2924/00012

Abstract: Provided herein are semiconductor devices with through electrodes and methods of fabricating the same. The methods may include providing a semiconductor substrate having top and bottom surfaces facing each other, forming on the top surface of the semiconductor substrate a main via having a hollow cylindrical structure and a metal line connected to the main via, forming an interlayered insulating layer on the top surface of the semiconductor substrate to cover the main via and the metal line, removing a portion of the semiconductor substrate to form a via hole exposing a portion of a bottom surface of the main via, and forming in the via hole a through electrode that is electrically connected to the main via. The bottom surface of the main via is overlapped by a circumference of the via hole, when viewed in a plan view.

公开(公告)号：US09219035B2

公开(公告)日：2015-12-22

申请号：US14153478

申请日：2014-01-13

Applicant: Ho-jin Lee ,  Kang-wook Lee ,  Myeong-soon Park ,  Ju-il Choi ,  Son-kwan Hwang

Inventor： Ho-jin Lee ,  Kang-wook Lee ,  Myeong-soon Park ,  Ju-il Choi ,  Son-kwan Hwang

IPC: H01L23/48 ,  H01L23/528 ,  H01L21/768 ,  H01L25/065 ,  H01L25/00 ,  H01L23/522

CPC classification number: H01L23/528 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/5226 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/06181 ,  H01L2224/13009 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/48145 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/15311 ,  H01L2924/00012

Abstract: Methods of forming an integrated circuit device include forming an interlayer dielectric layer on a first surface of a semiconductor substrate and then forming an interconnect hole that extends through the interlayer dielectric layer and into the semiconductor substrate. A first sidewall spacer layer is formed on a sidewall of the interconnect hole. The semiconductor substrate at a bottom of the interconnect hole is isotropically etched to define an undercut recess in the semiconductor substrate. This etching step is performed using the first sidewall spacer layer as an etching mask. The interconnect hole and the uncut recess are then filled with a through-via electrode. A second surface of the semiconductor substrate is removed for a sufficient duration to expose the uncut recess containing the through-via electrode.

Abstract translation: 形成集成电路器件的方法包括在半导体衬底的第一表面上形成层间电介质层，然后形成延伸穿过层间电介质层并进入半导体衬底的互连孔。 第一侧壁间隔层形成在互连孔的侧壁上。 在互连孔的底部的半导体衬底被各向同性蚀刻以在半导体衬底中限定底切凹部。 该蚀刻步骤使用第一侧壁间隔层作为蚀刻掩模进行。 然后用通孔电极填充互连孔和未切割凹部。 去除半导体衬底的第二表面足够的持续时间以露出包含通孔电极的未切割凹部。

公开(公告)号：US20150279825A1

公开(公告)日：2015-10-01

申请号：US14669291

申请日：2015-03-26

Applicant: Pil-Kyu KANG ,  Byung Lyul PARK ,  Taeyeong KIM ,  Yeun-Sang PARK ,  Dosun LEE ,  Ho-Jin LEE ,  Jinho CHUN ,  Ju-il CHOI ,  Yi Koan HONG

Inventor： Pil-Kyu KANG ,  Byung Lyul PARK ,  Taeyeong KIM ,  Yeun-Sang PARK ,  Dosun LEE ,  Ho-Jin LEE ,  Jinho CHUN ,  Ju-il CHOI ,  Yi Koan HONG

IPC: H01L25/16 ,  H01L23/538 ,  H01L23/495 ,  H01L21/48 ,  H01L21/768 ,  H01L21/66 ,  H01L25/00 ,  H01L21/304

CPC classification number: H01L25/50 ,  H01L21/304 ,  H01L21/561 ,  H01L21/76898 ,  H01L22/32 ,  H01L23/3128 ,  H01L23/481 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/08 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/92 ,  H01L24/94 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/0401 ,  H01L2224/05568 ,  H01L2224/0557 ,  H01L2224/05573 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/06181 ,  H01L2224/08146 ,  H01L2224/131 ,  H01L2224/13124 ,  H01L2224/13147 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/9202 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06558 ,  H01L2225/06565 ,  H01L2225/06596 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/81 ,  H01L2224/11 ,  H01L2224/03 ,  H01L2924/00014 ,  H01L2924/014

Abstract: A semiconductor device having a chip stack and an interconnection terminal is provided. The chip stack includes a first semiconductor chip, a second semiconductor chip and a third semiconductor chip stacked on each other. The interconnection terminal is electrically coupled to the chip stack. The first semiconductor chip includes a first front surface and a first backside surface. The second semiconductor chip includes a second front surface, a second backside surface, a second circuit layer and a through-electrode which is electrically coupled to the second circuit layer and penetrates the second semiconductor chip. The third semiconductor chip includes a third front surface, a third backside surface opposite to the third front surface and a third circuit layer adjacent to the third front surface. The first front surface and the second front surface face each other. The third front surface and the second backside surface face each other.

Abstract translation: 提供具有芯片堆叠和互连端子的半导体器件。 芯片堆叠包括彼此堆叠的第一半导体芯片，第二半导体芯片和第三半导体芯片。 互连端子电耦合到芯片堆叠。 第一半导体芯片包括第一正面和第一背面。 第二半导体芯片包括电耦合到第二电路层并穿透第二半导体芯片的第二前表面，第二背面，第二电路层和贯通电极。 第三半导体芯片包括第三前表面，与第三前表面相对的第三背面和与第三前表面相邻的第三电路层。 第一前表面和第二前表面彼此面对。 第三前表面和第二后侧表面彼此面对。

公开(公告)号：US08878215B2

公开(公告)日：2014-11-04

申请号：US13412820

申请日：2012-03-06

Applicant: Jun Seok Park ,  Ho Jin Lee

Inventor： Jun Seok Park ,  Ho Jin Lee

IPC: H01L33/60 ,  H01L33/52

CPC classification number: H01L33/54 ,  H01L33/002 ,  H01L33/06 ,  H01L33/10 ,  H01L33/44 ,  H01L33/48 ,  H01L33/483 ,  H01L33/507 ,  H01L33/52 ,  H01L33/58 ,  H01L33/62 ,  H01L33/644 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2924/00014

Abstract: Disclosed is a light emitting device module. The light emitting device module includes a first lead frame and a second lead frame electrically separated from each other, a light emitting device electrically connected to the first lead frame and the second lead frame, the light emitting device includes a light emitting structure having a first conduction type semiconductor layer, an active layer, and a second conduction type semiconductor layer, a dam disposed at the peripheral area of the light emitting device, a resin layer surrounding the light emitting device and disposed at the inner area of the dam, and a reflective member disposed at the peripheral area of the dam and including an inclined plane formed on at least one side surface thereof.

Abstract translation: 公开了一种发光器件模块。 发光器件模块包括彼此电分离的第一引线框架和第二引线框架，电连接到第一引线框架和第二引线框架的发光器件，发光器件包括发光结构，其具有第一 导电型半导体层，有源层和第二导电型半导体层，设置在发光器件的周边区域的堤坝，围绕发光器件并设置在坝的内部区域的树脂层，以及 反射构件设置在坝的周边区域并且包括形成在其至少一个侧表面上的倾斜平面。

公开(公告)号：US08619859B2

公开(公告)日：2013-12-31

申请号：US11779415

申请日：2007-07-18

Applicant: Sang-jo Lee ,  Ho-jin Lee ,  Do-hyung Kim

Inventor： Sang-jo Lee ,  Ho-jin Lee ,  Do-hyung Kim

IPC: H04N7/12

CPC classification number: H04N19/57 ,  H04N19/51 ,  H04N19/533 ,  H04N19/56

Abstract: Provided are a motion estimation apparatus and method and an image encoding apparatus and method employing the same. The motion estimation apparatus includes an optimal motion estimation unit performing motion estimation in an initial block mode while skipping remaining block modes excluding the initial block mode from a plurality of block modes of the current block, or performing motion estimation in candidate block modes determined from the plurality of block modes.

Abstract translation: 提供了一种运动估计装置和方法以及采用该运动估计装置和方法的图像编码装置和方法。 运动估计装置包括：最优运动估计单元，在从当前块的多个块模式中跳过除了初始块模式之外的剩余块模式时，以初始块模式执行运动估计，或者在从所述块模式确定的候选块模式中执行运动估计 多个块模式。