公开(公告)号：US09449822B2

公开(公告)日：2016-09-20

申请号：US12846020

申请日：2010-07-29

申请人： Wai-Kin Li ,  Wu-Song Huang ,  Joy Cheng ,  Kuang-Jung Chen

发明人： Wai-Kin Li ,  Wu-Song Huang ,  Joy Cheng ,  Kuang-Jung Chen

IPC分类号： H01L21/033

CPC分类号： H01L21/0337 ,  H01L21/0338

摘要： Embodiments of the present invention provide a method of forming a semiconductor structure. The method includes forming a set of shapes on top of a substrate; applying a layer of copolymer covering the substrate; causing the copolymer to form a plurality of cylindrical blocks both inside and outside the shapes; forming a pattern of contact holes from the plurality of cylindrical blocks; and transferring the pattern of contact holes to the substrate to form the semiconductor structure. In one embodiment, the shapes are rings and forming the set of shapes includes forming a set of rings that are equally and squarely spaced. In another embodiment, causing the copolymer to form the plurality of cylindrical blocks includes forming only one cylindrical block inside each of the rings and only one cylindrical block outside every four (4) squarely neighboring rings.

摘要翻译： 本发明的实施例提供一种形成半导体结构的方法。 该方法包括在衬底的顶部上形成一组形状; 涂覆覆盖基材的共聚物层; 使共聚物在形状内部和外部形成多个圆柱形块; 从所述多个圆柱形块形成接触孔的图案; 并将接触孔的图案转移到衬底以形成半导体结构。 在一个实施例中，形状是环，并且形成一组形状包括形成均匀且平直间隔的一组环。 在另一个实施方案中，使共聚物形成多个圆柱形块包括仅在每个环内形成一个圆柱形块，并且在每四（4）个正方形相邻的环周围仅形成一个圆柱形块。

公开(公告)号：US09316916B2

公开(公告)日：2016-04-19

申请号：US12419403

申请日：2009-04-07

申请人： Kuang-Jung Chen ,  Wu-Song Huang ,  Wai-kin Li

发明人： Kuang-Jung Chen ,  Wu-Song Huang ,  Wai-kin Li

IPC分类号： G03F7/207 ,  G03F7/40 ,  G03F7/00 ,  G03F7/20 ,  G03F7/38

CPC分类号： G03F7/40 ,  G03F7/0035 ,  G03F7/2024 ,  G03F7/203 ,  G03F7/2041 ,  G03F7/38

摘要： A method to mitigate resist pattern critical dimension (CD) variation in a double-exposure process generally includes forming a photoresist layer over a substrate; exposing the photoresist layer to a first radiation; developing the photoresist layer to form a first pattern in the photoresist layer; forming a topcoat layer over the photoresist layer; exposing the topcoat layer and the photoresist layer to a second radiation; removing the topcoat layer; and developing the photoresist layer to form a second pattern in the photoresist layer.

摘要翻译： 减轻双曝光工艺中抗蚀剂图案临界尺寸（CD）变化的方法通常包括在衬底上形成光致抗蚀剂层; 将光致抗蚀剂层暴露于第一辐射; 显影光致抗蚀剂层以在光致抗蚀剂层中形成第一图案; 在光致抗蚀剂层上形成顶涂层; 将顶涂层和光致抗蚀剂层暴露于第二辐射; 去除顶涂层; 并且在光致抗蚀剂层中显影光致抗蚀剂层以形成第二图案。

公开(公告)号：US08856693B2

公开(公告)日：2014-10-07

申请号：US13606055

申请日：2012-09-07

申请人： Joy Cheng ,  Kafai Lai ,  Wai-Kin Li ,  Young-Hye Na ,  Jed Walter Pitera ,  Charles Thomas Rettner ,  Daniel Paul Sanders ,  Da Yang

发明人： Joy Cheng ,  Kafai Lai ,  Wai-Kin Li ,  Young-Hye Na ,  Jed Walter Pitera ,  Charles Thomas Rettner ,  Daniel Paul Sanders ,  Da Yang

IPC分类号： G06F17/50 ,  G03F7/00 ,  G03F1/38

CPC分类号： G03F1/38 ,  B82Y10/00 ,  B82Y40/00 ,  G03F1/00 ,  G03F7/0002

摘要： A method and a computer system for designing an optical photomask for forming a prepattern opening in a photoresist layer on a substrate wherein the photoresist layer and the prepattern opening are coated with a self-assembly material that undergoes directed self-assembly to form a directed self-assembly pattern. The methods includes: generating a mask design shape from a target design shape; generating a sub-resolution assist feature design shape based on the mask design shape; using a computer to generate a prepattern shape based on the sub-resolution assist feature design shape; and using a computer to evaluate if a directed self-assembly pattern of the self-assembly material based on the prepattern shape is within specified ranges of dimensional and positional targets of the target design shape on the substrate.

摘要翻译： 一种用于设计光学掩模的方法和计算机系统，用于在基底上的光致抗蚀剂层中形成预模式开口，其中光致抗蚀剂层和预图案开口用自组装材料涂覆，所述自组装材料经过定向自组装以形成定向自身 装配模式 所述方法包括：从目标设计形状生成掩模设计形状; 基于掩模设计形状产生子分辨率辅助特征设计形状; 使用计算机基于子分辨率辅助特征设计形状生成预绘图形状; 并且使用计算机来评估基于预图案形状的自组装材料的定向自组装图案是否在基板上的目标设计形状的尺寸和位置目标的指定范围内。

公开(公告)号：US08835305B2

公开(公告)日：2014-09-16

申请号：US13562953

申请日：2012-07-31

申请人： Chih-Chao Yang ,  Shyng-Tsong Chen ,  Samuel S. Choi ,  Steven J. Holmes ,  David V. Horak ,  Charles W. Koburger, III ,  Wai-Kin Li ,  Christopher J. Penny ,  Shom Ponoth ,  Yunpeng Yin

发明人： Chih-Chao Yang ,  Shyng-Tsong Chen ,  Samuel S. Choi ,  Steven J. Holmes ,  David V. Horak ,  Charles W. Koburger, III ,  Wai-Kin Li ,  Christopher J. Penny ,  Shom Ponoth ,  Yunpeng Yin

IPC分类号： H01L21/4763 ,  H01L23/12 ,  H01L21/768 ,  H01L23/522

CPC分类号： H01L23/53295 ,  H01L21/76807 ,  H01L21/76813 ,  H01L21/76831 ,  H01L21/76844 ,  H01L23/481 ,  H01L23/5226 ,  H01L23/528 ,  H01L2924/0002 ,  H01L2924/00

摘要： The profile of a via can be controlled by forming a profile control liner within each via opening that is formed into a dielectric material prior to forming a line opening within the dielectric material. The presence of the profile control liner within each via opening during the formation of the line opening prevents rounding of the corners of a dielectric material portion that is present beneath the line opening and adjacent the via opening.

摘要翻译： 可以通过在形成介电材料之前形成电介质材料的每个通孔开口内形成轮廓控制衬垫来控制通孔的轮廓，然后在电介质材料内形成线路开口。 在形成线路开口期间在每个通孔开口内存在轮廓控制衬垫防止存在于线路开口下方并且邻近通孔开口的电介质材料部分的拐角的四舍五入。

公开(公告)号：US08772941B2

公开(公告)日：2014-07-08

申请号：US12206314

申请日：2008-09-08

申请人： Lawrence A. Clevenger ,  Matthew E. Colburn ,  Louis C. Hsu ,  Wai-Kin Li

发明人： Lawrence A. Clevenger ,  Matthew E. Colburn ,  Louis C. Hsu ,  Wai-Kin Li

IPC分类号： H01L23/522

CPC分类号： H01L21/76808 ,  H01L21/7682

摘要： A method for manufacturing a circuit includes the step of providing a first wiring level comprising first wiring level conductors separated by a first wiring level dielectric material. A first dielectric layer with a plurality of interconnect openings and a plurality of gap openings is formed above the first wiring level. The interconnect openings and the gap openings are pinched off with a pinching dielectric material to form relatively low dielectric constant (low-k) volumes in the gap openings. Metallic conductors comprising second wiring level conductors and interconnects to the first wiring level conductors are formed at the interconnect openings while maintaining the relatively low-k volumes in the gap openings. The gap openings with the relatively low-k volumes reduce parasitic capacitance between adjacent conductor structures formed by the conductors and interconnects.

摘要翻译： 一种制造电路的方法包括提供包括由第一布线层介电材料分隔开的第一布线层导体的第一布线层的步骤。 具有多个互连开口和多个间隙开口的第一介电层形成在第一布线层的上方。 互连开口和间隙开口用夹持电介质材料夹紧，以在间隙开口中形成相对较低的介电常数（低k）体积。 包括第二布线层导体的金属导体和与第一布线层导体的互连形成在互连开口处，同时保持间隙开口中相对低的k体积。 具有相对低k体积的间隙开口减小由导体和互连件形成的相邻导体结构之间的寄生电容。

公开(公告)号：US08394573B2

公开(公告)日：2013-03-12

申请号：US12883442

申请日：2010-09-16

申请人： Wu-Song Huang ,  Kuang-Jung Chen ,  Wai-Kin Li ,  Sen Liu

发明人： Wu-Song Huang ,  Kuang-Jung Chen ,  Wai-Kin Li ,  Sen Liu

IPC分类号： G03F7/00 ,  G03F7/004 ,  G03F7/40

CPC分类号： G03F7/40 ,  G03F7/0045 ,  G03F7/0397 ,  G03F7/405

摘要： A method for reducing a photoresist critical dimension, the method comprising depositing a photoresist film on a substrate, wherein the photoresist film includes a thermal base generator; patterning the photoresist film to form a first patterned film possessing a first critical dimension; depositing a crosslinkable film over the first patterned film; heat-activating the first patterned film, either before or after depositing the crosslinkable film, to release a base in the first patterned film and cause crosslinking in the crosslinkable film in contact with the first patterned film; and developing the crosslinkable film to remove non-crosslinked soluble portions therein to form a second patterned film possessing a reduced critical dimension compared to the first critical dimension.

摘要翻译： 一种降低光致抗蚀剂临界尺寸的方法，所述方法包括在基底上沉积光致抗蚀剂膜，其中光致抗蚀剂膜包括热碱发生器; 图案化光致抗蚀剂膜以形成具有第一临界尺寸的第一图案化膜; 在第一图案化膜上沉积可交联膜; 在沉积可交联膜之前或之后热激活第一图案化膜，以释放第一图案化膜中的碱，并引起与第一图案化膜接触的可交联膜的交联; 并且显影所述可交联膜以除去其中的非交联的可溶部分以形成与第一临界尺寸相比具有降低的临界尺寸的第二图案化膜。

公开(公告)号：US20130001484A1

公开(公告)日：2013-01-03

申请号：US13608409

申请日：2012-09-10

申请人： Martin Glodde ,  Dario L. Goldfarb ,  Wu-Song Huang ,  Wai-Kin Li ,  Sen Liu ,  Pushkara R. Varanasi ,  Libor Vyklicky

发明人： Martin Glodde ,  Dario L. Goldfarb ,  Wu-Song Huang ,  Wai-Kin Li ,  Sen Liu ,  Pushkara R. Varanasi ,  Libor Vyklicky

IPC分类号： G02B5/24

CPC分类号： G03F7/091 ,  G03F9/7026

摘要： A curable liquid formulation containing at least (i) one or more near-infrared absorbing triphenylamine-based dyes, and (ii) one or more casting solvents. The invention is also directed to solid near-infrared absorbing films composed of crosslinked forms of the curable liquid formulation. The invention is also directed to a microelectronic substrate containing a coating of the solid near-infrared absorbing film as well as a method for patterning a photoresist layer coated on a microelectronic substrate in the case where the near-infrared absorbing film is between the microelectronic substrate and a photoresist film.

摘要翻译： 包含至少（i）一种或多种近红外吸收性三苯胺类染料的可固化液体制剂，和（ii）一种或多种浇铸溶剂。 本发明还涉及由可固化液体制剂的交联形式组成的固体近红外吸收膜。 本发明还涉及一种含有固体近红外线吸收膜的涂层的微电子衬底，以及在近红外吸收膜位于微电子衬底之间的情况下，用于图案化涂覆在微电子衬底上的光刻胶层的方法 和光刻胶膜。

公开(公告)号：US08336003B2

公开(公告)日：2012-12-18

申请号：US12708570

申请日：2010-02-19

申请人： Joy Cheng ,  Kafai Lai ,  Wai-Kin Li ,  Young-Hye Na ,  Jed Walter Pitera ,  Charles Thomas Rettner ,  Daniel Paul Sanders ,  Da Yang

发明人： Joy Cheng ,  Kafai Lai ,  Wai-Kin Li ,  Young-Hye Na ,  Jed Walter Pitera ,  Charles Thomas Rettner ,  Daniel Paul Sanders ,  Da Yang

IPC分类号： G06F17/50

CPC分类号： G03F1/38 ,  B82Y10/00 ,  B82Y40/00 ,  G03F1/00 ,  G03F7/0002

摘要： A method and a computer system for designing an optical photomask for forming a prepattern opening in a photoresist layer on a substrate wherein the photoresist layer and the prepattern opening are coated with a self-assembly material that undergoes directed self-assembly to form a directed self-assembly pattern. The methods includes: generating a mask design shape from a target design shape; generating a sub-resolution assist feature design shape based on the mask design shape; using a computer to generate a prepattern shape based on the sub-resolution assist feature design shape; and using a computer to evaluate if a directed self-assembly pattern of the self-assembly material based on the prepattern shape is within specified ranges of dimensional and positional targets of the target design shape on the substrate.

摘要翻译： 一种用于设计光学掩模的方法和计算机系统，用于在基底上的光致抗蚀剂层中形成预模式开口，其中光致抗蚀剂层和预图案开口用自组装材料涂覆，所述自组装材料经过定向自组装以形成定向自身 装配模式 所述方法包括：从目标设计形状生成掩模设计形状; 基于掩模设计形状产生子分辨率辅助特征设计形状; 使用计算机基于子分辨率辅助特征设计形状生成预绘图形状; 并且使用计算机来评估基于预图案形状的自组装材料的定向自组装图案是否在基板上的目标设计形状的尺寸和位置目标的指定范围内。

公开(公告)号：US08330937B2

公开(公告)日：2012-12-11

申请号：US12511883

申请日：2009-07-29

申请人： Sajan Marokkey ,  Wai-Kin Li ,  Todd C. Bailey

发明人： Sajan Marokkey ,  Wai-Kin Li ,  Todd C. Bailey

IPC分类号： G03B27/54 ,  G03B27/52 ,  G01N21/00

CPC分类号： G03F7/7085 ,  G03F7/70558 ,  G03F7/70941

摘要： A lithography system with a stray light feedback system is disclosed. The stray light feedback helps control critical dimension (CD) within a stray light specification limit. A stray light dose control factor is calculated as a function of the stray light measured in the exposure tool and the sensitivity of the resist. The stray light dose control factor is used to adjust the exposure dose to achieve the desired CD. The stray light may be monitored, and if a threshold level of stray light is reached or exceeded, the use of the exposure tool may be discontinued for a particular type of semiconductor product, resist, or mask level, until the lens system is cleaned.

摘要翻译： 公开了具有杂散光反馈系统的光刻系统。 杂散光反馈有助于控制杂散光规格限制内的关键尺寸（CD）。 根据曝光工具中测量的杂散光和抗蚀剂的灵敏度计算杂光光剂量控制因子。 杂散光剂量控制因子用于调整曝光剂量以达到所需的CD。 可以监测杂散光，并且如果达到或超过杂散光的阈值水平，则可以针对特定类型的半导体产品，抗蚀剂或掩模级别停止使用曝光工具，直到透镜系统被清洁。

公开(公告)号：US20120228743A1

公开(公告)日：2012-09-13

申请号：US13480317

申请日：2012-05-24

申请人： O Seo Park ,  Wai-Kin Li

发明人： O Seo Park ,  Wai-Kin Li

IPC分类号： H01L21/311 ,  H01L21/66 ,  G06F17/50 ,  G03F1/32 ,  G03F1/36 ,  G03F1/26 ,  G03F1/30 ,  H01L29/02 ,  G03B27/68

CPC分类号： H01L21/31144 ,  G03F1/144 ,  G03F1/36 ,  G03F1/80 ,  H01L22/12 ,  H01L22/20

摘要： Methods of manufacturing semiconductor devices and methods of optical proximity correction methods are disclosed. In one embodiment, a method of manufacturing a semiconductor device includes determining an amount of reactive ion etch (RIE) lag of a RIE process for a material layer of the semiconductor device, and adjusting a size of at least one pattern for a feature of the material layer by an adjustment amount to partially compensate for the amount of RIE lag determined.

摘要翻译： 公开了制造半导体器件的方法和光学邻近校正方法的方法。 在一个实施例中，制造半导体器件的方法包括确定用于半导体器件的材料层的RIE工艺的反应离子蚀刻（RIE）滞后量，以及调整用于所述半导体器件的特征的至少一个图案的尺寸 材料层通过调整量来部分补偿确定的RIE滞后量。