Abstract:
A method for making a prismatic laminate includes the steps of: a) forming a back-coating roller having a roller surface with a plurality of recesses arranged in a predetermined pattern and produced by laser holography; b) preparing a prismatic structure including a plate body having a first surface and a second surface opposite to the first surface, and a plurality of prismatic strips formed on the first surface of the plate body; c) applying a coating containing a resin component and an antistatic agent on the second surface of the plate body; and d) embossing the coating with the back-coating roller to form an optical layer including a plurality of microstructures protruding in a direction away from the second surface of the plate body and having a pattern corresponding to that of the recesses in the roller surface.
Abstract:
A built-in module for an inverter and having tension control with integrated tension and velocity closed loops, where required tension feedbacks can be obtained by internal calculations of the inverter or feedback signals of a tension sensor. The tension control module is applied to provide a tension control for a winding mechanism which is operated by driving at least one motor. The tension control module firstly builds a tension control to provide a balanced tension to the winding mechanism. Afterward, the tension control module builds a velocity control to provide an accelerated or decelerated adjustment for the winding mechanism. Accordingly, the winding mechanism can stably maintain a tension-balanced operation.
Abstract:
The present invention relates to compounds of the Formula (I) and (II) wherein R, R21, R25-R33, m, n, X21-X23, and Q1 are defined herein. The compounds modulate protein kinase enzymatic activity to modulate cellular activities such as proliferation, differentiation, programmed cell death, migration and chemoinvasion. Compounds of the invention inhibit, regulate and/or modulate kinases, particularly p70S6 and/or Akt kinases. Methods of using and preparing the compounds, and pharmaceutical compositions thereof, to treat kinase-dependent diseases and conditions are also an aspect of the invention.
Abstract:
An annealing method includes performing an activation annealing on a wafer with a peak temperature of greater than about 1200° C., wherein the activation annealing has a first duration; and performing a defect-recovery annealing on the wafer at a defect-recovery temperature lower than the peak temperature for a second duration. The second duration is longer than the first duration. The annealing method includes no additional annealing steps at temperatures greater than about 1200° C., and no room-temperature cooling step exists between the activation annealing and the defect-recovery annealing.
Abstract:
A chip scale package structure and a method for fabricating the same are disclosed. The method includes forming metal pads on a predetermined part of a carrier; mounting chips on the carrier, each of the chips having a plurality of conductive bumps soldered to the metal pads; forming an encapsulant on the carrier to encapsulate the chips and the conductive bumps; removing the carrier to expose the metal pads and even the metal pads with a surface of the encapsulant; forming on the encapsulant a plurality of first conductive traces electrically connected to the metal pads; applying a solder mask on the first conductive traces, and forming a plurality of openings on the solder mask to expose a predetermined part of the first conductive traces; forming a plurality of conductive elements on the predetermined part; and cutting the encapsulant to form a plurality of chip scale package structures.
Abstract:
A manufacturing method and a structure of a surface-mounting type diode co-constructed from a silicon wafer and a base plate, in the method, a diffused wafer is stacked with a high temperature durable high strength base plate to have them sintered and molten together for connecting with each other to form a co-constructure; then the diffused wafer is processed by etching and ditching for filling with insulation material, electrodes of the diffused wafer are metalized and all on an identical plane, then production of all functional lines is completed; and then the co-constructure is cut to form a plurality of separated individuals which each forms a surface-mounting type diode to be applied straight. In comparison with the conventional techniques, manufacturing of the present invention is simplified and economic in reducing working hours, size and cost of production and the wafer is not subjected to breaking during manufacturing.
Abstract:
A semiconductor device having conductive bumps and a fabrication method thereof are provided. The fabrication method mainly including steps of: providing a semiconductor substrate having a solder pad and a passivation layer formed thereon with a portion of the solder pads exposed from the passivation layer; disposing a first metal layer on the solder pad and a portion of the passivation layer around the solder pad; disposing a covering layer on the first metal layer and the passivation layer, and forming an aperture in the covering layer to expose a portion of the first metal layer, wherein a center of the aperture is deviated from that of the solder pad; deposing a metal pillar on the portion of the first metal layer; and deposing a solder material on an outer surface of the metal pillar for providing a better buffering effect.
Abstract:
In aligning ends of optical fibers, e.g. ends of large mode area double-clad fibers (LMA-DCFs), in a fiber optic fusion splicer the best position of the object plane of the optical system for observing images of the cores of the fiber ends are first determined by maximizing the contrast of the core image, in particular the core image peak in intensity profiles. The alignment process may be performed by adjusting the offset distance between the observed cores in some suitable way, e.g. by using a cascade technique. In e.g. a process for prealigning the fiber ends the self-focusing effect of optical fibers can be used to first determine the best object plane position for observing the self-focusing effect and then the very pre-alignment operation can be performed. This may extend the range of image analysis allowing e.g. that alignment, in particular core alignment, can be performed without requiring direct information showing the position of sides or edges of the claddings in captured pictures.
Abstract:
A semiconductor package with a heat dissipating structure is provided. The heat dissipating structure includes a flat portion, and a plurality of support portions formed at edge corners of the flat portion for supporting the flat portion above a chip mounted on a substrate. The support portions are mounted at predetermined area on the substrate without interfering with arrangement of the chip and bonding wires that electrically connect the chip to the substrate. The support portions are arranged to form a space embraced by adjacent supports and the flat portion, so as to allow the bonding wires to pass through the space to reach area on the substrate outside coverage of the heat dissipating structure; besides, passive components or other electronic components can be mounted on the substrate at area within or outside the coverage of the heat dissipating structure, thereby improving flexibility in component arrangement in the semiconductor package.