公开(公告)号：US20170098076A1

公开(公告)日：2017-04-06

申请号：US15379974

申请日：2016-12-15

Applicant: VIA TECHNOLOGIES, INC.

Inventor： G. GLENN HENRY

IPC: G06F21/57 ,  H04L9/32 ,  G06F13/24 ,  G06F13/42 ,  G06F9/44 ,  H04L29/06

CPC classification number: G06F21/572 ,  G06F9/4401 ,  G06F13/24 ,  G06F13/4282 ,  G06F21/554 ,  G06F2221/2107 ,  H04L9/06 ,  H04L9/0618 ,  H04L9/0869 ,  H04L9/3231 ,  H04L9/3242 ,  H04L63/0435 ,  H04L63/0876 ,  H04L63/123

Abstract: An apparatus is provided for protecting a basic input/output system (BIOS) in a computing system. The apparatus includes a BIOS read only memory (ROM), an event detector, and a tamper detector. The BIOS ROM has BIOS contents that are stored as plaintext, and an encrypted message digest, where the encrypted message digest comprises an encrypted version of a first message digest that corresponds to the BIOS contents, and where and the encrypted version is generated via a symmetric key algorithm and a key. The event detector is configured to generate a BIOS check interrupt that interrupts normal operation of the computing system upon the occurrence of an event, where the event includes one or more occurrences of a hard disk access. The tamper detector is operatively coupled to the BIOS ROM and is configured to access the BIOS contents and the encrypted message digest upon assertion of the BIOS check interrupt, and is configured to direct a microprocessor to generate a second message digest corresponding to the BIOS contents and a decrypted message digest corresponding to the encrypted message digest using the symmetric key algorithm and the key, and is configured to compare the second message digest with the decrypted message digest, and configured to preclude the operation of the microprocessor if the second message digest and the decrypted message digest are not equal. The microprocessor includes a dedicated crypto/hash unit disposed within execution logic, where the crypto/hash unit generates the second message digest and the decrypted message digest, and where the key is exclusively accessed by the crypto/hash unit. The microprocessor further has a random number generator disposed within the execution logic, where the random number generator generates a random number at completion of a current BIOS check, which is employed by the event detector to randomly set a number of occurrences of the event that are to occur before a following BIOS check.

公开(公告)号：US09606951B2

公开(公告)日：2017-03-28

申请号：US14152343

申请日：2014-01-10

Applicant: VIA TECHNOLOGIES, INC.

Inventor： Chia-Ying Kuo

IPC: G06F13/40 ,  G06F13/14 ,  G06F9/44

CPC classification number: G06F13/4027 ,  G06F9/4411 ,  G06F13/14 ,  G06F2213/0042

Abstract: An interface controller, coupling a device main body of an external electronic device to a host, is disclosed, which transmits a termination-on signal to the host prior to a mechanically stable state of a device main body of the external electronic device. When the device main body has not reached the mechanically stable state yet, the interface controller responds to the host with default link information in a delayed manner. The default link information is contained in the interface controller. When the device main body reaches the mechanically stable state, the interface controller transmits specific link information retrieved from the device main body to the host.

公开(公告)号：US09606597B2

公开(公告)日：2017-03-28

申请号：US14205790

申请日：2014-03-12

Applicant: VIA TECHNOLOGIES, INC.

Inventor： Yi-Te Chen

IPC: G06F1/26 ,  H02J1/00 ,  H02J1/10

CPC classification number: G06F1/26 ,  G06F1/266 ,  H02J1/10

Abstract: An intermediate electronic device, arranged to be coupled to a host system and an electronic device. The intermediate electronic device includes: a controller, enabled by an enable signal to process the data transmission between the host system and the electronic device; and a power transmission unit disposed between the host system and the electronic device. The power transmission units detect whether the power transmission unit is coupled to the host system or an external power source. When the power transmission unit detects that the power transmission unit is coupled to the host system, but not coupled to the external power source, the power transmission unit informs the host system to raise the voltage output to the intermediate electronic device to supply power to the electronic device, and outputs the enable signal.

公开(公告)号：US09588769B2

公开(公告)日：2017-03-07

申请号：US14315122

申请日：2014-06-25

Applicant: VIA TECHNOLOGIES, INC.

Inventor： Gerard M. Col ,  Matthew Daniel Day

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F9/30069 ,  G06F9/30032 ,  G06F9/384 ,  G06F9/3855

Abstract: A processor performs out-of-order execution of a first instruction and a second instruction after the first instruction in program order, the first instruction includes source and destination indicators, the source indicator specifies a source of data, the destination indicator specifies a destination of the data, the first instruction instructs the processor to move the data from the source to the destination, the second instruction specifies a source indicator that specifies a source of data. A rename unit updates the second instruction source indicator with the first instruction source indicator if there are no intervening instructions that write to the source or to the destination of the first instruction and the second instruction source indicator matches the first instruction destination indicator.

Abstract translation: 处理器以程序顺序执行在第一指令之后的第一指令和第二指令的无序执行，第一指令包括源和目标指示符，源指示符指定数据源，目的地指示符指定 数据，第一指令指示处理器将数据从源移动到目的地，第二指令指定指定数据源的源指示符。 如果没有写入到第一指令的源或目的地的第二指令源指示符，并且第二指令源指示符与第一指令目标指示符匹配，则重命名单元用第一指令源指示符更新第二指令源指示符。

公开(公告)号：US09583555B2

公开(公告)日：2017-02-28

申请号：US14813510

申请日：2015-07-30

Applicant: VIA TECHNOLOGIES, INC.

Inventor： Sheng-Yuan Lee

IPC: H01L23/522 ,  H01L49/02 ,  H01L27/02

CPC classification number: H01L28/10 ,  H01L23/5227 ,  H01L27/0248 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device including a first insulating layer and a second insulating layer sequentially disposed on a substrate having a center region. The semiconductor device includes a first winding portion and a second winding portion disposed in the second insulating layer and surrounding the center region A second conductive line and a third conductive line are arranged from the inside to the outside. In addition, each of the first, second and third conductive lines has a first end and a second end. The semiconductor device also includes a coupling portion disposed in the first and second insulating layers between the first and second winding portions, and having a first pair of connection layers cross-connecting the second ends of the first and second conductive lines, and a second pair of connection layers cross-connecting the first ends of the second and third conductive lines.

Abstract translation: 一种半导体器件，包括顺序地设置在具有中心区域的衬底上的第一绝缘层和第二绝缘层。 半导体器件包括设置在第二绝缘层中并围绕中心区域的第一绕组部分和第二绕组部分，从内向外布置第二导线和第三导线。 此外，第一，第二和第三导线中的每一个具有第一端和第二端。 该半导体器件还包括一个耦合部分，设置在第一和第二绕组部分之间的第一和第二绝缘层中，并具有交叉连接第一和第二导线的第二端的第一对连接层，以及第二对 的连接层交叉连接第二和第三导线的第一端。

公开(公告)号：US09582670B2

公开(公告)日：2017-02-28

申请号：US14463991

申请日：2014-08-20

Applicant: VIA TECHNOLOGIES, INC.

Inventor： Lei Feng

IPC: G06F21/60 ,  G06F21/79 ,  G06F21/85

CPC classification number: G06F21/602 ,  G06F21/79 ,  G06F21/85

Abstract: A data scrambling and descrambling technology based on logical addresses. A data storage device with the data scrambling and descrambling technology includes a non-volatile memory and a controller. The controller generates a data scrambling seed according to a logical writing address issued from the host, scrambles the write data issued from the host with the data scrambling seed and then stores the scrambled write data into the non-volatile memory. The controller further generates a data descrambling seed according to a logical reading address issued from the host, and descrambles the read data retrieved from the non-volatile memory by the data descrambling seed. The controller further processes the descrambled read data for data checking and correction.

Abstract translation: 基于逻辑地址的数据加扰和解扰技术。 具有数据加扰和解扰技术的数据存储设备包括非易失性存储器和控制器。 控制器根据从主机发出的逻辑写入地址生成数据加扰种子，用数据加扰种子对从主机发出的写入数据进行加扰，然后将加扰的写入数据存储到非易失性存储器中。 控制器还根据从主机发出的逻辑读取地址生成数据解扰种子，并通过数据解扰种子解扰从非易失性存储器检索的读取数据。 控制器进一步处理解扰的读取数据用于数据检查和校正。

公开(公告)号：US09575541B2

公开(公告)日：2017-02-21

申请号：US14281796

申请日：2014-05-19

Applicant: VIA TECHNOLOGIES, INC.

Inventor： G. Glenn Henry ,  Stephan Gaskins

IPC: G06F15/16 ,  G06F1/04 ,  G06F1/32 ,  G06F12/08 ,  G06F13/24 ,  G06F9/44 ,  G06F9/38 ,  G06F9/30 ,  G06F1/12

CPC classification number: G06F9/3885 ,  G06F1/04 ,  G06F1/12 ,  G06F1/3203 ,  G06F1/3237 ,  G06F1/324 ,  G06F1/3287 ,  G06F1/3296 ,  G06F9/30032 ,  G06F9/30047 ,  G06F9/30079 ,  G06F9/30087 ,  G06F9/30105 ,  G06F9/30145 ,  G06F9/3802 ,  G06F9/3861 ,  G06F9/4403 ,  G06F9/4405 ,  G06F9/4411 ,  G06F9/4418 ,  G06F12/0808 ,  G06F12/084 ,  G06F12/0875 ,  G06F13/24 ,  G06F13/364 ,  G06F13/42 ,  G06F21/53 ,  G06F21/57 ,  G06F2212/452 ,  G06F2212/6028 ,  G06F2212/62 ,  H01L22/34 ,  H04L9/0877 ,  H04L9/0897 ,  Y02B70/12 ,  Y02B70/123 ,  Y02B70/126 ,  Y02B70/30 ,  Y02D10/10 ,  Y02D10/126 ,  Y02D10/128 ,  Y02D10/13 ,  Y02D10/171 ,  Y02D10/172 ,  Y02D10/30 ,  Y02D50/20

Abstract: A microprocessor a plurality of processing cores, wherein each of the plurality of processing cores instantiates a respective architecturally-visible storage resource. A first core of the plurality of processing cores is configured to encounter an architectural instruction that instructs the first core to update the respective architecturally-visible storage resource of the first core with a value specified by the architectural instruction. The first core is further configured to, in response to encountering the architectural instruction, provide the value to each of the other of the plurality of processing cores and update the respective architecturally-visible storage resource of the first core with the value. Each core of the plurality of processing cores other than the first core is configured to update the respective architecturally-visible storage resource of the core with the value provided by the first core without encountering the architectural instruction.

Abstract translation: 一种微处理器，多个处理核心，其中所述多个处理核心中的每一个都实例化相应的体系结构可视存储资源。 多个处理核心的第一核心被配置为遇到指令第一核心以由架构指令指定的值来更新第一核心的各个架构可见存储资源的架构指令。 第一核还被配置为响应于遇到结构指令而向多个处理核心中的另一个处理核心中的每一个提供该值，并用该值来更新第一核心的相应的架构可见存储资源。 除了第一核心之外的多个处理核心的每个核心被配置为利用由第一核心提供的值来更新核心的各个体系结构可见的存储资源，而不会遇到建筑指令。

公开(公告)号：US20170047908A1

公开(公告)日：2017-02-16

申请号：US14976363

申请日：2015-12-21

Applicant: VIA TECHNOLOGIES, INC.

Inventor： Cheng-Chun Yeh

IPC: H03H11/28 ,  H01R24/28 ,  H01R31/06

CPC classification number: H03H11/28 ,  G06F13/4086 ,  Y02D10/14 ,  Y02D10/151

Abstract: A control circuit disposed in a connection line including a first power pin and a second power pin and including a native N-type transistor, a first impedance unit, and a second impedance unit is provided. The native N-type transistor includes a first gate, a first drain and a first source. The first drain is coupled to the first power pin. The first impedance unit is coupled between the first source and the second power pin. The second impedance unit is coupled between the first drain and the first gate. When the voltage level of the first power pin is equal to a pre-determined level, the first gate of the native N-type transistor receives an adjusting signal to adjust an equivalent impedance of the native N-type transistor.

Abstract translation: 设置在包括第一电源引脚和第二电源引脚并且包括天然N型晶体管，第一阻抗单元和第二阻抗单元的连接线中的控制电路。 天然N型晶体管包括第一栅极，第一漏极和第一源极。 第一漏极耦合到第一电源引脚。 第一阻抗单元耦合在第一电源和第二电源引脚之间。 第二阻抗单元耦合在第一漏极和第一栅极之间。 当第一电源引脚的电压电平等于预定电平时，本机N型晶体管的第一栅极接收调整信号以调节天然N型晶体管的等效阻抗。

公开(公告)号：US20170038988A1

公开(公告)日：2017-02-09

申请号：US15333004

申请日：2016-10-24

Applicant: VIA TECHNOLOGIES, INC.

Inventor： Yao-Shun HUNG ,  Chin-Yin TSAI ,  Yi-Lin LAI

IPC: G06F3/06 ,  G06F11/10 ,  G06F9/44

CPC classification number: G06F3/0619 ,  G06F3/0632 ,  G06F3/064 ,  G06F3/0673 ,  G06F9/441 ,  G06F11/073 ,  G06F11/0751 ,  G06F11/076 ,  G06F11/1076 ,  G06F11/1417

Abstract: A memory chip coupled to a host includes a memory and a controller. The memory is pre-loaded with a plurality of boot images, wherein the boot images have the same content. The controller is coupled to the memory, and processes data transmissions between the memory chip and the host, wherein the controller further determines whether the memory chip enters a boot mode for the first time, and when the memory chip enters the boot mode for the first time, the controller accesses the memory to obtain a correct boot image from the boot images and transmits the correct boot image to the host. Further, each boot image includes a plurality of data blocks, and the controller loads a plurality of correct data blocks from one or more of the boot images to obtain the correct boot image.

Abstract translation: 耦合到主机的存储器芯片包括存储器和控制器。 存储器预加载有多个引导映像，其中引导映像具有相同的内容。 控制器耦合到存储器，并且处理存储器芯片和主机之间的数据传输，其中控制器进一步确定存储器芯片是否首次进入引导模式，以及当存储器芯片进入第一个引导模式时 时间，控制器访问内存以从引导映像获取正确的引导映像，并将正确的引导映像传输到主机。 此外，每个引导映像包括多个数据块，并且控制器从一个或多个引导映像加载多个正确的数据块以获得正确的启动映像。

公开(公告)号：US09557765B2

公开(公告)日：2017-01-31

申请号：US13757575

申请日：2013-02-01

Applicant: VIA Technologies, Inc.

Inventor： Vanessa S. Canac ,  James R. Lundberg

IPC: G06F13/42 ,  G06F1/12

CPC classification number: G11C7/1072 ,  G06F1/12 ,  G06F13/3625 ,  G06F13/4068 ,  G06F13/4217 ,  G06F13/4243 ,  G11C8/18

Abstract: An apparatus is provided that compensates for misalignment on a synchronous data bus. The apparatus includes a replica radial distribution element, a bit lag control element, and a synchronous lag receiver that is configured to receive one of a plurality of radially distributed strobes and a data bit, and that is configured to delay registering of the data bit by a propagation time. The replica radial distribution element is configured to receive a first signal, and is configured to generate a second signal, where the replica radial distribution element comprises replicated propagation path lengths, loads, and buffering of a radial distribution network for a strobe. The bit lag control element is configured to measure a propagation time beginning with assertion of the first signal and ending with assertion of the second signal, and is configured to generate a value on a lag bus that indicates the propagation time. The synchronous lag receiver has a first plurality of matched inverters, a first mux, and a bit receiver. The first plurality of matched inverters is configured to generate successively delayed versions of the data bit. The first mux is coupled to the first plurality of matched inverters, and is configured to receive a value on a lag bus that indicates the propagation time, and is configured to select one of the successively delayed versions of the data bit that corresponds to the value. The bit receiver is configured to receive the one of the successively delayed versions of the data bit and one of a plurality of radially distributed strobe signals, and is configured to register the state of the one of the successively delayed versions of the data bit upon assertion of the one of a plurality of radially distributed strobe signals.

Abstract translation: 提供了一种补偿同步数据总线上的未对准的装置。 该装置包括复制径向分布元件，位延迟控制元件和同步延迟接收器，其被配置为接收多个径向分布的选通中的一个和数据位，并且被配置为延迟数据位的寄存 传播时间。 复制径向分布元件被配置为接收第一信号，并且被配置为生成第二信号，其中副本径向分布元件包括用于选通脉冲的径向分布网络的复制传播路径长度，负载和缓冲。 比特滞后控制元件被配置为测量从第一信号的断言开始并以第二信号的断言结束的传播时间，并且被配置为在指示传播时间的滞后总线上生成值。 同步延迟接收器具有第一多个匹配的反相器，第一复用器和位接收器。 第一多个匹配的反相器被配置为产生数据位的连续延迟版本。 第一复用器耦合到第一多个匹配的反相器，并且被配置为在延迟总线上接收指示传播时间的值，并且被配置为选择对应于该值的数据位的连续延迟版本中的一个 。 位接收器被配置为接收数据位的连续延迟版本中的一个和多个径向分布的选通信号中的一个，并且被配置为在断言时注册数据位的连续延迟版本中的一个的状态 的多个径向分布的选通信号中的一个。