公开(公告)号：US20070263862A1

公开(公告)日：2007-11-15

申请号：US11465814

申请日：2006-08-21

Applicant: Tzyy-Jang Tseng ,  Cheng-Po Yu ,  Chi-Min Chang ,  Cheng-Hung Yu

Inventor： Tzyy-Jang Tseng ,  Cheng-Po Yu ,  Chi-Min Chang ,  Cheng-Hung Yu

IPC: G09C3/08

CPC classification number: H05K1/0269 ,  H05K3/0097 ,  H05K3/225 ,  H05K2201/09936 ,  H05K2203/013

Abstract: A manufacturing process and an apparatus for printing imprint on defective board are provided. An automatic printing device is used for replacing operator, so as to reduce manpower and to increase the correctness and veracity of defect mark printing. The manufacturing process includes the following steps: first, an image sensor captures an image of a defect mark and transmits the image to a processing unit for data processing. Next, the data is compared, and an inkjet head is notified of the correct printing position to print ink on the customer identification mark of the printed circuit board.

Abstract translation: 提供了制造工艺和用于在缺陷板上印刷压印的装置。 使用自动打印装置来代替操作者，以减少人力和提高缺陷标记打印的正确性和真实性。 制造过程包括以下步骤：首先，图像传感器捕获缺陷标记的图像，并将图像发送到用于数据处理的处理单元。 接下来，比较数据，并且通知喷墨头正确的打印位置以在印刷电路板的客户识别标记上印刷墨水。

公开(公告)号：US20070087457A1

公开(公告)日：2007-04-19

申请号：US11164855

申请日：2005-12-08

Applicant: Tzyy-Jang Tseng ,  Cheng-Po Yu

Inventor： Tzyy-Jang Tseng ,  Cheng-Po Yu

IPC: H01L21/00

CPC classification number: H05K3/225 ,  H05K1/0269 ,  H05K3/0032 ,  H05K3/064 ,  H05K2203/013

Abstract: A method for inspecting and mending defects of photo-resist is provided. It includes the following steps. First, a substrate having at least one film is provided. Then, a patterned photo-resist layer is formed on the film. Next, an optical inspection procedure is performed to inspect whether the patterned photo-resist layer has defects or not. If the patterned photo-resist layer has defects, the defects are classified into gaps and protrusions and then the gaps and the protrusions are positioned. If the patterned photo-resist layer has defects such as gaps, an ink-jet printing method, for example, is performed on the patterned photo-resist layer to fill the gaps up. If the patterned photo-resist layer has defects such as protrusions, a laser method, for example, is performed on the patterned photo-resist layer to remove the protrusions. So the defects of the patterned photo-resist layer can be mended.

Abstract translation: 提供了一种检查和修补光刻胶缺陷的方法。 它包括以下步骤。 首先，提供具有至少一个膜的基板。 然后，在膜上形成图案化的光致抗蚀剂层。 接下来，执行光学检查程序以检查图案化的光致抗蚀剂层是否具有缺陷。 如果图案的光致抗蚀剂层具有缺陷，则将缺陷分为间隙和突起，然后定位间隙和突起。 如果图案化的光致抗蚀剂层具有诸如间隙的缺陷，则在图案化的光致抗蚀剂层上进行例如喷墨打印方法来填充间隙。 如果图案化的光致抗蚀剂层具有诸如突起的缺陷，则在图案化的光致抗蚀剂层上执行例如激光方法以去除突起。 因此，可以修补图案化光致抗蚀剂层的缺陷。

公开(公告)号：US08466369B2

公开(公告)日：2013-06-18

申请号：US13305310

申请日：2011-11-28

Applicant: Cheng-Po Yu

Inventor： Cheng-Po Yu

IPC: H05K1/03

CPC classification number: H05K3/107 ,  H05K1/0265 ,  H05K3/0032 ,  H05K3/06 ,  H05K3/061 ,  H05K2201/0376 ,  H05K2201/09727 ,  H05K2203/0369 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/49155 ,  Y10T29/49165

Abstract: A circuit structure of a circuit board includes a dielectric layer, a number of first circuits, and a number of second circuits. The dielectric layer has a surface and an intaglio pattern. The first circuits are disposed on the surface of the dielectric layer. The second circuits are disposed in the intaglio pattern of the dielectric layer. Line widths of the second circuits are smaller than line widths of the first circuits, and a distance between every two of the adjacent second circuits is shorter than a distance between every two of the adjacent first circuits.

Abstract translation: 电路板的电路结构包括电介质层，多个第一电路和多个第二电路。 电介质层具有表面和凹版图案。 第一电路设置在电介质层的表面上。 第二电路设置在电介质层的凹版图案中。 第二电路的线宽小于第一电路的线宽，并且相邻的第二电路中的每两个之间的距离比相邻的第一电路中的每两个之间的距离短。

公开(公告)号：US20120174391A1

公开(公告)日：2012-07-12

申请号：US13423578

申请日：2012-03-19

Applicant: Tsung-Yuan Chen ,  Chun-Chien Chen ,  Cheng-Po Yu

Inventor： Tsung-Yuan Chen ,  Chun-Chien Chen ,  Cheng-Po Yu

IPC: H05K3/00

CPC classification number: H05K3/428 ,  H05K3/0032 ,  H05K3/0035 ,  H05K3/0038 ,  H05K3/20 ,  H05K3/205 ,  H05K2201/09509 ,  H05K2201/09563 ,  H05K2201/0969 ,  H05K2203/0369 ,  H05K2203/0376 ,  H05K2203/0384 ,  H05K2203/0554 ,  H05K2203/108 ,  H05K2203/1476 ,  Y10T29/49124 ,  Y10T29/49126

Abstract: A process for fabricating a wiring board is provided. In the process, a wiring carrying substrate including a carry substrate and a wiring layer is formed. Next, at least one blind via is formed in the wiring carrying substrate. Next, the wiring carrying substrate is laminated to another wiring carrying substrate via an insulation layer. The insulation layer is disposed between the wiring layers of the wiring carrying substrates and full fills the blind via. Next, parts of the carry substrates are removed to expose the insulation layer in the blind via. Next, a conductive pillar connected between the wiring layers is formed. Next, the rest carry substrates are removed.

Abstract translation: 提供一种制造布线板的工艺。 在该过程中，形成包括携带衬底和布线层的布线承载衬底。 接下来，在布线承载基板中形成至少一个盲孔。 接下来，通过绝缘层将布线承载基板层叠到另一布线承载基板。 绝缘层设置在布线基板的布线层之间，并且完全填充盲孔。 接下来，去除部分搬运基板以露出盲孔中的绝缘层。 接下来，形成连接在布线层之间的导电柱。 接下来，其余的携带衬底被去除。

公开(公告)号：US08217278B2

公开(公告)日：2012-07-10

申请号：US12613072

申请日：2009-11-05

Applicant: Cheng-Po Yu

Inventor： Cheng-Po Yu

IPC: H05K1/11

CPC classification number: H05K3/0035 ,  H05K3/107 ,  H05K3/465 ,  H05K2201/0236 ,  H05K2201/0959 ,  H05K2201/09845 ,  H05K2203/1476 ,  Y10T29/49155

Abstract: An embedded wiring board includes an upper wiring layer, a lower wiring layer, an insulation layer, a first conductive pillar and a second conductive pillar. The upper wiring layer contains an upper pad, the lower wiring layer contains a lower pad, and the insulation layer contains an upper surface and a lower surface opposite to the upper surface. The upper pad is embedded in the upper surface and the lower pad is embedded in the lower surface. The first conductive pillar is located in the insulation layer and includes an end surface which is exposed by the upper surface. A height of the first conductive pillar relative to the upper surface is larger than a depth of the upper pad relative to the upper surface. In addition, the second conductive pillar is located in the insulation layer and is connected between the first conductive pillar and the lower pad.

Abstract translation: 嵌入布线板包括上布线层，下布线层，绝缘层，第一导电柱和第二导电柱。 上布线层包含上焊盘，下布线层包含下焊盘，绝缘层包含与上表面相对的上表面和下表面。 上垫片嵌入在上表面中，下垫片嵌入下表面。 第一导电柱位于绝缘层中，并且包括由上表面暴露的端面。 第一导电柱相对于上表面的高度大于上垫相对于上表面的深度。 此外，第二导电柱位于绝缘层中并连接在第一导电柱和下垫之间。

公开(公告)号：US20120031652A1

公开(公告)日：2012-02-09

申请号：US13050009

申请日：2011-03-17

Applicant: TZYY-JANG TSENG ,  Chang-Ming Lee ,  Wen-Fang Liu ,  Cheng-Po Yu

Inventor： TZYY-JANG TSENG ,  Chang-Ming Lee ,  Wen-Fang Liu ,  Cheng-Po Yu

IPC: H05K1/00 ,  C25D5/02 ,  H05K3/00 ,  H05K3/10 ,  H05K3/12

CPC classification number: H05K3/12 ,  C23C18/1605 ,  C23C18/165 ,  C25D5/022 ,  H05K1/0203 ,  H05K1/056 ,  H05K3/02 ,  H05K3/181 ,  H05K3/188 ,  H05K3/3436 ,  H05K2201/0187 ,  Y10T29/302 ,  Y10T29/49155 ,  Y10T156/10

Abstract: A circuit board includes a metal pattern layer, a thermally conductive plate, an electrically insulating layer, and at least one electrically insulating material. The thermally conductive plate has a plane. The electrically insulating layer is disposed between the metal pattern layer and the plane and partially covers the plane. The electrically insulating material covers the plane where is not covered by the electrically insulating layer and touches the thermally conductive plate. The electrically insulating layer exposes the electrically insulating material, and a thermal conductivity of the electrically insulating material is larger than a thermal conductivity of the electrically insulating layer.

Abstract translation: 电路板包括金属图案层，导热板，电绝缘层和至少一个电绝缘材料。 导热板具有平面。 电绝缘层设置在金属图案层和平面之间并且部分覆盖平面。 电绝缘材料覆盖未被电绝缘层覆盖并接触导热板的平面。 电绝缘层暴露电绝缘材料，并且电绝缘材料的热导率大于电绝缘层的热导率。

公开(公告)号：US07745933B2

公开(公告)日：2010-06-29

申请号：US11739515

申请日：2007-04-24

Applicant: Cheng-Po Yu

Inventor： Cheng-Po Yu

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC classification number: H05K1/116 ,  H01L21/6835 ,  H01L2221/68359 ,  H05K3/20 ,  H05K3/4644 ,  H05K3/4658 ,  H05K2201/09454 ,  H05K2201/09563 ,  H05K2201/096 ,  Y10T29/49124

Abstract: A circuit structure has a first dielectric layer, a first circuit pattern embedded in the first dielectric layer and having a first via pad, a first conductive via passing through the first dielectric layer and connecting to the first via pad, and an independent via pad disposed on a surface of the first dielectric layer away from the first via pad and connecting to one end of the first conductive via. The circuit structure further has a second dielectric layer disposed over the surface of the first dielectric layer where the independent via pad is disposed, a second conductive via passing through the second dielectric layer and connecting to the independent via pad, and a second circuit pattern embedded in the second dielectric layer, located at a surface thereof away from the independent via pad, and having a second via pad connected to the second conductive via.

Abstract translation: 电路结构具有第一电介质层，第一电路图案，其嵌入在第一电介质层中并且具有第一通孔焊盘，穿过第一电介质层并连接到第一通孔焊盘的第一导电通孔和设置在第一电介质层上的独立通孔焊盘 在第一电介质层的远离第一通孔焊盘的表面上并连接到第一导电通孔的一端。 电路结构还具有设置在第一电介质层的表面上的第二电介质层，其中设置独立通孔焊盘，通过第二介电层并连接到独立通孔焊盘的第二导电通孔和嵌入的第二电路图案 在第二电介质层中，位于其远离独立通孔焊盘的表面，并且具有连接到第二导电通孔的第二通孔焊盘。

公开(公告)号：US20100006327A1

公开(公告)日：2010-01-14

申请号：US12260096

申请日：2008-10-29

Applicant: Cheng-Po Yu ,  Han-Pei Huang

Inventor： Cheng-Po Yu ,  Han-Pei Huang

IPC: H05K1/11 ,  H05K1/00 ,  B29C35/08 ,  C04B35/00

CPC classification number: H05K1/11 ,  H05K1/0284 ,  H05K1/142 ,  H05K3/185 ,  H05K3/4007 ,  H05K3/4661 ,  H05K2201/0236 ,  H05K2201/09045 ,  H05K2201/09118 ,  H05K2201/09163 ,  H05K2201/09436 ,  H05K2201/09509 ,  H05K2201/09845 ,  H05K2203/1327 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49158 ,  Y10T428/24802 ,  Y10T428/24917

Abstract: A circuit board structure including a circuit board main body and an injection molded three-dimensional circuit device encapsulating at least a portion of the circuit board main body is provided. The three-dimensional circuit device includes a molded plastic body having a non-plate type, stereo structure, on which a three-dimensional pattern is also fabricated. The three-dimensional pattern is interconnected with a contact pad on the circuit board main body through a conductive via.

Abstract translation: 提供一种包括电路板主体和封装有电路板主体的至少一部分的注射成型的三维电路装置的电路板结构。 三维电路装置包括具有非板型立体结构的模制塑料体，其上还制造三维图案。 三维图案通过导电通孔与电路板主体上的接触焊盘互连。

公开(公告)号：US20080179744A1

公开(公告)日：2008-07-31

申请号：US11739515

申请日：2007-04-24

Applicant: Cheng-Po Yu

Inventor： Cheng-Po Yu

IPC: H01L23/48

CPC classification number: H05K1/116 ,  H01L21/6835 ,  H01L2221/68359 ,  H05K3/20 ,  H05K3/4644 ,  H05K3/4658 ,  H05K2201/09454 ,  H05K2201/09563 ,  H05K2201/096 ,  Y10T29/49124

Abstract: A circuit structure has a first dielectric layer, a first circuit pattern embedded in the first dielectric layer and having a first via pad, a first conductive via passing through the first dielectric layer and connecting to the first via pad, and an independent via pad disposed on a surface of the first dielectric layer away from the first via pad and connecting to one end of the first conductive via. The circuit structure further has a second dielectric layer disposed over the surface of the first dielectric layer where the independent via pad is disposed, a second conductive via passing through the second dielectric layer and connecting to the independent via pad, and a second circuit pattern embedded in the second dielectric layer, located at a surface thereof away from the independent via pad, and having a second via pad connected to the second conductive via.

Abstract translation: 电路结构具有第一电介质层，第一电路图案，其嵌入在第一电介质层中并且具有第一通孔焊盘，穿过第一电介质层并连接到第一通孔焊盘的第一导电通孔和设置在第一电介质层上的独立通孔焊盘 在第一电介质层的远离第一通孔焊盘的表面上并连接到第一导电通孔的一端。 电路结构还具有设置在第一电介质层的表面上的第二电介质层，其中设置独立通孔焊盘，通过第二介电层并连接到独立通孔焊盘的第二导电通孔和嵌入的第二电路图案 在第二电介质层中，位于其远离独立通孔焊盘的表面，并且具有连接到第二导电通孔的第二通孔焊盘。

公开(公告)号：US20070153488A1

公开(公告)日：2007-07-05

申请号：US11554882

申请日：2006-10-31

Applicant: Ming-Huan Yang ,  Chung-Wei Wang ,  Chia-Chi Wu ,  Chao-Kai Cheng ,  Tzyy-Jang Tseng ,  Chang-Ming Lee ,  Cheng-Po Yu ,  Cheng-Hung Yu

Inventor： Ming-Huan Yang ,  Chung-Wei Wang ,  Chia-Chi Wu ,  Chao-Kai Cheng ,  Tzyy-Jang Tseng ,  Chang-Ming Lee ,  Cheng-Po Yu ,  Cheng-Hung Yu

IPC: H05K7/00 ,  H05K3/10

CPC classification number: H05K3/182 ,  H05K3/389 ,  H05K3/421 ,  H05K3/422 ,  H05K3/426 ,  H05K3/4661 ,  H05K2203/013 ,  H05K2203/0565 ,  H05K2203/0709 ,  Y10T29/49155

Abstract: A method for fabricating a double-sided or multi-layer printed circuit board (PCB) by ink-jet printing that includes providing a substrate, forming a first self-assembly membrane (SAM) on at least one side of the substrate, forming a non-adhesive membrane on the first SAM, forming at least one microhole in the substrate, forming a second SAM on a surface of the microhole, providing catalyst particles on the at least one side of the substrate and on the surface of the microhole, and forming a catalyst circuit pattern on the substrate.

Abstract translation: 一种通过喷墨印刷制造双面或多层印刷电路板（PCB）的方法，其包括提供基板，在所述基板的至少一侧上形成第一自组装膜（SAM），形成 在所述第一SAM上形成非粘性膜，在所述基底中形成至少一个微孔，在所述微孔的表面上形成第二SAM，在所述基底的至少一侧和所述微孔的表面上提供催化剂颗粒，以及 在基板上形成催化剂电路图案。