公开(公告)号：US20120306067A1

公开(公告)日：2012-12-06

申请号：US13151720

申请日：2011-06-02

申请人： Pei-Haw Tsao ,  Kuo-Chin Chang ,  Han-Ping Pu

发明人： Pei-Haw Tsao ,  Kuo-Chin Chang ,  Han-Ping Pu

IPC分类号： H01L23/488 ,  H01L23/36 ,  H01L21/50

CPC分类号： H01L21/568 ,  H01L21/561 ,  H01L23/3128 ,  H01L23/4334 ,  H01L23/49816 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L24/92 ,  H01L2224/12105 ,  H01L2224/13022 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/19 ,  H01L2224/215 ,  H01L2224/221 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73253 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2224/96 ,  H01L2924/01029 ,  H01L2924/10253 ,  H01L2924/15311 ,  H01L2924/15788 ,  H01L2924/181 ,  H01L2224/11 ,  H01L2924/00014 ,  H01L2924/01047 ,  H01L2924/0665 ,  H01L2924/00

摘要： According to an embodiment, an integrated circuit package comprises a chip, a thermal component, and a molding compound. The chip comprises an active surface and a backside surface opposite the active surface. The thermal component is physically coupled to the backside surface of the chip. The molding compound encapsulates the chip, and an exposed surface of the thermal component is exposed through the molding compound. Another embodiment is a method to form an integrated circuit package.

摘要翻译： 根据实施例，集成电路封装包括芯片，热部件和模制化合物。 芯片包括有源表面和与有源表面相对的背面。 热分量物理耦合到芯片的背面。 模塑料包封芯片，并且通过模塑料露出热组分的暴露表面。 另一实施例是形成集成电路封装的方法。

公开(公告)号：US08058100B2

公开(公告)日：2011-11-15

申请号：US12788772

申请日：2010-05-27

申请人： Han-Ping Pu ,  Chien-Ping Huang ,  Cheng-Hsu Hsiao

发明人： Han-Ping Pu ,  Chien-Ping Huang ,  Cheng-Hsu Hsiao

IPC分类号： H01L21/60

CPC分类号： H01L21/561 ,  H01L21/568 ,  H01L23/3114 ,  H01L24/19 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/20 ,  H01L2224/97 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/15311 ,  H01L2924/18161 ,  H01L2924/18162 ,  H01L2924/351 ,  H01L2224/82 ,  H01L2924/00

摘要： A chip scale package structure and a method for fabricating the same are disclosed. The method includes forming metal pads on a predetermined part of a carrier; mounting chips on the carrier, each of the chips having a plurality of conductive bumps soldered to the metal pads; forming an encapsulant on the carrier to encapsulate the chips and the conductive bumps; removing the carrier to expose the metal pads and even the metal pads with a surface of the encapsulant; forming on the encapsulant a plurality of first conductive traces electrically connected to the metal pads; applying a solder mask on the first conductive traces, and forming a plurality of openings on the solder mask to expose a predetermined part of the first conductive traces; forming a plurality of conductive elements on the predetermined part; and cutting the encapsulant to form a plurality of chip scale package structures.

摘要翻译： 公开了一种芯片级封装结构及其制造方法。 该方法包括在载体的预定部分上形成金属垫; 在载体上安装芯片，每个芯片具有焊接到金属焊盘的多个导电凸块; 在载体上形成密封剂以封装芯片和导电凸块; 移除载体以暴露金属垫和甚至具有密封剂表面的金属垫; 在所述密封剂上形成电连接到所述金属焊盘的多个第一导电迹线; 在所述第一导电迹线上施加焊接掩模，以及在所述焊接掩模上形成多个开口以暴露所述第一导电迹线的预定部分; 在所述预定部分上形成多个导电元件; 以及切割所述密封剂以形成多个芯片级封装结构。

公开(公告)号：US07993967B2

公开(公告)日：2011-08-09

申请号：US12616834

申请日：2009-11-12

申请人： Yih-Jenn Jiang ,  Han-Ping Pu ,  Chien-Ping Huang ,  Cheng-Hsu Hsiao

发明人： Yih-Jenn Jiang ,  Han-Ping Pu ,  Chien-Ping Huang ,  Cheng-Hsu Hsiao

IPC分类号： H01L21/44 ,  H01L21/48 ,  H01L21/50

CPC分类号： H01L23/3121 ,  H01L21/561 ,  H01L21/6835 ,  H01L24/48 ,  H01L24/97 ,  H01L2221/68345 ,  H01L2224/16 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/97 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/15747 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/351 ,  H01L2224/85 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2224/0401 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor package and a fabrication method are disclosed. The fabrication method includes applying a sacrificial layer on one surface of a metal carrier, applying an insulation layer on the sacrificial layer, and forming through holes in the sacrificial layer and the insulation layer to expose the metal carrier; forming a conductive metallic layer in each through hole; forming a patterned circuit layer on the insulation layer to be electrically connected to the conductive metallic layer; mounting at least a chip on the insulation layer and electrically connecting the chip to the patterned circuit layer; forming an encapsulant to encapsulate the chip and the patterned circuit layer; and removing the metal carrier and the sacrificial layer to expose the insulation layer and conductive metallic layer to allow the conductive metallic layer to protrude from the insulation layer. In the present invention, the distance between the semiconductor package and the external device is increased, and thermal stress caused by difference between the thermal expansion coefficients is reduced, so as to enhance the reliability of the product.

摘要翻译： 公开了半导体封装和制造方法。 制造方法包括在金属载体的一个表面上施加牺牲层，在牺牲层上施加绝缘层，以及在牺牲层和绝缘层中形成通孔以露出金属载体; 在每个通孔中形成导电金属层; 在所述绝缘层上形成图案化电路层，以电连接到所述导电金属层; 将至少一个芯片安装在所述绝缘层上并将所述芯片电连接到所述图案化电路层; 形成密封剂以封装所述芯片和所述图案化电路层; 并且去除金属载体和牺牲层以暴露绝缘层和导电金属层，以允许导电金属层从绝缘层突出。 在本发明中，半导体封装和外部器件之间的距离增加，由于热膨胀系数之差导致的热应力降低，从而提高了产品的可靠性。

公开(公告)号：US20110070697A1

公开(公告)日：2011-03-24

申请号：US12955256

申请日：2010-11-29

申请人： Fang-Lin Tsai ,  Ho-Yi Tsai ,  Han-Ping Pu ,  Cheng-Hsu Hsiao

发明人： Fang-Lin Tsai ,  Ho-Yi Tsai ,  Han-Ping Pu ,  Cheng-Hsu Hsiao

IPC分类号： H01L21/48

CPC分类号： H01L25/105 ,  H01L23/49811 ,  H01L23/49838 ,  H01L24/73 ,  H01L25/50 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/01077 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00

摘要： A stack structure of semiconductor packages and a method for fabricating the stack structure are provided. A plurality of electrical connection pads and dummy pads are formed on a surface of a substrate of an upper semiconductor package and at positions corresponding to those around an encapsulant of a lower semiconductor package. Solder balls are implanted to the electrical connection pads and the dummy pads. The upper semiconductor package is mounted on the lower semiconductor package. The upper semiconductor package is electrically connected to the lower semiconductor package by the solder balls implanted to the electrical connection pads, and the encapsulant of the lower semiconductor package is surrounded and confined by the solder balls implanted to the dummy pads. Thereby, the upper semiconductor package is properly and securely positioned on the lower semiconductor package, without the occurrence of misalignment between the upper and lower semiconductor packages.

摘要翻译： 提供半导体封装的堆叠结构以及制造叠层结构的方法。 在上半导体封装的衬底的表面上和与下半导体封装的密封剂周围的位置相对应的位置处形成多个电连接焊盘和虚拟焊盘。 将焊球植入电连接焊盘和虚拟焊盘。 上半导体封装安装在下半导体封装上。 上半导体封装通过注入电连接焊盘的焊球电连接到下半导体封装，并且下半导体封装的密封剂被植入到虚拟焊盘中的焊球围绕并限制。 因此，上半导体封装被适当且牢固地定位在下半导体封装上，而不会发生上下半导体封装之间的未对准。

公开(公告)号：US20100151631A1

公开(公告)日：2010-06-17

申请号：US12710450

申请日：2010-02-23

申请人： Han-Ping Pu ,  Chien-Ping Huang ,  Cheng-Hsu Hsiao

发明人： Han-Ping Pu ,  Chien-Ping Huang ,  Cheng-Hsu Hsiao

IPC分类号： H01L21/60

CPC分类号： H01L23/473 ,  H01L21/563 ,  H01L23/3157 ,  H01L2224/16225 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73253

摘要： A semiconductor package with a heat dissipating device and a fabrication method of the semiconductor package are provided. A chip is mounted on a substrate. The heat dissipating device is mounted on the chip, and includes an accommodating room, and a first opening and a second opening that communicate with the accommodating room. An encapsulant is formed between the heat dissipating device and the substrate to encapsulate the chip. A cutting process is performed to remove a non-electrical part of structure and expose the first and second openings from the encapsulant. A cooling fluid is received in the accommodating room to absorb and dissipate heat produced by the chip. The heat dissipating device covers the encapsulant and the chip to provide a maximum heat transfer area for the semiconductor package.

摘要翻译： 提供了具有散热装置的半导体封装和半导体封装的制造方法。 芯片安装在基板上。 散热装置安装在芯片上，并且包括容纳室，以及与容纳室连通的第一开口和第二开口。 在散热装置和衬底之间形成密封剂以封装芯片。 执行切割处理以去除结构的非电气部分并且从密封剂暴露第一和第二开口。 冷却流体容纳在容纳室中以吸收和散发由芯片产生的热量。 散热装置覆盖密封剂和芯片，以为半导体封装提供最大的传热面积。

公开(公告)号：US07671466B2

公开(公告)日：2010-03-02

申请号：US11647832

申请日：2006-12-29

申请人： Han-Ping Pu ,  Chien-Ping Huang ,  Cheng-Hsu Hsiao

发明人： Han-Ping Pu ,  Chien-Ping Huang ,  Cheng-Hsu Hsiao

IPC分类号： H01L23/34 ,  H05K7/20 ,  H01L21/00

CPC分类号： H01L23/473 ,  H01L21/563 ,  H01L23/3157 ,  H01L2224/16225 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73253

摘要： A semiconductor package with a heat dissipating device and a fabrication method of the semiconductor package are provided. A chip is mounted on a substrate. The heat dissipating device is mounted on the chip, and includes an accommodating room, and a first opening and a second opening that communicate with the accommodating room. An encapsulant is formed between the heat dissipating device and the substrate to encapsulate the chip. A cutting process is performed to remove a non-electrical part of structure and expose the first and second openings from the encapsulant. A cooling fluid is received in the accommodating room to absorb and dissipate heat produced by the chip. The heat dissipating device covers the encapsulant and the chip to provide a maximum heat transfer area for the semiconductor package.

摘要翻译： 提供了具有散热装置的半导体封装和半导体封装的制造方法。 芯片安装在基板上。 散热装置安装在芯片上，并且包括容纳室，以及与容纳室连通的第一开口和第二开口。 在散热装置和衬底之间形成密封剂以封装芯片。 执行切割处理以去除结构的非电气部分，并使第一和第二开口与密封剂暴露。 冷却流体容纳在容纳室中以吸收和散发由芯片产生的热量。 散热装置覆盖密封剂和芯片，以为半导体封装提供最大的传热面积。

公开(公告)号：US07489044B2

公开(公告)日：2009-02-10

申请号：US11592046

申请日：2006-11-01

申请人： Han-Ping Pu ,  Cheng-Hsu Hsiao

发明人： Han-Ping Pu ,  Cheng-Hsu Hsiao

IPC分类号： H01L23/48 ,  H01L23/52

CPC分类号： H01L23/3128 ,  H01L24/48 ,  H01L24/73 ,  H01L24/97 ,  H01L25/105 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2225/1005 ,  H01L2225/1023 ,  H01L2225/1029 ,  H01L2225/1058 ,  H01L2225/1064 ,  H01L2924/00014 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2224/81 ,  H01L2224/85 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： The present invention provides a semiconductor package and a fabrication method thereof. The method includes the steps of: providing a chip carrier module having a plurality of chip carriers, disposing a plurality of electrical connecting points on the chip carriers, performing chip mounting and molding on the chip carrier module to form an encapsulant encapsulating the semiconductor chip, exposing the electrical connecting points from the encapsulant; forming a patterned circuit layer on the encapsulant, electrically connecting the patterned circuit layer to the electrical connecting points, cutting and separating the chip carriers to form a plurality of semiconductor packages each having a circuit layer formed on the encapsulant such that the circuit layer provides extra electrical connecting points and thereby enhances electrical performance of electrical products. During a package stacking process, no package is limited by the design of another package below.

摘要翻译： 本发明提供半导体封装及其制造方法。 该方法包括以下步骤：提供具有多个芯片载体的芯片载体模块，在芯片载体上布置多个电连接点，在芯片载体模块上执行芯片安装和模制以形成封装半导体芯片的密封剂， 将电连接点暴露于密封剂; 在所述密封剂上形成图案化电路层，将所述图案化电路层电连接到所述电连接点，切割和分离所述芯片载体以形成多个半导体封装，每个半导体封装具有形成在所述密封剂上的电路层，使得所述电路层提供额外的 电连接点，从而提高电气产品的电气性能。 在包装堆垛过程中，没有包装受下面另一包装的设计限制。

公开(公告)号：US20070296079A1

公开(公告)日：2007-12-27

申请号：US11818225

申请日：2007-06-12

申请人： Chien-Ping Huang ,  Han-Ping Pu ,  Ho-Yi Tsai

发明人： Chien-Ping Huang ,  Han-Ping Pu ,  Ho-Yi Tsai

IPC分类号： H01L23/34 ,  H01L21/58

CPC分类号： H01L23/4334 ,  H01L23/3121 ,  H01L24/48 ,  H01L2224/4824 ,  H01L2224/73204 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01079 ,  H01L2924/1815 ,  H01L2924/18165 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A heat sink package structure and a method for fabricating the same are disclosed. The method includes mounting and electrically connecting a semiconductor chip to a chip carrier, forming an interface layer or a second heat dissipating element having the interface layer on the semiconductor chip and installing a first heat dissipating element having a heat dissipating portion and a supporting portion onto the chip carrier. The method further includes forming openings corresponding to the semiconductor chip in the heat dissipating portion, and forming an encapsulant for covering the semiconductor chip, the interface layer or the second heat dissipating element, and the first heat dissipating element. A height is reserved on top of the interface layer for the formation of the encapsulant for covering the interface layer. The method further includes cutting the encapsulant along edges of the interface layer, and removing the redundant encapsulant on the interface layer. Therefore, the drawbacks of the prior art of the burrs caused by a cutting tool for cutting the heat dissipating element and wearing of the cutting tool are overcome.

摘要翻译： 公开了一种散热器封装结构及其制造方法。 该方法包括将半导体芯片安装并电连接到芯片载体，在半导体芯片上形成具有界面层的界面层或第二散热元件，并将具有散热部分和支撑部分的第一散热元件安装到 芯片载体。 该方法还包括形成对应于散热部分中的半导体芯片的开口，以及形成用于覆盖半导体芯片，界面层或第二散热元件的密封剂和第一散热元件。 在接口层顶部保留一个高度，用于形成覆盖界面层的密封剂。 该方法还包括沿着界面层的边缘切割密封剂，以及去除界面层上的冗余密封剂。 因此，克服了用于切割散热元件的切削工具和切削工具的磨损引起的毛刺现有技术的缺陷。

公开(公告)号：US07247934B2

公开(公告)日：2007-07-24

申请号：US11026933

申请日：2004-12-29

申请人： Han-Ping Pu

发明人： Han-Ping Pu

IPC分类号： H01L23/48 ,  H01L23/52

CPC分类号： H05K1/141 ,  H01L24/97 ,  H01L25/03 ,  H01L25/0657 ,  H01L2224/0554 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73253 ,  H01L2224/97 ,  H01L2225/06517 ,  H01L2225/06582 ,  H01L2225/06589 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/15311 ,  H05K3/284 ,  H05K3/3436 ,  H05K2201/10515 ,  H05K2201/10674 ,  H05K2201/10689 ,  H01L2224/81 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

摘要： A multi-chip semiconductor package and a fabrication method thereof are provided. At least one first chip is mounted on and electrically connected to an upper surface of a substrate via solder bumps. A preformed package structure having a second chip and a first encapsulation body is mounted on the upper surface of the substrate, wherein outer leads of the preformed package structure are exposed from the first encapsulation body and electrically connected to the upper surface of the substrate. The first encapsulation body, outer leads and substrate form a space where the first chip is received, and a gap is present between the first chip and the first encapsulation body. A second encapsulation body is formed on the upper surface of the substrate to encapsulate the first chip, solder bumps and preformed package structure. A plurality of solder balls are implanted on the lower surface of the substrate.

摘要翻译： 提供一种多芯片半导体封装及其制造方法。 至少一个第一芯片通过焊料凸块安装在基板的上表面上并电连接到基板的上表面。 具有第二芯片和第一封装体的预制封装结构安装在基板的上表面上，其中预成型封装结构的外引线从第一封装体露出并电连接到基板的上表面。 第一封装体，外引线和衬底形成接收第一芯片的空间，并且在第一芯片和第一封装体之间存在间隙。 第二封装体形成在衬底的上表面上，以封装第一芯片，焊料凸块和预成型封装结构。 在基板的下表面上注入多个焊球。

公开(公告)号：US20060160348A1

公开(公告)日：2006-07-20

申请号：US11100140

申请日：2005-04-05

申请人： Han-Ping Pu ,  Chun-Chi Ke ,  Kuo-Jui Tai ,  Cheng-Hsu Hsiao

发明人： Han-Ping Pu ,  Chun-Chi Ke ,  Kuo-Jui Tai ,  Cheng-Hsu Hsiao

IPC分类号： H01L21/44

CPC分类号： H01L24/13 ,  H01L24/11 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05027 ,  H01L2224/0508 ,  H01L2224/05124 ,  H01L2224/05155 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2924/0001 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/00014 ,  H01L2924/013

摘要： A semiconductor element with under bump metallurgy (UBM) structures and a fabrication method thereof are proposed. When UBM structures are formed on signal pads and ground pads on a surface of the semiconductor element that is completely fabricated with a circuit layout, a metallic layer for defining the UBM structures is retained, wherein the UBM structures on the ground pads are electrically connected to the metallic layer, and the UBM structures on the signal pads are electrically insulated from the metallic layer. This allows the metallic layer for defining the UBM structures to directly serve as a grounding layer for the semiconductor element.

摘要翻译： 提出了具有凸块下冶金（UBM）结构的半导体元件及其制造方法。 当在完全由电路布局制造的半导体元件的表面上的信号焊盘和接地焊盘上形成UBM结构时，保留用于限定UBM结构的金属层，其中接地焊盘上的UBM结构电连接到 金属层和信号焊盘上的UBM结构与金属层电绝缘。 这允许用于限定UBM结构的金属层直接用作半导体元件的接地层。