公开(公告)号：US09275898B1

公开(公告)日：2016-03-01

申请号：US14637442

申请日：2015-03-04

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jiehui Shu ,  Zhiguo Sun ,  Yang Bum Lee ,  Huang Liu

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L23/53228 ,  C23C16/04 ,  C23C16/16 ,  C23C16/45523 ,  H01L21/28562 ,  H01L21/76826 ,  H01L21/76849 ,  H01L21/76862 ,  H01L21/76883 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods of forming a Co cap on a Cu interconnect in or through an ULK ILD with improved selectivity while protecting an ULK ILD surface are provided. Embodiments include providing a Cu filled via in an ULK ILD; depositing a Co precursor and H2 over the Cu-filled via and the ULK ILD, the Co precursor and H2 forming a Co cap over the Cu-filled via; depositing an UV cured methyl over the Co cap and the ULK ILD; performing an NH3 plasma treatment after depositing the UV cured methyl; and repeating the steps of depositing a Co precursor through performing an NH3 plasma treatment to remove impurities from the Co cap.

Abstract translation: 提供了在保护ULK ILD表面的情况下，通过ULK ILD或通过ULK ILD在Cu互连上形成Co帽的方法，其具有改进的选择性。 实施例包括在ULK ILD中提供Cu填充的通孔; 在Cu填充的通孔和ULK ILD上沉积Co前体和H 2，Co前体和H 2在Cu填充的通孔上形成Co盖; 在Co盖和ULK ILD上沉积UV固化的甲基; 沉积UV固化甲基后进行NH3等离子体处理; 并且重复以下步骤：通过进行NH 3等离子体处理来沉积Co前体以从Co盖去除杂质。

公开(公告)号：US09184288B2

公开(公告)日：2015-11-10

申请号：US14207822

申请日：2014-03-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Sipeng Gu ,  Zhiguo Sun ,  Sandeep Gaan ,  Danni Chen ,  Wen-Pin Peng ,  Huang Liu

IPC: H01L21/8238 ,  H01L29/78 ,  H01L29/40 ,  H01L21/02

CPC classification number: H01L29/7843 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02205 ,  H01L21/02211 ,  H01L21/02271 ,  H01L21/02274 ,  H01L21/02304 ,  H01L21/76801 ,  H01L21/76829 ,  H01L29/401 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545

Abstract: Semiconductor structures and fabrication methods are provided having a bridging film which facilitates adherence of both an underlying layer of dielectric material and an overlying stress-inducing layer. The method includes, for instance, providing a layer of dielectric material, with at least one gate structure disposed therein, over a semiconductor substrate; providing a bridging film over the layer of dielectric material with the at least one gate structure; and providing a stress-inducing layer over the bridging film. The bridging film is selected to facilitate adherence of both the underlying layer of dielectric material and the overlying stress-inducing layer by, in part, forming a chemical bond with the layer of dielectric material, without forming a chemical bond with the stress-inducing layer.

Abstract translation: 提供半导体结构和制造方法，其具有桥接膜，其有助于介电材料的下层和上覆的应力诱导层的粘附。 该方法包括例如在半导体衬底上提供其中设置有至少一个栅极结构的电介质材料层; 在所述介​​电材料层上提供具有所述至少一个栅极结构的桥接膜; 并在桥接膜上提供应力诱导层。 选择桥接膜以便于通过部分地与电介质材料层形成化学键而使介电材料的下层和上覆的应力诱导层两者粘附，而不与应力诱导层形成化学键 。

公开(公告)号：US09123771B2

公开(公告)日：2015-09-01

申请号：US13765723

申请日：2013-02-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hongliang Shen ,  Kyutae Na ,  Sandeep Gaan ,  Hsin-Neng Tai ,  Weihua Tong ,  Sang Cheol Han ,  Tae Hoon Kim ,  Ja Hyung Han ,  Haigou Huang ,  Changyong Xiao ,  Huang Liu ,  Seung Yeon Kim

IPC: H01L21/762 ,  H01L21/02

CPC classification number: H01L29/0649 ,  H01L21/02123 ,  H01L21/76224 ,  H01L21/76229 ,  H01L27/0886

Abstract: Aspects of the present invention generally relate to approaches for forming a semiconductor device such as a TSV device having a “buffer zone” or gap layer between the TSV and transistor(s). The gap layer is typically filled with a low stress thin film fill material that controls stresses and crack formation on the devices. Further, the gap layer ensures a certain spatial distance between TSVs and transistors to reduce the adverse effects of temperature excursion.

Abstract translation: 本发明的方面通常涉及用于形成半导体器件的方法，例如在TSV和晶体管之间具有“缓冲区”或间隙层的TSV器件。 间隙层通常填充有低应力薄膜填充材料，其控制器件上的应力和裂纹形成。 此外，间隙层确保TSV和晶体管之间的一定空间距离，以减少温度偏移的不利影响。

公开(公告)号：US09093561B2

公开(公告)日：2015-07-28

申请号：US14085906

申请日：2013-11-21

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hong Yu ,  Huang Liu ,  Lun Zhao ,  Richard J. Carter

IPC: H01L21/8238 ,  H01L21/768 ,  H01L21/308 ,  H01L21/84

CPC classification number: H01L21/823857 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/3081 ,  H01L21/3086 ,  H01L21/3105 ,  H01L21/31155 ,  H01L21/76829 ,  H01L21/823821 ,  H01L21/823864 ,  H01L21/845 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7848

Abstract: Circuit fabrication methods are provided which include, for example: providing the circuit structure with at least one gate structure extending over a first region and a second region of a substrate structure, the at least one gate structure including a capping layer; and modifying an etch property of at least a portion of the capping layer of the at least one gate structure, where the modified etch property inhibits etching of the at least one gate structure during a first etch process facilitating fabrication of at least one first transistor in the first region and inhibits etching of the at least one gate structure during a second etch process facilitating fabrication of at least one second transistor in the second region.

Abstract translation: 提供了电路制造方法，其包括例如：为电路结构提供在衬底结构的第一区域和第二区域上延伸的至少一个栅极结构，所述至少一个栅极结构包括封盖层; 以及修改所述至少一个栅极结构的覆盖层的至少一部分的蚀刻特性，其中所述修改的蚀刻性能在第一蚀刻工艺期间禁止蚀刻所述至少一个栅极结构，促进制造至少一个第一晶体管 所述第一区域并且在第二蚀刻工艺期间抑制所述至少一个栅极结构的蚀刻，促进在所述第二区域中制造至少一个第二晶体管。

公开(公告)号：US20150099340A1

公开(公告)日：2015-04-09

申请号：US14049848

申请日：2013-10-09

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hong Yu ,  Hyucksoo Yang ,  Huang Liu ,  Richard J. Carter

IPC: H01L29/66

CPC classification number: H01L29/7848 ,  H01L21/823814 ,  H01L21/823821 ,  H01L29/161 ,  H01L29/165 ,  H01L29/24 ,  H01L29/267 ,  H01L29/6653 ,  H01L29/66636 ,  H01L29/66795 ,  H01L21/8238 ,  H01L29/785

Abstract: Embodiments of the present invention provide improved methods for fabricating field effect transistors such as finFETs. Stressor regions are used to increase carrier mobility. However, subsequent processes such as deposition of flowable oxide and annealing can damage the stressor regions, diminishing the amount of stress that is induced. Embodiments of the present invention provide a protective layer of silicon or silicon oxide over the stressor regions prior to the flowable oxide deposition and anneal.

Abstract translation: 本发明的实施例提供了用于制造诸如finFET的场效应晶体管的改进方法。 应力区域用于增加载流子迁移率。 然而，诸如沉积可流动氧化物和退火的后续过程可能损害应力区域，减少了所引起的应力量。 本发明的实施例在可流动的氧化物沉积和退火之前在应力区域上提供硅或氧化硅的保护层。

公开(公告)号：US08993446B2

公开(公告)日：2015-03-31

申请号：US13868412

申请日：2013-04-23

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hung-Wei Liu ,  Tsung-Liang Chen ,  Huang Liu ,  Zhiguo Sun

IPC: H01L21/311 ,  H01L21/02

CPC classification number: H01L21/02112 ,  H01L21/02129 ,  H01L21/02131 ,  H01L21/02164 ,  H01L21/02271 ,  H01L21/0228 ,  H01L21/02337 ,  H01L21/76837

Abstract: A method for flowable oxide deposition is provided. An oxygen source gas is increased as a function of time or film depth to change the flowable oxide properties such that the deposited film is optimized for gap fill near a substrate surface where high aspect ratio shapes are present. The oxygen gas flow rate increases as the film depth increases, such that the deposited film is optimized for planarization quality at the upper regions of the deposited film.

Abstract translation: 提供了一种可流动氧化物沉积的方法。 作为时间或膜深度的函数，氧源气体增加以改变可流动的氧化物性质，使得沉积膜针对存在高纵横比形状的衬底表面附近的间隙填充进行了优化。 氧气流速随着膜深度的增加而增加，使得沉积膜对沉积膜的上部区域的平坦化质量进行了优化。

公开(公告)号：US20150076624A1

公开(公告)日：2015-03-19

申请号：US14031839

申请日：2013-09-19

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Huang Liu ,  Jialin Yu ,  Jilin Xia

IPC: H01L21/28 ,  H01L29/49 ,  H01L21/3213 ,  H01L21/285 ,  H01L21/321

CPC classification number: H01L21/32115 ,  H01L21/28088 ,  H01L21/28194 ,  H01L21/32136 ,  H01L21/823437 ,  H01L21/82345 ,  H01L21/823828 ,  H01L21/823842 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/78

Abstract: Integrated circuits with smooth metal gates and methods for fabricating integrated circuits with smooth metal gates are provided. In an embodiment, a method for fabricating an integrated circuit includes providing a partially fabricated integrated circuit including a dielectric layer formed with a trench bound by a trench surface. The method deposits metal in the trench and forms an overburden portion of metal overlying the dielectric layer. The method includes selectively etching the metal with a chemical etchant and removing the overburden portion of metal.

Abstract translation: 提供了具有平滑金属栅极的集成电路和用于制造具有光滑金属栅极的集成电路的方法。 在一个实施例中，一种用于制造集成电路的方法包括提供部分制造的集成电路，其包括由沟槽表面限定的沟槽形成的电介质层。 该方法将金属沉积在沟槽中并形成覆盖在介电层上的金属覆盖层部分。 该方法包括用化学蚀刻剂选择性地蚀刻金属并去除金属的覆盖层部分。

公开(公告)号：US20170338226A1

公开(公告)日：2017-11-23

申请号：US15628984

申请日：2017-06-21

Applicant: GLOBALFOUNDRIES INC.

Inventor： Haigou Huang ,  Jinping Liu ,  Huang Liu ,  Taifong Chao

IPC: H01L27/088 ,  H01L21/3105 ,  H01L21/3115 ,  H01L21/8234

CPC classification number: H01L27/0886 ,  H01L21/28518 ,  H01L21/31053 ,  H01L21/31155 ,  H01L21/823431 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/66803 ,  H01L29/7856

Abstract: Various embodiments include methods and integrated circuit structures. In some cases, an integrated circuit (IC) structure includes: a substrate; a set of fin structures overlying the substrate, the set of fin structures including a substrate base and a silicide layer over the substrate base; an oxide layer located between adjacent fins in the set of fin structures; and a nitride layer over the set of fin structures, wherein a height of the nitride layer is substantially uniform across the set of fin structures.

公开(公告)号：US09793169B1

公开(公告)日：2017-10-17

申请号：US15175187

申请日：2016-06-07

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Huy Cao ,  Huang Liu ,  Guillaume Bouche ,  Songkram Srivathanakul

IPC: H01L21/02 ,  H01L21/8234 ,  H01L21/308 ,  H01L21/311 ,  H01L21/3115

CPC classification number: H01L21/823431 ,  H01L21/02126 ,  H01L21/0214 ,  H01L21/02211 ,  H01L21/02216 ,  H01L21/3081 ,  H01L21/3086 ,  H01L21/31133 ,  H01L21/31138 ,  H01L21/31144 ,  H01L21/3115 ,  H01L29/66795

Abstract: One method disclosed herein includes, among other things, forming a process layer on a substrate, forming a carbon-containing silicon dioxide layer above the process layer and forming a patterned mask layer above the carbon-containing silicon dioxide layer. The patterned mask layer exposes portions of the carbon-containing silicon dioxide layer. A material modification process is performed on the exposed portions of the carbon-containing silicon dioxide layer to generate modified portions, and the modified portions are removed. The process layer is etched using remaining portions of the carbon-containing silicon dioxide layer as an etch mask.

公开(公告)号：US20170162430A1

公开(公告)日：2017-06-08

申请号：US14958224

申请日：2015-12-03

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Xintuo Dai ,  Huang Liu ,  Chang Ho Maeng

IPC: H01L21/764 ,  H01L23/31 ,  H01L23/528 ,  H01L21/768 ,  H01L23/535

CPC classification number: H01L23/3107 ,  H01L21/76802 ,  H01L21/76811 ,  H01L21/76816 ,  H01L21/7682 ,  H01L21/76829 ,  H01L21/76877 ,  H01L21/76885 ,  H01L23/5222 ,  H01L23/528 ,  H01L23/53295 ,  H01L23/535

Abstract: Methods for producing integrated circuits and integrated circuits produced by such methods are provided. In an exemplary embodiment, a method for producing an integrated circuit includes forming a base dielectric layer overlying a substrate. A sacrificial layer is formed overlying the base dielectric layer, and adjacent conductive components are formed in the sacrificial layer where the adjacent conductive components are physically separated by material of the sacrificial layer. The sacrificial layer is removed such that an air gap is defined between the adjacent conductive components, where the air gap overlies the base dielectric layer. A cap dielectric layer is formed overlying the base dielectric layer and the air gap to enclose the air gap within the integrated circuit.