公开(公告)号：US20190296214A1

公开(公告)日：2019-09-26

申请号：US16301498

申请日：2016-06-13

Applicant: INTEL CORPORATION

Inventor： Zachary R. YOSCOVITS ,  David J. MICHALAK ,  Jeanette M. ROBERTS ,  Ravi PILLARISETTY ,  James S. CLARKE

IPC: H01L39/24 ,  H01L27/18 ,  H01L39/02 ,  H01L39/22

Abstract: Described herein are structures that include Josephson Junctions (JJs) to be used in superconducting qubits of quantum circuits disposed on a substrate. The JJs of these structures are fabricated using an approach that can be efficiently used in large scale manufacturing, providing a substantial improvement with respect to conventional approaches which include fabrications steps which are not manufacturable. In one aspect of the present disclosure, the proposed approach includes providing a patterned superconductor layer over a substrate, providing a layer of surrounding dielectric over the patterned superconductor layer, and providing a via opening in the layer of surrounding dielectric over a first portion of the patterned superconductor layer. The proposed approach further includes depositing in the via opening a first superconductor, a barrier dielectric, and a second superconductor to form, respectively, a base electrode, a tunnel barrier layer, and a top electrode of the JJ.

公开(公告)号：US20180315659A1

公开(公告)日：2018-11-01

申请号：US15528031

申请日：2014-12-17

Applicant: Intel Corporation

Inventor： Sansaptak DASGUPTA ,  Han Wui THEN ,  Marko RADOSAVLJEVIC ,  Sanaz K. GARDNER ,  Seung Hoon SUNG ,  Robert S. CHAU ,  Ravi PILLARISETTY

IPC: H01L21/8252 ,  H01L33/00 ,  H01L33/08 ,  H01L33/12 ,  H01L33/24 ,  H01L33/32

CPC classification number: H01L21/8252 ,  H01L21/02458 ,  H01L21/0254 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/02647 ,  H01L33/007 ,  H01L33/08 ,  H01L33/10 ,  H01L33/12 ,  H01L33/24 ,  H01L33/32 ,  H01L2224/16225 ,  H01L2924/15311

Abstract: Embodiments of the present disclosure are directed toward an integrated circuit (IC) die. In embodiments, an IC die may include a semiconductor substrate and a buffer layer disposed over the semiconductor substrate. The buffer layer may have a plurality of openings formed therein. In embodiments, the IC die may further include a plurality of group III-Nitride structures. Individual group III-Nitride structures of the plurality of group III-Nitride structures may include a lower portion disposed in a respective opening of the plurality of openings and an upper portion disposed over the respective opening. In embodiments, the upper portion may include a base extending radially from sidewalls of the respective opening over a surface of the buffer layer to form a perimeter around the respective opening. Other embodiments may be described and/or claimed.

公开(公告)号：US20180261669A1

公开(公告)日：2018-09-13

申请号：US15892182

申请日：2018-02-08

Applicant: Intel Corporation

Inventor： Van H. LE ,  Benjamin CHU-KUNG ,  Harold Hal W. KENNEL ,  Willy RACHMADY ,  Ravi PILLARISETTY ,  Jack T. KAVALIEROS

IPC: H01L29/06 ,  H01L29/78 ,  H01L29/66 ,  H01L29/165 ,  H01L21/02 ,  H01L29/10 ,  H01L29/08 ,  H01L29/15

CPC classification number: H01L29/0673 ,  H01L21/02532 ,  H01L21/283 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/1054 ,  H01L29/155 ,  H01L29/161 ,  H01L29/165 ,  H01L29/42392 ,  H01L29/66431 ,  H01L29/66477 ,  H01L29/66651 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/7842 ,  H01L29/7849 ,  H01L29/785 ,  H01L29/7851 ,  H01L29/78681 ,  H01L29/78687 ,  H01L29/78696

Abstract: Transistor structures having channel regions comprising alternating layers of compressively and tensilely strained epitaxial materials are provided. The alternating epitaxial layers can form channel regions in single and mitigate transistor structures. In alternate embodiments, one of the two alternating layers is selectively etched away to form nanoribbons or nanowires of the remaining material. The resulting strained nanoribbons or nanowires form the channel regions of transistor structures. Also provided are computing devices comprising transistors comprising channel regions comprised of alternating compressively and tensilely strained epitaxial layers and computing devices comprising transistors comprising channel regions comprised of strained nanoribbons or nanowires.

公开(公告)号：US20170288019A1

公开(公告)日：2017-10-05

申请号：US15626018

申请日：2017-06-16

Applicant: Intel Corporation

Inventor： Willy RACHMADY ,  Van H. LE ,  Ravi PILLARISETTY ,  Jessica S. KACHIAN ,  Marc C. FRENCH ,  Aaron A. BUDREVICH

IPC: H01L29/06

CPC classification number: H01L29/0673 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/02584 ,  H01L21/30604 ,  H01L21/30608 ,  H01L21/3065 ,  H01L29/1054 ,  H01L29/161 ,  H01L29/165 ,  H01L29/167 ,  H01L29/365 ,  H01L29/42392 ,  H01L29/511 ,  H01L29/66439 ,  H01L29/66477 ,  H01L29/66628 ,  H01L29/66742 ,  H01L29/775 ,  H01L29/7781 ,  H01L29/78 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/786 ,  H01L29/78696 ,  Y02E10/50

Abstract: Semiconductor device stacks and devices made there from having Ge-rich device layers. A Ge-rich device layer is disposed above a substrate, with a p-type doped Ge etch suppression layer (e.g., p-type SiGe) disposed there between to suppress etch of the Ge-rich device layer during removal of a sacrificial semiconductor layer richer in Si than the device layer. Rates of dissolution of Ge in wet etchants, such as aqueous hydroxide chemistries, may be dramatically decreased with the introduction of a buried p-type doped semiconductor layer into a semiconductor film stack, improving selectivity of etchant to the Ge-rich device layers.

公开(公告)号：US20170012126A1

公开(公告)日：2017-01-12

申请号：US15119674

申请日：2014-03-28

Applicant: INTEL CORPORATION

Inventor： Benjamin CHU-KUNG ,  Gilbert DEWEY ,  Van H. LE ,  Jack T. KAVALIEROS ,  Marko RADOSAVLJEVIC ,  Ravi PILLARISETTY ,  Han Wui THEN ,  Niloy MUKHERJEE ,  Sansaptak DASGUPTA

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/66 ,  H01L29/423 ,  H01L29/786

Abstract: Vertical semiconductor devices having selectively regrown top contacts and method of fabricating vertical semiconductor devices having selectively regrown top contacts are described. For example, a semiconductor device includes a substrate having a surface. A first source/drain region is disposed on the surface of the substrate. A vertical channel region is disposed on the first source/drain region and has a first width parallel with the surface of the substrate. A second source/drain region is disposed on the vertical channel region and has a second width parallel with and substantially greater than the first width. A gate stack is disposed on and completely surrounds a portion of the vertical channel region.

Abstract translation: 描述了具有选择性再生长顶端触点的垂直半导体器件和制造具有选择性再生长顶端触点的垂直半导体器件的方法。 例如，半导体器件包括具有表面的衬底。 第一源极/漏极区域设置在衬底的表面上。 垂直沟道区域设置在第一源极/漏极区域上并且具有与衬底的表面平行的第一宽度。 第二源极/漏极区域设置在垂直沟道区域上并且具有与第一宽度平行并且基本上大于第一宽度的第二宽度。 栅堆叠设置在垂直沟道区的一部分上并完全环绕。

公开(公告)号：US20170011912A1

公开(公告)日：2017-01-12

申请号：US15119683

申请日：2014-03-18

Applicant: INTEL CORPORATION

Inventor： Niloy MUKHERJEE ,  Brian S. DOYLE ,  Marko RADOSAVLJEVIC ,  Ravi PILLARISETTY ,  Han Wui THEN ,  Valluri R. RAO ,  Robert S. CHAU

IPC: H01L21/02 ,  H01L29/786 ,  H01L27/12

CPC classification number: H01L21/02513 ,  H01L21/02164 ,  H01L21/02178 ,  H01L21/02186 ,  H01L21/0228 ,  H01L21/02282 ,  H01L21/02422 ,  H01L21/02428 ,  H01L21/02488 ,  H01L21/02521 ,  H01L21/02532 ,  H01L21/02538 ,  H01L21/02549 ,  H01L21/02551 ,  H01L21/02595 ,  H01L21/02631 ,  H01L21/02675 ,  H01L21/763 ,  H01L27/1218 ,  H01L27/1225 ,  H01L29/78603 ,  H01L29/78681

Abstract: Embodiments of semiconductor assemblies, and related integrated circuit devices and techniques, are disclosed herein. In some embodiments, a semiconductor assembly may include a flexible substrate, a polycrystalline semiconductor material, and a polycrystalline dielectric disposed between and adjacent to the flexible substrate and the polycrystalline semiconductor material. The polycrystalline semiconductor material. The polycrystalline semiconductor material may include a polycrystalline III-V material, a polycrystalline II-VI material or polycrystalline germanium. Other embodiments may be disclosed and/or claimed.

Abstract translation: 本文公开了半导体组件的实施例以及相关的集成电路器件和技术。 在一些实施例中，半导体组件可以包括柔性衬底，多晶半导体材料和布置在柔性衬底和多晶半导体材料之间和之后的多晶电介质。 多晶半导体材料。 多晶半导体材料可以包括多晶III-V材料，多晶II-VI材料或多晶锗。 可以公开和/或要求保护其他实施例。

公开(公告)号：US20160240671A1

公开(公告)日：2016-08-18

申请号：US14914847

申请日：2013-09-27

Applicant: INTEL CORPORATION

Inventor： Willy RACHMADY ,  Van H. LE ,  Ravi PILLARISETTY ,  Marko RADOSAVLJEVIC ,  Gilbert DEWEY ,  Niloy MUKHERJEE ,  Jack T. KAVALIEROS ,  Robert S. CHAU ,  Benjamin CHU-KUNG ,  Roza KOTLYAR

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/16 ,  H01L29/66 ,  H01L29/20

CPC classification number: H01L29/7842 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/068 ,  H01L29/1054 ,  H01L29/16 ,  H01L29/165 ,  H01L29/20 ,  H01L29/42392 ,  H01L29/512 ,  H01L29/66439 ,  H01L29/66568 ,  H01L29/775 ,  H01L29/778 ,  H01L29/78696

Abstract: An apparatus including a heterostructure disposed on a substrate and defining a channel region, the heterostructure including a first material having a first band gap less than a band gap of a material of the substrate and a second material having a second band gap that is greater than the first band gap; and a gate stack on the channel region, wherein the second material is disposed between the first material and the gate stack. A method including forming a first material having a first band gap on a substrate; forming a second material having a second band gap greater than the first band gap on the first material; and forming a gate stack on the second material.

Abstract translation: 一种包括设置在衬底上并限定沟道区的异质结构的装置，所述异质结构包括具有小于所述衬底的材料的带隙的第一带隙的第一材料和具有大于所述衬底的材料的第二带隙的第二材料 第一个带隙; 以及栅极堆叠，其中所述第二材料设置在所述第一材料和所述栅极叠层之间。 一种方法，包括在基板上形成具有第一带隙的第一材料; 形成具有大于所述第一材料上的所述第一带隙的第二带隙的第二材料; 以及在所述第二材料上形成栅叠层。

公开(公告)号：US20160172477A1

公开(公告)日：2016-06-16

申请号：US14909090

申请日：2013-09-27

Applicant: INTEL CORPORATION

Inventor： Gilbert DEWEY ,  Matthew V. METZ ,  Niloy MUKHERJEE ,  Robert S. CHAU ,  Marko RADOSAVLJEVIC ,  Ravi PILLARISETTY ,  Benjamin CHU-KUNG

IPC: H01L29/778 ,  H01L29/78 ,  H01L29/66 ,  H01L29/205

CPC classification number: H01L29/7786 ,  H01L29/1054 ,  H01L29/205 ,  H01L29/66462 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851

Abstract: An apparatus including a heterostructure disposed on a substrate and defining a channel region, the heterostructure including a first material having a first band gap less than a band gap of a material of the substrate and a second material having a second band gap that is greater than the first band gap; and a gate stack on the channel region, wherein the second material is disposed between the first material and the gate stack. A method including forming a first material having a first band gap on a substrate; forming a second material having a second band gap greater than the first band gap on the first material; and forming a gate stack on the second material.

Abstract translation: 一种包括设置在衬底上并限定沟道区的异质结构的装置，所述异质结构包括具有小于所述衬底的材料的带隙的第一带隙的第一材料和具有大于所述衬底的材料的第二带隙的第二材料 第一个带隙; 以及栅极堆叠，其中所述第二材料设置在所述第一材料和所述栅极叠层之间。 一种方法，包括在基板上形成具有第一带隙的第一材料; 形成具有大于所述第一材料上的所述第一带隙的第二带隙的第二材料; 以及在所述第二材料上形成栅叠层。

公开(公告)号：US20220130443A1

公开(公告)日：2022-04-28

申请号：US17570249

申请日：2022-01-06

Applicant: Intel Corporation

Inventor： Abhishek A. SHARMA ,  Brian S. DOYLE ,  Ravi PILLARISETTY ,  Prashant MAJHI ,  Elijah V. KARPOV

IPC: G11C11/22 ,  H01L27/11585

Abstract: A 1S-1T ferroelectric memory cell is provided that include a transistor and a two-terminal selector device. The transistor exhibits a low conductive state and a high conductive state (channel resistance), depending on drive voltage. The two-terminal selector device exhibits one of an ON-state and an OFF-state depending upon whether the transistor is in its low conductive state or its high conductive state. The transistor may be, for instance, a ferroelectric gate vertical transistor. Modulation of a polarization state of ferroelectric material of the vertical transistor may be utilized to switch the state of the selector device. The memory cell may thus selectively be operated in one of an ON-state and an OFF-state depending upon whether the selector device is in its ON-state or OFF-state.

公开(公告)号：US20210091080A1

公开(公告)日：2021-03-25

申请号：US16772636

申请日：2018-03-28

Applicant: Intel Corporation

Inventor： Gilbert DEWEY ,  Ravi PILLARISETTY ,  Abhishek A. SHARMA ,  Aaron D. LILAK ,  Willy RACHMADY ,  Rishabh MEHANDRU ,  Kimin JUN ,  Anh PHAN ,  Hui Jae YOO ,  Patrick MORROW ,  Cheng-Ying HUANG

IPC: H01L27/092 ,  H01L27/12 ,  H01L21/8254

Abstract: An integrated circuit structure comprises a lower device layer that includes a first structure comprising a plurality of PMOS transistors. An upper device layer is formed on the lower device layer, wherein the upper device layer includes a second structure comprising a plurality of NMOS thin-film transistors (TFT).