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公开(公告)号:US06563212B2
公开(公告)日:2003-05-13
申请号:US10046204
申请日:2002-01-16
申请人: Masanori Shibamoto , Masahiro Ichitani , Ryo Haruta , Katsuyuki Matsumoto , Junichi Arita , Ichiro Anjo
发明人: Masanori Shibamoto , Masahiro Ichitani , Ryo Haruta , Katsuyuki Matsumoto , Junichi Arita , Ichiro Anjo
IPC分类号: H01L2334
CPC分类号: H01L24/50 , H01L23/13 , H01L23/16 , H01L23/24 , H01L23/293 , H01L23/3128 , H01L23/34 , H01L23/36 , H01L23/3672 , H01L23/3675 , H01L23/3732 , H01L23/3735 , H01L23/3736 , H01L23/3737 , H01L23/49572 , H01L23/49816 , H01L23/4985 , H01L24/48 , H01L24/73 , H01L2224/16 , H01L2224/16225 , H01L2224/16227 , H01L2224/29144 , H01L2224/32225 , H01L2224/32245 , H01L2224/48091 , H01L2224/48227 , H01L2224/73253 , H01L2224/73265 , H01L2224/73269 , H01L2224/92247 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01058 , H01L2924/01074 , H01L2924/01079 , H01L2924/01082 , H01L2924/0132 , H01L2924/01322 , H01L2924/15153 , H01L2924/1517 , H01L2924/15311 , H01L2924/15312 , H01L2924/1532 , H01L2924/16195 , H01L2924/181 , H01L2924/30107 , H01L2924/351 , H01L2924/0105 , H01L2924/00012 , H01L2924/00 , H01L2924/01014 , H01L2224/45099
摘要: A semiconductor device in which a semiconductor chip 1 is bonded by a metal bond 2 to one surface of a heat sink 4 formed of a material with a thermal expansion coefficient is close to he semiconductor chip 1, the heat sink 4 is glued to a stiffener with a silicon adhesive 5 with an elastic modulus of 10 MPa or less, a TAB tape 9 is glued to the stiffener 3 with an epoxy adhesive 6, and the semiconductor chip 1 is sealed with an epoxy sealing resin 8 with an elastic modulus of 10 GPa or more for protection from outside.
摘要翻译: 其中半导体芯片1通过金属接合2接合到由具有热膨胀系数的材料形成的散热器4的一个表面接近半导体芯片1的半导体器件,散热器4被胶合到加强件 使用弹性模量为10MPa以下的硅粘合剂5,用环氧树脂粘合剂6将TAB带9胶合到加强件3,并用环氧树脂密封树脂8密封弹性模量为10的半导体芯片1 GPa或更多用于保护外部。
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公开(公告)号:US20060239055A1
公开(公告)日:2006-10-26
申请号:US11378368
申请日:2006-03-20
申请人: Yuji Sonoda , Shuji Kikuchi , Katsunori Hirano , Ichiro Anjo , Mitsuaki Katagiri
发明人: Yuji Sonoda , Shuji Kikuchi , Katsunori Hirano , Ichiro Anjo , Mitsuaki Katagiri
IPC分类号: G11C5/02
CPC分类号: G11C29/48 , G11C5/04 , G11C2029/2602 , G11C2029/5602
摘要: The present invention relates to a DRAM stacked packages, a DIMM, a method for testing them, and a semiconductor manufacturing method. According to the present invention, there is provided a DRAM stacked package comprising: a plurality of stacked DRAMs; external terminals to which test equipment is connected, said external terminals being used to input/output at least address, command, and data; and an interface chip provided between said plurality of stacked DRAMs and said external terminals. The plurality of DRAMs and the interface chip are implemented on a package. The interface chip comprises: a test circuit including: an algorithmic pattern generator for generating a test pattern used to test the plurality of DRAMs; applying circuits for applying said generated test pattern to the plurality of DRAMs; and a comparator for comparing each response signal received from the plurality of DRAMs with an expected value for judgment.
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公开(公告)号:US06404049B1
公开(公告)日:2002-06-11
申请号:US09077190
申请日:1998-05-26
申请人: Masanori Shibamoto , Masahiro Ichitani , Ryo Haruta , Katsuyuki Matsumoto , Junichi Arita , Ichiro Anjo
发明人: Masanori Shibamoto , Masahiro Ichitani , Ryo Haruta , Katsuyuki Matsumoto , Junichi Arita , Ichiro Anjo
IPC分类号: H01L2334
CPC分类号: H01L24/50 , H01L23/13 , H01L23/16 , H01L23/24 , H01L23/293 , H01L23/3128 , H01L23/34 , H01L23/36 , H01L23/3672 , H01L23/3675 , H01L23/3732 , H01L23/3735 , H01L23/3736 , H01L23/3737 , H01L23/49572 , H01L23/49816 , H01L23/4985 , H01L24/48 , H01L24/73 , H01L2224/16 , H01L2224/16225 , H01L2224/16227 , H01L2224/29144 , H01L2224/32225 , H01L2224/32245 , H01L2224/48091 , H01L2224/48227 , H01L2224/73253 , H01L2224/73265 , H01L2224/73269 , H01L2224/92247 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01058 , H01L2924/01074 , H01L2924/01079 , H01L2924/01082 , H01L2924/0132 , H01L2924/01322 , H01L2924/15153 , H01L2924/1517 , H01L2924/15311 , H01L2924/15312 , H01L2924/1532 , H01L2924/16195 , H01L2924/181 , H01L2924/30107 , H01L2924/351 , H01L2924/0105 , H01L2924/00012 , H01L2924/00 , H01L2924/01014 , H01L2224/45099
摘要: A semiconductor device in which a semiconductor chip 1 is bonded by a metal bond 2 to one surface of a heat sink 4 formed of a material with a thermal expansion coefficient is close to the semiconductor chip 1, the heat sink 4 is glued to a stiffener with a silicon adhesive 5 with an elastic modulus of 10 MPa or less, a TAB tape 9 is glued to the stiffener 3 with an epoxy adhesive 6, and the semiconductor chip 1 is sealed with an epoxy sealing resin 8 with an elastic modulus of 10 GPa or more for protection from outside.
摘要翻译: 其中半导体芯片1通过金属粘合剂2结合到由具有热膨胀系数的材料形成的散热器4的一个表面接近半导体芯片1,散热器4被粘合到加强件 使用弹性模量为10MPa以下的硅粘合剂5,用环氧树脂粘合剂6将TAB带9胶合到加强件3,并用环氧树脂密封树脂8密封弹性模量为10的半导体芯片1 GPa或更多用于保护外部。
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公开(公告)号:US4974054A
公开(公告)日:1990-11-27
申请号:US313438
申请日:1989-02-22
申请人: Ichiro Anjo
发明人: Ichiro Anjo
IPC分类号: H01L21/60 , H01L21/607
CPC分类号: H01L24/85 , H01L24/05 , H01L24/48 , H01L24/78 , H01L2224/04042 , H01L2224/05556 , H01L2224/05624 , H01L2224/45144 , H01L2224/4807 , H01L2224/48091 , H01L2224/48247 , H01L2224/48451 , H01L2224/48453 , H01L2224/48465 , H01L2224/48624 , H01L2224/78302 , H01L2224/85043 , H01L2224/85203 , H01L2224/85205 , H01L24/45 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01033 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/181 , H01L2924/351 , Y10S228/904 , Y10T29/49121
摘要: The trend toward higher integration degrees has caused the semiconductor pellets to have large sizes. In the resin molded semiconductor devices, in particular, cracks develop on the pellet due to contraction upon cooling that stems from the difference of coefficient of thermal expansion between the molding resin and the pellet. Cracks develop conspicuously under the ball of the wire that is bonded onto the bonding pad on the pellet. The area that receives the shearing stress increases with the increase in the ball portion, and the cracks develop easily.To decrease the shearing stress and to prevent the crack from developing according to the present invention, the breaking strength of the bonding portion is set to be greater than the bending moment that is received depending upon the shape of the ball. That is, the ratio d/l of the thickness d of the ball portion and the width l of the alloy layer formed by the pad and the wire at the time of bonding is selected to be smaller than 0.2.
摘要翻译: 集成程度越高,半导体芯片的尺寸越大。 在树脂模制的半导体器件中,特别是由于模制树脂和颗粒之间的热膨胀系数的差异,由于冷却时的收缩,在颗粒上产生裂纹。 裂纹明显地发生在焊接在颗粒上的焊盘上的焊丝球下。 接受剪切应力的区域随着球部分的增加而增加,并且裂纹容易发展。 为了减少剪切应力并防止根据本发明的裂纹显现,接合部分的断裂强度被设定为大于根据球的形状接收的弯曲力矩。 也就是说,接合时的球部的厚度d的比d / l和由焊盘和焊丝形成的合金层的宽度l选择为小于0.2。
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公开(公告)号:US08164186B2
公开(公告)日:2012-04-24
申请号:US11105546
申请日:2005-04-14
申请人: Yuji Watanabe , Hisashi Tanie , Koji Hosokawa , Mitsuaki Katagiri , Ichiro Anjo
发明人: Yuji Watanabe , Hisashi Tanie , Koji Hosokawa , Mitsuaki Katagiri , Ichiro Anjo
IPC分类号: H01L23/48
CPC分类号: H01L23/49816 , H01L23/3128 , H01L24/81 , H01L2224/81801 , H01L2924/15311 , H05K3/303 , H05K3/3436 , H05K2201/09781 , H05K2201/2036 , Y02P70/613
摘要: A BGA semiconductor device includes a semiconductor package and a mounting board mounting thereon the semiconductor package, wherein an array of signal electrodes of the semiconductor package and an array of signal electrodes of the mounting board are coupled together via signal bumps. The BGA semiconductor device also includes a dummy bump, which reinforces the bending strength of the BGA semiconductor device and is broken by a shearing force caused by thermal expansion to alleviate the stress for the signal bumps.
摘要翻译: BGA半导体器件包括半导体封装和安装在其上的半导体封装的安装板,其中半导体封装的信号电极阵列和安装板的信号电极阵列通过信号凸块耦合在一起。 BGA半导体器件还包括虚拟凸块,其加强了BGA半导体器件的弯曲强度,并被由热膨胀引起的剪切力破坏以减轻信号凸块的应力。
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公开(公告)号:US20100295179A1
公开(公告)日:2010-11-25
申请号:US12846120
申请日:2010-07-29
申请人: Yuji Watanabe , Hisashi Tanie , Koji Hosokawa , Mitsuaki Katagiri , Ichiro Anjo
发明人: Yuji Watanabe , Hisashi Tanie , Koji Hosokawa , Mitsuaki Katagiri , Ichiro Anjo
IPC分类号: H01L23/498
CPC分类号: H01L23/49816 , H01L23/3128 , H01L24/81 , H01L2224/81801 , H01L2924/15311 , H05K3/303 , H05K3/3436 , H05K2201/09781 , H05K2201/2036 , Y02P70/613
摘要: A BGA semiconductor device includes a semiconductor package and a mounting board mounting thereon the semiconductor package, wherein an array of signal electrodes of the semiconductor package and an array of signal electrodes of the mounting board are coupled together via signal bumps. The BGA semiconductor device also includes a dummy bump, which reinforces the bending strength of the BGA semiconductor device and is broken by a shearing force caused by thermal expansion to alleviate the stress for the signal bumps.
摘要翻译: BGA半导体器件包括半导体封装和安装在其上的半导体封装的安装板,其中半导体封装的信号电极阵列和安装板的信号电极阵列通过信号凸块耦合在一起。 BGA半导体器件还包括虚拟凸块,其加强了BGA半导体器件的弯曲强度,并被由热膨胀引起的剪切力破坏以减轻信号凸块的应力。
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公开(公告)号:US07119428B2
公开(公告)日:2006-10-10
申请号:US11025634
申请日:2004-12-28
申请人: Hisashi Tanie , Nae Hisano , Hiroyuki Ohta , Hiroaki Ikeda , Ichiro Anjo , Mitsuaki Katagiri , Yuji Watanabe
发明人: Hisashi Tanie , Nae Hisano , Hiroyuki Ohta , Hiroaki Ikeda , Ichiro Anjo , Mitsuaki Katagiri , Yuji Watanabe
IPC分类号: H01L23/22 , H01L23/053 , H01L21/44
CPC分类号: H01L25/0657 , H01L23/481 , H01L24/48 , H01L2224/05573 , H01L2224/05647 , H01L2224/13025 , H01L2224/16145 , H01L2224/16225 , H01L2224/45144 , H01L2224/48091 , H01L2224/48227 , H01L2224/48472 , H01L2224/73204 , H01L2225/06513 , H01L2225/0652 , H01L2225/06541 , H01L2225/06589 , H01L2225/06593 , H01L2924/00014 , H01L2924/01019 , H01L2924/01079 , H01L2924/01087 , H01L2924/10253 , H01L2924/14 , H01L2924/15311 , H01L2924/15312 , H01L2924/181 , H01L2924/19041 , H01L2924/19105 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要: A semiconductor device capable of reducing a temperature increase during operation thereof is provided. In the semiconductor device, an interface chip is stacked on a plurality of stacked semiconductor elements. Both an “Si” interposer and a resin interposer are arranged under the plural semiconductor elements. The Si interposer is arranged between the resin interposer and the plural semiconductor elements. The Si interposer owns a thickness which is thicker than a thickness of a semiconductor element, and also has a linear expansion coefficient which is smaller than a linear expansion coefficient of the resin interposer, and further, is larger than, or equal to linear expansion coefficients of the plural semiconductor elements.
摘要翻译: 提供一种能够在其操作期间降低温度升高的半导体器件。 在半导体装置中,在多个层叠的半导体元件上层叠有接口芯片。 “Si”插入件和树脂插入器都布置在多个半导体元件下方。 Si插入件布置在树脂插入件和多个半导体元件之间。 Si插入件具有比半导体元件的厚度厚的厚度,并且还具有比树脂插入体的线膨胀系数小的线膨胀系数,并且还大于或等于线膨胀系数 的多个半导体元件。
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公开(公告)号:US06621160B2
公开(公告)日:2003-09-16
申请号:US10046258
申请日:2002-01-16
申请人: Masanori Shibamoto , Masahiro Ichitani , Ryo Haruta , Katsuyuki Matsumoto , Junichi Arita , Ichiro Anjo
发明人: Masanori Shibamoto , Masahiro Ichitani , Ryo Haruta , Katsuyuki Matsumoto , Junichi Arita , Ichiro Anjo
IPC分类号: H01L2334
CPC分类号: H01L24/50 , H01L23/13 , H01L23/16 , H01L23/24 , H01L23/293 , H01L23/3128 , H01L23/34 , H01L23/36 , H01L23/3672 , H01L23/3675 , H01L23/3732 , H01L23/3735 , H01L23/3736 , H01L23/3737 , H01L23/49572 , H01L23/49816 , H01L23/4985 , H01L24/48 , H01L24/73 , H01L2224/16 , H01L2224/16225 , H01L2224/16227 , H01L2224/29144 , H01L2224/32225 , H01L2224/32245 , H01L2224/48091 , H01L2224/48227 , H01L2224/73253 , H01L2224/73265 , H01L2224/73269 , H01L2224/92247 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01058 , H01L2924/01074 , H01L2924/01079 , H01L2924/01082 , H01L2924/0132 , H01L2924/01322 , H01L2924/15153 , H01L2924/1517 , H01L2924/15311 , H01L2924/15312 , H01L2924/1532 , H01L2924/16195 , H01L2924/181 , H01L2924/30107 , H01L2924/351 , H01L2924/0105 , H01L2924/00012 , H01L2924/00 , H01L2924/01014 , H01L2224/45099
摘要: A semiconductor device in which a semiconductor chip 1 is bonded by a metal bond 2 to one surface of a heat sink 4 formed of a material with a thermal expansion coefficient is close to he semiconductor chip 1, the heat sink 4 is glued to a stiffener with a silicon adhesive 5 with an elastic modulus of 10 MPa or less, a TAB tape 9 is glued to the stiffener 3 with an epoxy adhesive 6, and the semiconductor chip 1 is sealed with an epoxy sealing resin 8 with an elastic modulus of 10 GPa or more for protection from outside.
摘要翻译: 其中半导体芯片1通过金属接合2接合到由具有热膨胀系数的材料形成的散热器4的一个表面接近半导体芯片1的半导体器件,散热器4被胶合到加强件 使用弹性模量为10MPa以下的硅粘合剂5,用环氧树脂粘合剂6将TAB带9胶合到加强件3,并用环氧树脂密封树脂8密封弹性模量为10的半导体芯片1 GPa或更多用于保护外部。
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