公开(公告)号：US20050249779A1

公开(公告)日：2005-11-10

申请号：US10530813

申请日：2003-10-03

申请人： Munehiro Oda ,  Sigeru Aizawa ,  Masayuki Uchida ,  Masayuki Suzuki ,  Manabu Sase

发明人： Munehiro Oda ,  Sigeru Aizawa ,  Masayuki Uchida ,  Masayuki Suzuki ,  Manabu Sase

IPC分类号： A23C19/08 ,  A23C19/082 ,  A23C9/12 ,  A61K47/00

CPC分类号： A23C19/082 ,  A23C19/08

摘要： Processed cheeses with an antihypertensive effect greater than that of conventional cheese are provided in order to obtain a sufficient antihypertensive effect with a small intake. Specifically, processed cheeses with ACE inhibitory activity of 350 units per gram or more are manufactured using natural cheese such as cheddar cheese produced in New Zealand and Emmental cheese produced in Switzerland with ACE inhibitory activity of 420 units per grams or more. In addition, it is preferable to use low salt or unsalted natural cheese as a raw material, and use potassium salt as molten salt in order to make sodium content 990 mg or less per 100 g of processed cheese.

摘要翻译： 提供具有比常规乳酪更高的抗高血压作用的加工奶酪，以便以小的摄取获得足够的抗高血压作用。 具体来说，使用天然干酪如新西兰生产的切达干酪和瑞士生产的Emmental奶酪，每克或更多的ACE抑制活性为420单位，制成具有350单位/克或更多的ACE抑制活性的加工奶酪。 此外，优选使用低盐或无盐天然干酪作为原料，并且使用钾盐作为熔融盐，以使每100g加工奶酪的钠含量为990mg以下。

公开(公告)号：US20050186729A1

公开(公告)日：2005-08-25

申请号：US11110693

申请日：2005-04-21

申请人： Shinichi Fukada ,  Naotaka Hashimoto ,  Masanori Kojima ,  Hiroshi Momiji ,  Hiromi Abe ,  Masayuki Suzuki

发明人： Shinichi Fukada ,  Naotaka Hashimoto ,  Masanori Kojima ,  Hiroshi Momiji ,  Hiromi Abe ,  Masayuki Suzuki

IPC分类号： H01L21/336 ,  H01L21/8238 ,  H01L21/8242

CPC分类号： H01L29/6659 ,  H01L21/2652 ,  H01L21/28518 ,  H01L21/823814 ,  H01L21/823835 ,  H01L21/823842 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/7833

摘要： An implantation step of a dopant ion for forming source and drain regions (S and D) is divided into one implantation of a dopant ion for forming a p/n junction with a well region (3), and one implantation of a dopant ion that does not influence a position of the p/n junction between the source and drain regions (S and D) and the well region with a shallow implantation depth and a large implantation amount. After conducting an activation heat treatment of the dopant, a surface of the source/drain region is made into cobalt silicide 12, so that the source/drain region (S and D) can have a low resistance, and a p/n junction leakage can be reduced.

摘要翻译： 用于形成源区和漏区（S和D）的掺杂剂离子的注入步骤被划分为用于与阱区（3）形成ap / n结的掺杂剂离子的一次注入，并且一次注入掺杂剂离子 不影响源极和漏极区域（S和D）之间的p / n结的位置以及具有浅的注入深度和大的注入量的阱区域。 在对掺杂剂进行激活热处理之后，将源极/漏极区域的表面制成硅化钴12，使得源极/漏极区域（S和D）可以具有低电阻，并且ap / n结泄漏可以 减少

公开(公告)号：US20050118805A1

公开(公告)日：2005-06-02

申请号：US11006702

申请日：2004-12-08

申请人： Shinji Nishihara ,  Shuji Ikeda ,  Naotaka Hashimoto ,  Hiroshi Momiji ,  Hiromi Abe ,  Shinichi Fukada ,  Masayuki Suzuki

发明人： Shinji Nishihara ,  Shuji Ikeda ,  Naotaka Hashimoto ,  Hiroshi Momiji ,  Hiromi Abe ,  Shinichi Fukada ,  Masayuki Suzuki

IPC分类号： H01L21/285 ,  H01L21/336 ,  H01L21/762 ,  H01L21/8238 ,  H01L23/532 ,  H01L29/45 ,  H01L29/49 ,  H01L29/78 ,  H01L21/3205 ,  H01L21/4763 ,  H01L21/44

CPC分类号： H01L21/823814 ,  C23C14/16 ,  C23C14/3414 ,  H01L21/28518 ,  H01L21/2855 ,  H01L21/31608 ,  H01L21/76229 ,  H01L21/76828 ,  H01L21/823835 ,  H01L21/823842 ,  H01L21/823871 ,  H01L23/53223 ,  H01L29/456 ,  H01L29/4933 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833 ,  H01L2924/0002 ,  H01L2924/00

摘要： A Co silicide layer having a low resistance and a small junction leakage current is formed on the surface of the gate electrode, source and drain of MOSFETs by silicidizing a Co film deposited on a main plane of a wafer by sputtering using a high purity Co target having a Co purity of at least 99.99% and Fe and Ni contents of not greater than 10 ppm, preferably having a Co purity of 99.999%.

公开(公告)号：US20050056635A1

公开(公告)日：2005-03-17

申请号：US10670337

申请日：2003-09-26

申请人： Masayuki Suzuki ,  Hideo Ishizu

发明人： Masayuki Suzuki ,  Hideo Ishizu

IPC分类号： H05B3/00 ,  F27D19/00 ,  F27D21/00 ,  H01L21/00 ,  H01L21/205 ,  H01L21/324 ,  H05B1/02

CPC分类号： H05B1/0233 ,  F27D19/00 ,  F27D21/0014 ,  H01L21/67248

摘要： To find the deterioration degree of a heater that heats a furnace. The present invention includes: a current detector 21 that detects a level of a current flowing through a heater 7 that is heated based on a commercial power source 1; a voltage detector 20 that detects a level of a voltage applied to the heater 7; a temperature detector 22 that detects a temperature of the heater 7; a table memory 14 on which a temperature coefficient of resistance for use in calculation of a resistance of the heater 7 at a time of manufacture is stored; and a CPU 17A that calculates a resistance of the heater 7 at an inspection time based on respective detection results by the voltage detector 20 and the current detector 21 and calculates the resistance of the heater 7 at a reference time based on a detection result by the temperature detector 22 and the temperature coefficient of resistance stored on the table memory 14, thereby finding the deterioration degree of the heater 7 based on the resistance of the heater 7 at the inspection time and the resistance of the heater 7 at the reference time.

摘要翻译： 找到加热炉的加热器的劣化程度。 本发明包括：电流检测器21，其检测流过基于商用电源1加热的加热器7的电流的电平; 检测施加到加热器7的电压的电平的电压检测器20; 温度检测器22，其检测加热器7的温度; 存储用于计算制造时的加热器7的电阻的电阻的温度系数的表存储器14; 以及CPU 17A，其基于电压检测器20和电流检测器21的各检测结果，在检查时刻计算加热器7的电阻，并基于检测结果由基准时间计算加热器7的电阻 温度检测器22和存储在台式存储器14上的电阻温度系数，从而基于加热器7在检查时的电阻和加热器7在参考时间的电阻而发现加热器7的劣化程度。

公开(公告)号：US20050003586A1

公开(公告)日：2005-01-06

申请号：US10902785

申请日：2004-08-02

申请人： Yoshihiko Shimanuki ,  Masayuki Suzuki

发明人： Yoshihiko Shimanuki ,  Masayuki Suzuki

IPC分类号： H01L23/12 ,  H01L21/301 ,  H01L21/304 ,  H01L21/48 ,  H01L21/56 ,  H01L23/28 ,  H01L23/31 ,  H01L21/44 ,  H01L21/50 ,  H01L23/495

CPC分类号： H01L24/32 ,  H01L21/4832 ,  H01L21/561 ,  H01L23/3107 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/97 ,  H01L2221/68377 ,  H01L2224/05554 ,  H01L2224/29007 ,  H01L2224/29111 ,  H01L2224/29139 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/48639 ,  H01L2224/48644 ,  H01L2224/48664 ,  H01L2224/49113 ,  H01L2224/49171 ,  H01L2224/49433 ,  H01L2224/73265 ,  H01L2224/85439 ,  H01L2224/85444 ,  H01L2224/85464 ,  H01L2224/92247 ,  H01L2224/97 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01019 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01083 ,  H01L2924/0132 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/3025 ,  H01L2924/00014 ,  H01L2224/83 ,  H01L2224/85 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/01026 ,  H01L2924/0105 ,  H01L2924/01082 ,  H01L2924/3512

摘要： A non-leaded resin-sealed semiconductor device is manufactured by the steps of providing a conductive flat substrate (metal plate) of copper plate or the like, fixing semiconductor elements respectively to predetermined positions on the principal surface of the substrate by an insulating adhesive, electrically connecting electrodes on the surfaces of the semiconductor elements with predetermined partition parts of the substrate separate from the semiconductor elements by conductive wires, forming an insulating resin layer on the principal surface of the substrate to cover the semiconductor elements and wires, selectively removing the substrate from the rear of said substrate to form electrically independent partition parts whereof at least some are external electrode terminals, and selectively removing said resin layer to fragment the device into regions containing the semiconductor elements and the plural partition parts around the semiconductor elements. Thus, there is provided a compact non-leaded semiconductor device having a large number of electrode terminals.

摘要翻译： 非导电树脂密封半导体器件通过以下步骤制造：提供铜板等的导电平面基板（金属板），通过绝缘粘合剂将半导体元件分别固定在基板的主表面上的预定位置， 将半导体元件的表面上的电极与基板的预定分隔部分用导电线与半导体元件分开，在基板的主表面上形成绝缘树脂层以覆盖半导体元件和导线，选择性地去除基板 从所述基板的后部形成电气独立的分隔部，其中至少一些是外部电极端子，并且选择性地去除所述树脂层以将器件分解成包含半导体元件的区域和围绕半导体元件的多个分隔部分。 因此，提供了具有大量电极端子的紧凑的非铅半导体器件。

公开(公告)号：US06818457B2

公开(公告)日：2004-11-16

申请号：US10153776

申请日：2002-05-24

申请人： Masayuki Suzuki

发明人： Masayuki Suzuki

IPC分类号： H01L2100

CPC分类号： H01L21/02183 ,  H01L21/0223 ,  H01L21/02271 ,  H01L21/02337 ,  H01L21/02356 ,  H01L21/31604 ,  H01L27/10814 ,  H01L28/40

摘要： After formation of a lower electrode, made of an Ru film, over the side walls and bottom portion of a hole in a silicon oxide film, wherein an information storage capacitive element is to be formed, a tantalum oxide film, which is to serves as a capacitive insulating film, is deposited by CVD over the lower electrode. In order to improve the quality of this tantalum oxide film, heat treatment of it is conducted in a mixed gas atmosphere of H2O (water vapor) and H2 (hydrogen), while controlling a partial pressure ratio of H2O to H2 so as to fall within a region bounded by the curves (a) and (c) of FIG. 15. This heat treatment makes it possible to improve the quality of the tantalum oxide film, while preventing oxidation of the Ru film constituting the lower electrode.

摘要翻译： 在形成要形成信息存储电容元件的氧化硅膜中形成由Ru膜制成的下电极，在氧化硅膜上的孔的侧壁和底部之上，形成氧化钽膜，其用作 电容绝缘膜通过CVD沉积在下电极上。 为了提高该钽氧化物膜的质量，在H 2 O（水蒸气）和H 2（氢）的混合气体气氛中进行热处理，同时控制H 2 O与H 2的分压比，使其落入 由图1的曲线（a）和（c）限定的区域。 该热处理使得可以提高氧化钽膜的质量，同时防止构成下电极的Ru膜的氧化。

公开(公告)号：US06723583B2

公开(公告)日：2004-04-20

申请号：US10453606

申请日：2003-06-04

申请人： Noriyuki Takahashi ,  Masayuki Suzuki ,  Kouji Tsuchiya ,  Takao Matsuura ,  Takanori Hashizume ,  Masahiro Ichitani ,  Kazunari Suzuki ,  Takafumi Nishita ,  Kenichi Imura ,  Takashi Miwa

发明人： Noriyuki Takahashi ,  Masayuki Suzuki ,  Kouji Tsuchiya ,  Takao Matsuura ,  Takanori Hashizume ,  Masahiro Ichitani ,  Kazunari Suzuki ,  Takafumi Nishita ,  Kenichi Imura ,  Takashi Miwa

IPC分类号： H01L2144

CPC分类号： H01L23/564 ,  H01L21/561 ,  H01L21/565 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49838 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/97 ,  H01L2223/5442 ,  H01L2223/54473 ,  H01L2224/16 ,  H01L2224/32225 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/73265 ,  H01L2224/92 ,  H01L2224/97 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01023 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/07802 ,  H01L2924/0781 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15151 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/20752 ,  H01L2924/30105 ,  H01L2924/351 ,  H01L2224/83 ,  H01L2224/85 ,  H01L2924/00014 ,  H01L2224/92247 ,  H01L2924/00 ,  H01L2924/00012

摘要： The back side of a strip substrate with plural semiconductor chips mounted thereon is vacuum-chucked to a lower mold half of a mold, and in this state the plural semiconductor chips are sealed with resin simultaneously to form a seal member. Thereafter, the strip substrate and the seal member are released from the mold and are cut into plural semiconductor devices. The semiconductor devices thus obtained are improved in their mounting reliability.

摘要翻译： 将其上安装有多个半导体芯片的带状基板的背面真空吸附到模具的下半模，并且在该状态下，多个半导体芯片同时用树脂密封以形成密封构件。 此后，带状基板和密封构件从模具中释放并切割成多个半导体器件。 由此获得的半导体器件的安装可靠性得到改善。

公开(公告)号：US06707532B2

公开(公告)日：2004-03-16

申请号：US09790865

申请日：2001-02-23

申请人： Masayuki Suzuki

发明人： Masayuki Suzuki

IPC分类号： G03B2768

CPC分类号： G02B17/0892 ,  G02B17/008 ,  G02B17/08 ,  G02B17/0812 ,  G02B27/0025 ,  G03F7/70225 ,  G03F7/70258 ,  G03F7/70308

摘要： An exposure apparatus includes a projection optical system of a catadioptric type and an optical element disposed on a reciprocating light path of the projection optical system. The optical element is movable along an optical axis direction.

摘要翻译： 曝光装置包括反射折射型的投影光学系统和设置在投影光学系统的往复光路上的光学元件。 光学元件可沿光轴方向移动。

公开(公告)号：US06666560B2

公开(公告)日：2003-12-23

申请号：US10136722

申请日：2002-04-30

申请人： Masayuki Suzuki

发明人： Masayuki Suzuki

IPC分类号： G02B510

CPC分类号： G03F7/70233 ,  G02B17/0657

摘要： A reflection type magnification projection optical system includes five light-reflecting mirrors arranged from an object side to an image side in a sequence of a concave mirror (M1), a convex mirror (M2), a concave mirror (M3), a convex mirror (M4), and a concave mirror (M5) such that those mirrors basically form a coaxial system, and forming no intermediate image, and wherein an object point and an image point are respectively on opposite sides across an optical axis, and the object point and the image point are kept 400˜1500 mm apart with respect to a direction orthogonal to the optical axis.

摘要翻译： 反射型放大投影光学系统包括从凹面镜（M1），凸面镜（M2），凹面镜（M3），凸面镜（M3），凸面镜 （M4）和凹面镜（M5），使得这些反射镜基本上形成同轴系统，并且不形成中间图像，并且其中物点和像点分别在光轴的相对侧上，并且物点 并且相对于与光轴正交的方向，图像点保持400〜1500mm。

公开(公告)号：US06511778B2

公开(公告)日：2003-01-28

申请号：US09753517

申请日：2001-01-04

申请人： Satoshi Okazaki ,  Ichiro Kaneko ,  Jiro Moriya ,  Masayuki Suzuki ,  Tamotsu Maruyama

发明人： Satoshi Okazaki ,  Ichiro Kaneko ,  Jiro Moriya ,  Masayuki Suzuki ,  Tamotsu Maruyama

IPC分类号： G03F900

CPC分类号： G03F1/32 ,  G03F1/26

摘要： A phase shift mask blank comprising a transparent substrate and at least one layer of a phase shifter thereon, wherein the phase shifter is a film composed primarily of a fluorine-doped metal silicide, can be fabricated into a high-performance phase shift mask having adequate transmittance and good stability over time even when used with light sources that emit short-wavelength light. The phase shift mask can be used to fabricate semiconductor integrated circuits to a smaller minimum feature size and a higher level of integration.

摘要翻译： 一种相移掩模坯料，其包括透明基板和至少一层其上的移相器，其中移相器是主要由掺氟金属硅化物构成的膜，可以被制成具有足够的高性能相移掩模 即使在与发出短波长光的光源一起使用时，透射率和稳定性也很好。 相移掩模可用于将半导体集成电路制造成更小的最小特征尺寸和更高的集成度。