公开(公告)号：US09911485B2

公开(公告)日：2018-03-06

申请号：US14244173

申请日：2014-04-03

Applicant: QUALCOMM Incorporated

Inventor： Deepti Vijayalakshmi Sriramagiri ,  Jung Pill Kim ,  Jungwon Suh ,  Xiangyu Dong

IPC: G06F12/00 ,  G11C11/406

CPC classification number: G11C11/40618 ,  G11C11/406 ,  G11C11/40603 ,  G11C11/40615 ,  G11C11/40626 ,  G11C2211/406

Abstract: A method includes sending a first signal from a memory device to a memory controller. The first signal indicates to the memory controller that particular memory cells of the memory device are to be refreshed by the memory device.

公开(公告)号：US09800271B2

公开(公告)日：2017-10-24

申请号：US14852988

申请日：2015-09-14

Applicant: QUALCOMM Incorporated ,  Industry-Academic Cooperation Foundation, Yonsei University

Inventor： Seong-Ook Jung ,  Sara Choi ,  Byung Kyu Song ,  Taehui Na ,  Jisu Kim ,  Jung Pill Kim ,  Sungryul Kim ,  Taehyun Kim ,  Seung Hyuk Kang

IPC: H03M13/00 ,  G06F11/10 ,  H03M13/15

CPC classification number: H03M13/616 ,  G06F11/10 ,  G06F11/1012 ,  H03M13/152 ,  H03M13/1575 ,  H03M13/617 ,  H03M13/6502

Abstract: Error detection and correction decoding apparatus performs single error correction-double error detection (SEC-DED) or double error correction-triple error detection (DEC-TED) depending on whether the data input contains a single-bit error or a multiple-bit error, to reduce power consumption and latency in case of single-bit errors and to provide powerful error correction in case of multiple-bit errors.

公开(公告)号：US09753874B2

公开(公告)日：2017-09-05

申请号：US14627318

申请日：2015-02-20

Applicant: QUALCOMM Incorporated

Inventor： Adam Edward Newham ,  Rashid Ahmed Akbar Attar ,  Seung Hyuk Kang ,  Jung Pill Kim ,  Sungryul Kim ,  Taehyun Kim

IPC: G06F13/28 ,  G06F12/02 ,  G06F9/44

CPC classification number: G06F13/28 ,  G06F9/4406 ,  G06F12/0246 ,  G06F2212/7209

Abstract: Multi-step programming of heat-sensitive non-volatile memory (NVM) in processor-based systems, and related methods and systems are disclosed. To avoid relying on programmed instructions stored in heat-sensitive NVM during fabrication, wherein the programmed instructions can become corrupted during thermal packaging processes, the NVM is programmed in a multi-step programming process. In a first programming step, a boot loader comprising programming instructions is loaded into the NVM. The boot loader may be loaded into the NVM after the thermal processes during packaging are completed to avoid risking data corruption in the boot loader. Thereafter, the programmed image can be loaded quickly into a NV program memory over the peripheral interface using the boot loader to save programming time and associated costs, as opposed to loading the programmed image using lower transfer rate programming techniques. The processor can execute the program instructions to carry out tasks in the processor-based system.

公开(公告)号：US09679663B2

公开(公告)日：2017-06-13

申请号：US14994231

申请日：2016-01-13

Applicant: QUALCOMM Incorporated

Inventor： Jung Pill Kim ,  Taehyun Kim ,  Kangho Lee ,  Seung H. Kang ,  Xia Li ,  Wah Nam Hsu

IPC: G11C11/00 ,  G11C17/18 ,  G11C11/16 ,  G11C17/02 ,  G11C17/16

CPC classification number: G11C17/18 ,  G11C11/16 ,  G11C11/1673 ,  G11C11/1675 ,  G11C17/02 ,  G11C17/16 ,  G11C17/165

Abstract: A one time programming (OTP) apparatus unit cell includes magnetic tunnel junctions (MTJs) with reversed connections for placing the MTJ in an anti-parallel resistance state during programming. Increased MTJ resistance in its anti-parallel resistance state causes a higher programming voltage which reduces programming time and programming current.

公开(公告)号：US09653183B1

公开(公告)日：2017-05-16

申请号：US15254068

申请日：2016-09-01

Applicant: QUALCOMM Incorporated

Inventor： Hyunsuk Shin ,  Sungryul Kim ,  Jung Pill Kim

IPC: G11C29/00 ,  G11C29/18 ,  G11C11/16 ,  G11C29/12

CPC classification number: G11C29/18 ,  G11C8/12 ,  G11C11/165 ,  G11C11/1677 ,  G11C29/1201 ,  G11C29/26 ,  G11C29/44 ,  G11C29/4401

Abstract: Shared built-in self-analysis of memory systems employing a memory array tile architecture is provided. To selectively control which memory tile among a plurality of memory tiles is accessed for a built-in self-analysis (BISA) operation, a shared BISA address issued from a shared BISA circuit includes a memory tile address. Each memory tile includes a unique fixed memory tile address that is compared to the received memory tile address of a received BISA address. If the memory tile address in the received BISA address matches the fixed memory tile address of a memory tile, the memory tile is activated to use the memory address in the BISA address to access addressed memory bit cells for analysis. Thus, if the memory system is redesigned to include additional memory tiles for increased capacity, the memory tile address size in the BISA address can be updated for addressing added memory tiles.

公开(公告)号：US09633706B1

公开(公告)日：2017-04-25

申请号：US15289495

申请日：2016-10-10

Applicant: QUALCOMM Incorporated

Inventor： Sungryul Kim ,  Jung Pill Kim ,  Hyunsuk Shin

IPC: G11C11/14 ,  G11C11/16

CPC classification number: G11C11/1657 ,  G11C8/08 ,  G11C8/10 ,  G11C8/18 ,  G11C11/1653 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/1693 ,  G11C11/1697

Abstract: A voltage self-boosting circuit for generating a boosted voltage for driving a word line write in a memory array for a memory write operation is provided. A voltage generation circuit(s) is configured to generate a read voltage for a memory read operation and a write voltage for a memory write operation based on a predefined supply voltage. For the memory write operation, a delay circuit delays the delay circuit enable signal by a predetermined delay to generate the output voltage control signal. Accordingly, the voltage generation circuit(s) generates boosted voltage that drives the write voltage to a selected word line(s). For the memory read operation, the voltage generation circuit(s) does not generate the boosted voltage and thus drives the read voltage to the selected word line(s). Hence, it is possible to reduce power consumption and timing delay during the memory read operation or the memory write operation.

公开(公告)号：US20160358649A1

公开(公告)日：2016-12-08

申请号：US15244456

申请日：2016-08-23

Applicant: QUALCOMM Incorporated

Inventor： Jung Pill Kim ,  Taehyun Kim

IPC: G11C13/00

CPC classification number: G11C13/004 ,  G11C5/063 ,  G11C7/08 ,  G11C11/1673 ,  G11C13/0038 ,  G11C13/0069 ,  G11C29/026 ,  G11C29/028 ,  G11C2013/0054

Abstract: A memory has a plurality of non-volatile resistive (NVR) memory arrays, each with an associated reference voltage generating circuit coupled by a reference circuit coupling link to a reference line, the reference coupled to a sense amplifier for that NVR memory array. Reference line coupling links couple the reference lines of different NVR memory arrays. Optionally, different ones of the reference coupling links are removed or opened, obtaining respective different average and isolated reference voltages on the different reference lines. Optionally, different ones of the reference circuit coupling links are removed or opened, obtaining respective different averaged voltages on the reference lines, and uncoupling and isolating different reference circuits.

公开(公告)号：US09431129B2

公开(公告)日：2016-08-30

申请号：US14266326

申请日：2014-04-30

Applicant: QUALCOMM Incorporated

Inventor： Jung Pill Kim ,  Taehyun Kim ,  Sungryul Kim ,  Xiangyu Dong

IPC: G11C29/02 ,  G11C29/30 ,  G11C7/10 ,  G11C16/26 ,  G11C16/30 ,  G11C14/00 ,  G06F11/10 ,  G11C29/52 ,  G11C7/06 ,  G11C7/08 ,  G11C29/04 ,  G11C11/16 ,  G11C13/00

CPC classification number: G11C29/026 ,  G06F11/106 ,  G06F11/1072 ,  G06F11/1076 ,  G11C7/06 ,  G11C7/08 ,  G11C7/1006 ,  G11C7/1072 ,  G11C11/16 ,  G11C11/1673 ,  G11C13/004 ,  G11C14/0081 ,  G11C14/009 ,  G11C16/26 ,  G11C16/30 ,  G11C29/30 ,  G11C29/52 ,  G11C2029/0411

Abstract: A device includes a plurality of memory cells of a memory array, a sense amplifier of the memory array, and selection logic of the memory array. The sense amplifier is configured to sense at least one data value from at least one memory cell of the plurality of memory cells. The selection logic is configured to select between causing the sense amplifier to sense the at least one data value using a first sensing delay and causing the sense amplifier to sense the at least one data value using a second sensing delay. The second sensing delay is longer than the first sensing delay.

Abstract translation: 一种器件包括存储器阵列的多个存储单元，存储器阵列的读出放大器和存储器阵列的选择逻辑。 感测放大器被配置为感测来自多个存储器单元中的至少一个存储单元的至少一个数据值。 选择逻辑被配置为在使感测放大器使用第一感测延迟来感测至少一个数据值并且使得感测放大器使用第二感测延迟来感测至少一个数据值之间进行选择。 第二感测延迟比第一感测延迟更长。

公开(公告)号：US20160246608A1

公开(公告)日：2016-08-25

申请号：US14627318

申请日：2015-02-20

Applicant: QUALCOMM Incorporated

Inventor： Adam Edward Newham ,  Rashid Ahmed Akbar Attar ,  Seung Hyuk Kang ,  Jung Pill Kim ,  Sungryul Kim ,  Taehyun Kim

IPC: G06F9/44 ,  G06F13/28 ,  G06F12/02

CPC classification number: G06F13/28 ,  G06F9/4406 ,  G06F12/0246 ,  G06F2212/7209

Abstract: Multi-step programming of heat-sensitive non-volatile memory (NVM) in processor-based systems, and related methods and systems are disclosed. To avoid relying on programmed instructions stored in heat-sensitive NVM during fabrication, wherein the programmed instructions can become corrupted during thermal packaging processes, the NVM is programmed in a multi-step programming process. In a first programming step, a boot loader comprising programming instructions is loaded into the NVM. The boot loader may be loaded into the NVM after the thermal processes during packaging are completed to avoid risking data corruption in the boot loader. Thereafter, the programmed image can be loaded quickly into a NV program memory over the peripheral interface using the boot loader to save programming time and associated costs, as opposed to loading the programmed image using lower transfer rate programming techniques. The processor can execute the program instructions to carry out tasks in the processor-based system.

Abstract translation: 公开了基于处理器的系统中的热敏非易失性存储器（NVM）的多步编程以及相关的方法和系统。 为了避免在制造期间依赖于存储在热敏NVM中的编程指令，其中编程指令可能在热封装过程中被破坏，NVM以多步编程过程编程。 在第一编程步骤中，包括编程指令的引导加载器被加载到NVM中。 引导加载程序可能在打包完成后的热处理后加载到NVM中，以避免引导加载程序中的数据损坏风险。 此后，与使用较低传输速率编程技术加载编程图像相比，编程图像可以使用引导加载程序通过外设接口快速加载到NV程序存储器中，从而节省编程时间和相关成本。 处理器可以执行程序指令以在基于处理器的系统中执行任务。

公开(公告)号：US09379201B2

公开(公告)日：2016-06-28

申请号：US14805745

申请日：2015-07-22

Applicant: QUALCOMM Incorporated

Inventor： Vidhya Ramachandran ,  Brian Matthew Henderson ,  Shiqun Gu ,  Chiew-Guan Tan ,  Jung Pill Kim ,  Taehyun Kim

IPC: H01L21/4763 ,  H01L29/66 ,  H01L23/498 ,  H01L29/861 ,  H01L21/768 ,  H01L29/872 ,  H01L21/762 ,  H01L29/06 ,  H01L27/08 ,  H01L21/304 ,  H01L23/48 ,  H01L23/60 ,  H01L27/02 ,  H01L27/06 ,  H01L23/535 ,  H01L25/065 ,  H01L23/525

CPC classification number: H01L29/66128 ,  H01L21/304 ,  H01L21/762 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/49827 ,  H01L23/525 ,  H01L23/535 ,  H01L23/60 ,  H01L25/0657 ,  H01L27/0255 ,  H01L27/0296 ,  H01L27/0694 ,  H01L27/0814 ,  H01L29/0649 ,  H01L29/66143 ,  H01L29/8611 ,  H01L29/872 ,  H01L2224/02372 ,  H01L2224/0239 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/0557 ,  H01L2224/11002 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/16145 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/12032 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2224/05552

Abstract: A method includes thinning a back-side of a substrate to expose a portion of a first via that is formed in the substrate. The method also includes forming a first diode at the back-side of the substrate. The first diode is coupled to the first via.

Abstract translation: 一种方法包括使衬底的背面变薄以暴露形成在衬底中的第一通孔的一部分。 该方法还包括在衬底的背面形成第一二极管。 第一二极管耦合到第一通孔。