公开(公告)号：US10181410B2

公开(公告)日：2019-01-15

申请号：US14634547

申请日：2015-02-27

Applicant: QUALCOMM Incorporated

Inventor： Young Kyu Song ,  Kyu-Pyung Hwang ,  Hong Bok We

IPC: H01G4/12 ,  H01G4/224 ,  H01L21/48 ,  H01L23/00 ,  H01L23/498

Abstract: Many aspects of an improved IC package are disclosed herein. The improved IC package exhibits low-impedance and high power and signal integrity. The improved IC package comprises an IC die mounted on a multilayer coreless substrate. The thicknesses of prepreg layers of the coreless substrate are specific chosen to minimize warpage and to provide good mechanical performance. Each of the prepreg layers may have different coefficient of thermal expansion (CTE) and/or thickness to enable better control of the coreless substrate mechanical properties. The improved IC package also includes a vertically mounted die side capacitor and a conductive layer formed on the solder resist layer of the substrate. The conductive layer is formed such that it also encapsulates the vertically mounted capacitor while being electrically coupled to one of the capacitor's electrode.

公开(公告)号：US10109584B2

公开(公告)日：2018-10-23

申请号：US14474860

申请日：2014-09-02

Applicant: QUALCOMM Incorporated

Inventor： Uei-Ming Jow ,  Young Kyu Song ,  Jung Ho Yoon ,  Jong-Hoon Lee ,  Xiaonan Zhang

IPC: H01F17/00 ,  H01F27/28 ,  H01L21/48 ,  H01L23/00 ,  H01L23/31 ,  H01L23/64 ,  H01L49/02 ,  H01L23/495 ,  H01L23/498 ,  H01L23/522 ,  H01L23/528

Abstract: A semiconductor package according to some examples of the disclosure may include a first body layer, a transformer that may comprise one or more inductors, coupled inductors, or inductive elements positioned above the first body layer. A first ground plane is on a top of the first body layer between the first body layer and the inductive element. The first ground plane may have conductive lines generally perpendicular to a magnetic field generated by the inductive element, and a second ground plane on a bottom of the first body layer opposite the first ground plane. The first and second ground planes may also provide heat dissipation elements for the semiconductor as well as reduce or eliminate eddy current and parasitic effects produced by the inductive element.

公开(公告)号：US09933455B2

公开(公告)日：2018-04-03

申请号：US14703677

申请日：2015-05-04

Applicant: QUALCOMM Incorporated

Inventor： Young Kyu Song ,  Kyu-Pyung Hwang

IPC: G01R1/04 ,  G01R1/073 ,  G01R31/28 ,  G01R29/08 ,  G01R1/067

CPC classification number: G01R1/045 ,  G01R1/06722 ,  G01R1/06772 ,  G01R1/07314 ,  G01R29/08 ,  G01R31/2822

Abstract: Embodiments contained in the disclosure provide a method and apparatus for testing an electronic device. An electronic device is installed in a test socket guide. A pusher tip applies a load to the guided coaxial spring probes and forces contact with pads on the device. Test and ground signals are routed through the device and test socket. The apparatus includes a socket having at least one guided coaxial spring probe pin. A socket guide shim is positioned between the receptacle for the electronic device and the socket. A socket guide aids positioning. A pusher tip is placed on the side opposite that of the guided coaxial spring probe pins. The pusher tip mates with a pusher shim and the pusher spring. A top is then placed on the assembly and acts to compress the pusher spring and engage the guided coaxial spring probe pins with the pads on the device.

公开(公告)号：US09807884B2

公开(公告)日：2017-10-31

申请号：US14579651

申请日：2014-12-22

Applicant: QUALCOMM Incorporated

Inventor： Kyu-Pyung Hwang ,  Young Kyu Song

IPC: H05K1/18 ,  H05K1/11 ,  H05K1/02 ,  H05K3/46 ,  H05K3/30 ,  H05K3/40 ,  H01G4/248 ,  H01G4/012 ,  H01G4/005 ,  H01G4/232 ,  H01L23/538 ,  H01L23/50 ,  H01G4/30 ,  H01L23/00 ,  H01L25/065

CPC classification number: H05K1/185 ,  H01G4/005 ,  H01G4/012 ,  H01G4/232 ,  H01G4/248 ,  H01G4/30 ,  H01L23/50 ,  H01L23/5383 ,  H01L24/16 ,  H01L25/0655 ,  H01L2224/16227 ,  H01L2924/15174 ,  H01L2924/15311 ,  H05K1/0231 ,  H05K1/0298 ,  H05K1/111 ,  H05K1/115 ,  H05K3/30 ,  H05K3/4007 ,  H05K3/4038 ,  H05K3/46 ,  H05K3/4602 ,  H05K3/4697 ,  H05K2201/0187 ,  H05K2201/09781 ,  H05K2201/10015 ,  H05K2201/10636 ,  Y02P70/611

Abstract: A substrate that includes a first dielectric layer and a capacitor embedded in the first dielectric layer. The capacitor includes a first terminal, a second terminal, and a third terminal. The second terminal is laterally located between the first terminal and the third terminal. The capacitor also includes a second dielectric layer, a first metal layer and a second metal layer. The first metal layer is coupled to the first and third terminals. The first metal layer, the first terminal, and the third terminal are configured to provide a first electrical path for a first signal. The second metal layer is coupled to the second terminal. The second metal layer and the second terminal are configured to provide a second electrical path for a second signal.

公开(公告)号：US09806144B2

公开(公告)日：2017-10-31

申请号：US14079488

申请日：2013-11-13

Applicant: QUALCOMM Incorporated

Inventor： Daeik Daniel Kim ,  Young Kyu Song ,  Xiaonan Zhang ,  Jonghae Kim

IPC: H01L49/02 ,  H01F17/00 ,  H01F41/04

CPC classification number: H01L28/10 ,  H01F17/0013 ,  H01F41/041 ,  H01F2017/0053

Abstract: Some implementations provide an integrated device (e.g., semiconductor device) that includes a substrate and an inductor in the substrate. In some implementations, the inductor is a solenoid inductor. The inductor includes a set of windings. The set of windings has an inner perimeter. The set of windings includes a set of interconnects and a set of vias. The set of interconnects and the set of vias are located outside the inner perimeter of the set of windings. In some implementations, the set of windings further includes a set of capture pads. The set of interconnects is coupled to the set of vias through the set of capture pads. In some implementations, the set of windings has an outer perimeter. The set of pads is coupled to the set of interconnects such that the set of pads is at least partially outside the outer perimeter of the set of windings.

公开(公告)号：US20170077574A1

公开(公告)日：2017-03-16

申请号：US15218626

申请日：2016-07-25

Applicant: QUALCOMM Incorporated

Inventor： John Jong-Hoon Lee ,  Young Kyu Song ,  Uei-Ming Jow ,  Sangjo Choi ,  Xiaonan Zhang

IPC: H01P1/207 ,  H01L23/66 ,  H01L21/48 ,  H01L23/60 ,  H01L23/522 ,  H05K1/02 ,  H01L23/00

CPC classification number: H01P1/207 ,  H01L21/4853 ,  H01L23/5222 ,  H01L23/5227 ,  H01L23/552 ,  H01L23/60 ,  H01L23/66 ,  H01L24/16 ,  H01L28/10 ,  H01L28/40 ,  H01L2223/6627 ,  H01L2223/6666 ,  H01L2223/6672 ,  H01L2224/10 ,  H01L2224/16227 ,  H01P1/201 ,  H01P7/06 ,  H01P7/065 ,  H03B5/1817 ,  H05K1/0243

Abstract: A flip-chip employing an integrated cavity filter is disclosed comprising an integrated circuit (IC) chip comprising a semiconductor die and a plurality of conductive bumps. The plurality of conductive bumps is interconnected to at least one metal layer of the semiconductor die to provide a conductive “fence” that defines an interior resonator cavity for providing an integrated cavity filter in the flip-chip. The interior resonator cavity is configured to receive an input RF signal from an input transmission line through an input signal transmission aperture provided in an internal layer in the semiconductor die. The interior resonator cavity resonates the input RF signal to generate the output RF signal comprising a filtered RF signal of the input RF signal, and couples the output RF signal on an output signal transmission line in the flip-chip through an output transmission aperture provided in the aperture layer.

Abstract translation: 公开了一种采用集成腔滤波器的倒装芯片，其包括集成电路（IC）芯片，其包括半导体管芯和多个导电凸块。 多个导电凸块互连到半导体管芯的至少一个金属层，以提供限定用于在倒装芯片中提供集成腔滤波器的内部谐振腔的导电“栅栏”。 内部谐振腔被配置为通过设置在半导体管芯中的内层中的输入信号传输孔从输入传输线接收输入RF信号。 内部谐振器腔谐振输入RF信号以产生包括输入RF信号的滤波RF信号的输出RF信号，并且通过输出传输孔将输出RF信号耦合在倒装芯片中的输出信号传输线上 孔径层。

公开(公告)号：US09583433B2

公开(公告)日：2017-02-28

申请号：US14631391

申请日：2015-02-25

Applicant: QUALCOMM Incorporated

Inventor： Young Kyu Song ,  Hong Bok We ,  Kyu-Pyung Hwang

IPC: H01L29/66 ,  H01L23/522 ,  H01L23/31 ,  H01L23/48 ,  H01L21/56 ,  H01L49/02 ,  H01F27/28 ,  H01F27/29 ,  H01L23/64 ,  H01L23/498 ,  H01L23/00

CPC classification number: H01L23/5227 ,  H01F27/2847 ,  H01F27/292 ,  H01F41/063 ,  H01L21/563 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/481 ,  H01L23/49822 ,  H01L23/5389 ,  H01L23/645 ,  H01L24/13 ,  H01L24/16 ,  H01L28/10 ,  H01L2224/131 ,  H01L2224/16227 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2924/15311 ,  H01L2924/014

Abstract: An integrated device package includes a package substrate, a die coupled to the package substrate, an encapsulation layer encapsulating the die, and at least one sheet of electrically conductive material configured to operate as an inductor. The sheet of electrically conductive material is at least partially encapsulated by the encapsulation layer. The sheet of electrically conductive material is configured to operate as a solenoid inductor. The sheet of electrically conductive material includes a first sheet portion, a second sheet portion coupled to the first sheet portion, where the first sheet portion and the second sheet portion form a first winding of the inductor, a first terminal portion coupled to the first sheet portion, and a second terminal portion coupled to the second sheet portion. The first sheet portion is formed on a first level of the sheet. The second sheet portion is formed on a second level of the sheet.

Abstract translation: 集成器件封装包括封装衬底，耦合到封装衬底的管芯，封装管芯的封装层以及配置成作为电感器工作的至少一片导电材料。 导电材料片材至少部分地被封装层封装。 导电材料片被配置为作为螺线管电感器工作。 导电材料片包括第一片部分，第二片部分，其耦合到第一片部分，第一片部分和第二片部分形成电感器的第一绕组，第一端部分耦合到第一片 部分，以及耦合到第二片部分的第二端子部分。 第一片部分形成在片材的第一层上。 第二片部分形成在片材的第二层上。

公开(公告)号：US09576718B2

公开(公告)日：2017-02-21

申请号：US14746652

申请日：2015-06-22

Applicant: QUALCOMM Incorporated

Inventor： Uei-Ming Jow ,  Young Kyu Song ,  Jong-Hoon Lee ,  Jung Ho Yoon ,  Sangjo Choi ,  Xiaonan Zhang

IPC: H01F27/28 ,  H01F5/00 ,  H01F41/04

CPC classification number: H01F27/2804 ,  H01F17/0006 ,  H01F17/0013 ,  H01F41/041 ,  H01F2027/2809

Abstract: An inductor structure includes a first set of traces corresponding to a first layer of an inductor, a second set of traces corresponding to a second layer of the inductor, and a third set of traces corresponding to a third layer of the inductor that is positioned between the first layer and the second layer. The first set of traces includes a first trace and a second trace that is parallel to the first trace. A dimension of the first trace is different from a corresponding dimension of the second trace. The second set of traces is coupled to the first set of traces. The second set of traces includes a third trace that is coupled to the first trace and to the second trace. The third set of traces is coupled to the first set of traces.

Abstract translation: 电感器结构包括对应于电感器的第一层的第一组迹线，对应于电感器的第二层的第二组迹线，以及对应于电感器的第三层的第三组迹线，其位于 第一层和第二层。 第一组轨迹包括与第一轨迹平行的第一轨迹和第二轨迹。 第一个跟踪的维度与第二个跟踪的相应维度不同。 第二组迹线耦合到第一组迹线。 第二组迹线包括耦合到第一迹线和第二迹线的第三迹线。 第三组迹线耦合到第一组迹线。

公开(公告)号：US09530739B2

公开(公告)日：2016-12-27

申请号：US14609289

申请日：2015-01-29

Applicant: QUALCOMM Incorporated

Inventor： Young Kyu Song ,  Kyu-Pyung Hwang

IPC: H01L23/00 ,  H01L23/538 ,  H01L21/768 ,  H01L25/065 ,  H01L25/00 ,  H01L23/552 ,  H01L23/60 ,  H01L25/10

CPC classification number: H01L23/5384 ,  H01L21/768 ,  H01L23/5386 ,  H01L23/5389 ,  H01L23/552 ,  H01L23/60 ,  H01L24/00 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/92 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/13101 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/92125 ,  H01L2225/1023 ,  H01L2225/1047 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A package on package (PoP) device includes a first package and a second package. The first package includes a first package substrate, a die coupled to the first package substrate, an encapsulation layer located on the first package substrate, and an inter package connection coupled to the first package substrate. The inter package connection is located in the encapsulation layer. The inter package connection includes a first interconnect configured to provide a first electrical path for a reference ground signal, and a second set of interconnects configured to provide at least one second electrical path for at least one second signal. The first interconnect has a length that is at least about twice as long as a width of the first interconnect. The second set of interconnects is configured to at least be partially coupled to the first interconnect by an electric field.

Abstract translation: 包装（PoP）装置包括第一包装和第二包装。 第一封装包括第一封装衬底，耦合到第一封装衬底的管芯，位于第一封装衬底上的封装层以及耦合到第一封装衬底的封装间连接。 封装间连接位于封装层中。 所述间隔间连接包括被配置为提供用于参考接地信号的第一电路径的第一互连和被配置为为至少一个第二信号提供至少一个第二电路径的第二组互连。 第一互连的长度至少是第一互连宽度的两倍。 第二组互连被配置为通过电场至少部分地耦合到第一互连。

公开(公告)号：US09443810B1

公开(公告)日：2016-09-13

申请号：US14853802

申请日：2015-09-14

Applicant: QUALCOMM Incorporated

Inventor： John Jong-Hoon Lee ,  Young Kyu Song ,  Uei-Ming Jow ,  Sangjo Choi ,  Xiaonan Zhang

IPC: H01P1/20 ,  H01P7/06 ,  H01L21/00 ,  H01L27/15 ,  H01L23/66 ,  H01L49/02 ,  H01L23/552 ,  H03B5/18 ,  H01P1/201

CPC classification number: H01P1/207 ,  H01L21/4853 ,  H01L23/5222 ,  H01L23/5227 ,  H01L23/552 ,  H01L23/60 ,  H01L23/66 ,  H01L24/16 ,  H01L28/10 ,  H01L28/40 ,  H01L2223/6627 ,  H01L2223/6666 ,  H01L2223/6672 ,  H01L2224/10 ,  H01L2224/16227 ,  H01P1/201 ,  H01P7/06 ,  H01P7/065 ,  H03B5/1817 ,  H05K1/0243

Abstract: A flip-chip employing an integrated cavity filter is disclosed comprising an integrated circuit (IC) chip comprising a semiconductor die and a plurality of conductive bumps. The plurality of conductive bumps is interconnected to at least one metal layer of the semiconductor die to provide a conductive “fence” that defines an interior resonator cavity for providing an integrated cavity filter in the flip-chip. The interior resonator cavity is configured to receive an input RF signal from an input transmission line through an input signal transmission aperture provided in an internal layer in the semiconductor die. The interior resonator cavity resonates the input RF signal to generate the output RF signal comprising a filtered RF signal of the input RF signal, and couples the output RF signal on an output signal transmission line in the flip-chip through an output transmission aperture provided in the aperture layer.

Abstract translation: 公开了一种采用集成腔滤波器的倒装芯片，其包括集成电路（IC）芯片，其包括半导体管芯和多个导电凸块。 多个导电凸块互连到半导体管芯的至少一个金属层，以提供限定用于在倒装芯片中提供集成腔滤波器的内部谐振腔的导电“栅栏”。 内部谐振腔被配置为通过设置在半导体管芯中的内层中的输入信号传输孔从输入传输线接收输入RF信号。 内部谐振器腔谐振输入RF信号以产生包括输入RF信号的滤波RF信号的输出RF信号，并且通过输出传输孔将输出RF信号耦合在倒装芯片中的输出信号传输线上 孔径层。