公开(公告)号：US20210193674A1

公开(公告)日：2021-06-24

申请号：US16722745

申请日：2019-12-20

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Ramy Nashed Bassely SAID ,  Senaka KANAKAMEDALA ,  Fei ZHOU ,  Raghuveer S. MAKALA ,  Yao-Sheng LEE

IPC: H01L27/11582 ,  H01L21/02

Abstract: A three-dimensional memory device includes a vertically alternating stack of insulating layers and electrically conductive layers located over a top surface of a substrate and memory stack structures extending through the alternating stack. Each of the memory stack structures contains a respective memory film and a respective vertical semiconductor channel, and each of the insulating layers contains a metal-organic framework (MOF) material portion. The MOF material portion has a low dielectric constant, and reduces RC coupling between the electrically conductive layers. An optional airgap may be located within the MOF material portion to further reduce the effective dielectric constant. Optionally, discrete charge storage regions or floating gates may be formed only at the levels of the electrically conductive layers to reduce program disturb and noise in the device.

公开(公告)号：US20210183883A1

公开(公告)日：2021-06-17

申请号：US16710572

申请日：2019-12-11

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Yanli ZHANG ,  Dong-il MOON ,  Raghuveer S. MAKALA ,  Peng ZHANG ,  Wei ZHAO ,  Ashish BARASKAR

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L23/528 ,  H01L23/532 ,  H01L23/522 ,  H01L21/768 ,  H01L21/28 ,  H01L27/11526 ,  H01L27/11519 ,  H01L27/11565 ,  H01L27/11573

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, memory openings vertically extending through the alternating stack, and memory stack structures extending through the alternating stack. Each of the memory stack structures contains a memory film and a vertical semiconductor channel. At least one of the electrically conductive layers contains a first conductive material portion having a respective inner sidewall that contacts a respective one of the memory films at a vertical interface, and a second conductive material portion that has a different composition from the first conductive material portion, and contacting the first electrically conductive material portion. The first conductive material portion has a lower work function than the second conductive material portion.

公开(公告)号：US20200295039A1

公开(公告)日：2020-09-17

申请号：US16886081

申请日：2020-05-28

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Peter RABKIN ,  Raghuveer S. MAKALA ,  Masaaki HIGASHITANI

IPC: H01L27/11582 ,  H01L21/768 ,  H01L27/11556 ,  H01L27/11529 ,  H01L27/1157 ,  H01L27/11573 ,  H01L23/522 ,  H01L23/532 ,  H01L21/02 ,  H01L27/11524 ,  H01L21/28

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers containing molybdenum portions located over a substrate, memory stack structures extending through the alternating stack, and including a memory film and a vertical semiconductor channel, and a backside blocking dielectric layer of a dielectric oxide material including aluminum atoms and at least one of lanthanum or zirconium atoms which directly contacts the molybdenum portions.

公开(公告)号：US20200251443A1

公开(公告)日：2020-08-06

申请号：US16263058

申请日：2019-01-31

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Senaka KANAKAMEDALA ,  Raghuveer S. MAKALA ,  Yao-Sheng LEE ,  Jian CHEN

IPC: H01L23/00 ,  H01L25/18 ,  H01L23/522 ,  H01L23/538 ,  H01L21/822 ,  H01L21/033

Abstract: A first semiconductor die and a second semiconductor die can be bonded in a manner that enhances alignment of bonding pads. Non-uniform deformation of a first wafer including first semiconductor dies can be compensated for by forming a patterned stress-generating film on a backside of the first wafer. Metallic bump portions can be formed on concave surfaces of metallic bonding pads by a selective metal deposition process to reduce gaps between pairs of bonded metallic bonding pads. Pad-to-pad pitch can be adjusted on a semiconductor die to match the pad-to-pad pitch of another semiconductor die employing a tilt-shift operation in a lithographic exposure tool. A chuck configured to provide non-uniform displacement across a wafer can be employed to hold a wafer in a contoured shape for bonding with another wafer in a matching contoured position. Independently height-controlled pins can be employed to hold a wafer in a non-planar configuration.

公开(公告)号：US20190287982A1

公开(公告)日：2019-09-19

申请号：US16020088

申请日：2018-06-27

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Tatsuya HINOUE ,  Tomoyuki OBU ,  Tomohiro UNO ,  Yusuke MUKAE ,  Rahul SHARANGPANI ,  Raghuveer S. MAKALA ,  Fei ZHOU ,  Adarsh RAJASHEKHAR

IPC: H01L27/11556 ,  H01L27/11582 ,  H01L27/11524 ,  H01L27/1157 ,  H01L27/11529 ,  H01L27/11573

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate and memory stack structures extending through the alternating stack. Each of the electrically conductive layers includes a stack of a compositionally graded diffusion barrier and a metal fill material portion, and the compositionally graded diffusion barrier includes a substantially amorphous region contacting the interface between the compositionally graded diffusion barrier and a substantially crystalline region that is spaced from the interface by the amorphous region. The substantially crystalline region effectively blocks atomic diffusion, and the amorphous region induces formation of large grains during deposition of the metal fill material portions.

公开(公告)号：US20180138194A1

公开(公告)日：2018-05-17

申请号：US15496359

申请日：2017-04-25

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Keisuke SHIGEMURA ,  Junichi ARIYOSHI ,  Masanori TSUTSUMI ,  Michiaki SANO ,  Yanli ZHANG ,  Raghuveer S. MAKALA

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L29/423 ,  H01L23/528 ,  H01L23/532 ,  H01L21/28 ,  H01L27/11524 ,  H01L21/768 ,  H01L21/311 ,  H01L27/1157 ,  H01L27/11526 ,  H01L27/11573 ,  H01L27/11519 ,  H01L27/11565

CPC classification number: H01L27/11582 ,  H01L21/28008 ,  H01L21/31111 ,  H01L21/76843 ,  H01L21/76877 ,  H01L23/528 ,  H01L23/53266 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L29/42324 ,  H01L29/4234

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, the alternating stack having a memory array region and a contact region containing stepped surfaces, and memory stack structures having a semiconductor channel and a memory film extending through the memory array region of the alternating stack. The electrically conductive layers include a drain select gate electrode and word lines, where the drain select gate electrode is thicker than each of the word lines.

公开(公告)号：US20160293617A1

公开(公告)日：2016-10-06

申请号：US15177737

申请日：2016-06-09

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Rahul SHARANGPANI ,  Raghuveer S. MAKALA ,  Thomas Jongwan KWON ,  Senaka KANAKAMEDALA ,  George MATAMIS

IPC: H01L27/115 ,  H01L21/285 ,  H01L29/788 ,  H01L21/311 ,  H01L21/3205 ,  H01L29/423 ,  H01L21/28 ,  H01L21/02

CPC classification number: H01L27/11556 ,  G11C16/0408 ,  G11C16/06 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02238 ,  H01L21/28273 ,  H01L21/28556 ,  H01L21/28562 ,  H01L21/28568 ,  H01L21/31111 ,  H01L21/32055 ,  H01L27/11519 ,  H01L27/11524 ,  H01L29/42332 ,  H01L29/7883

Abstract: A method of making a monolithic three dimensional NAND string which contains a semiconductor channel and a plurality of control gate electrodes, includes selectively forming a plurality of discrete charge storage regions using atomic layer deposition. The plurality of discrete charge storage regions includes at least one of a metal or an electrically conductive metal oxide.

Abstract translation: 包括半导体通道和多个控制栅电极的单片三维NAND串的制造方法包括使用原子层沉积选择性地形成多个离散的电荷存储区域。 多个离散电荷存储区域包括金属或导电金属氧化物中的至少一种。

公开(公告)号：US20240349501A1

公开(公告)日：2024-10-17

申请号：US18363486

申请日：2023-08-01

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Rahul SHARANGPANI ,  Raghuveer S. MAKALA ,  Adarsh RAJASHEKHAR ,  Bing ZHOU ,  Senaka KANAKAMEDALA

IPC: H10B43/27 ,  G11C16/04 ,  H10B43/10 ,  H10B43/35

CPC classification number: H10B43/27 ,  G11C16/0483 ,  H10B43/10 ,  H10B43/35

Abstract: A semiconductor structure includes an alternating stack of insulating layers and electrically conductive layers, a memory opening vertically extending through the alternating stack and a memory opening fill structure located in the memory opening. A Group IV-containing material portion is formed by selective deposition on an end portion of the vertical semiconductor channel. Alternatively, a backside semiconductor cap structure can be formed directly on a bottom surface of the vertical semiconductor channel by selective or non-selective deposition of a semiconductor material.

公开(公告)号：US20240349500A1

公开(公告)日：2024-10-17

申请号：US18363460

申请日：2023-08-01

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Bing ZHOU ,  Raghuveer S. MAKALA ,  Senaka KANAKAMEDALA ,  Rahul SHARANGPANI ,  Adarsh RAJASHEKHAR

IPC: H10B43/27 ,  H01L23/00 ,  H01L25/00 ,  H01L25/065 ,  H01L25/18 ,  H10B41/27 ,  H10B41/35 ,  H10B43/35 ,  H10B80/00

CPC classification number: H10B43/27 ,  H01L24/08 ,  H01L24/80 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H10B41/27 ,  H10B41/35 ,  H10B43/35 ,  H10B80/00 ,  H01L2224/08145 ,  H01L2224/80006 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2924/1431 ,  H01L2924/14511

Abstract: A semiconductor structure includes an alternating stack of insulating layers and electrically conductive layers, a memory opening vertically extending through the alternating stack and a memory opening fill structure located in the memory opening. A Group IV-containing material portion is formed by selective deposition on an end portion of the vertical semiconductor channel. Alternatively, a backside semiconductor cap structure can be formed directly on a bottom surface of the vertical semiconductor channel by selective or non-selective deposition of a semiconductor material.

公开(公告)号：US20240332177A1

公开(公告)日：2024-10-03

申请号：US18362706

申请日：2023-07-31

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Ryo NAKAMURA ,  Fei ZHOU ,  Rahul SHARANGPANI ,  Adarsh RAJASHEKHAR ,  Raghuveer S. MAKALA

IPC: H01L23/528 ,  G11C16/04 ,  H01L23/522 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

CPC classification number: H01L23/5283 ,  G11C16/0483 ,  H01L23/5226 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

Abstract: A memory device includes an alternating stack of insulating layers and electrically conductive layers, memory openings vertically extending through the alternating stack, where a smallest unit shape of three nearest neighbor memory openings is a non-equilateral triangle, and memory opening fill structures located in the memory openings, where each of the memory opening fill structures includes a vertical semiconductor channel and a vertical stack of memory elements.