公开(公告)号：US09716048B2

公开(公告)日：2017-07-25

申请号：US14985379

申请日：2015-12-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sundae Kim ,  Yun-Rae Cho ,  Namgyu Baek ,  Seokhyun Lee

IPC: H01L21/66

CPC classification number: H01L22/32 ,  H01L21/76877 ,  H01L21/822 ,  H01L22/14 ,  H01L22/34 ,  H01L23/485 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/10897

Abstract: Provided is a semiconductor device including an interconnection structure provided on a cell region of a substrate to include a first line and a second line sequentially stacked on the substrate, and a defect detection structure provided on a peripheral region of the substrate to include first and second defect detection lines provided at the same levels as those of the first and second lines, respectively.

公开(公告)号：US09364914B2

公开(公告)日：2016-06-14

申请号：US14471327

申请日：2014-08-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seokhyun Lee ,  Jaegwon Jang ,  Chul-Yong Jang

IPC: H01L23/02 ,  B23K3/06 ,  B23K1/00 ,  B23K1/20 ,  H01L23/498 ,  H01L25/10 ,  H01L25/00 ,  H01L21/48 ,  H01L23/31 ,  H01L23/00 ,  H01L25/065

CPC classification number: B23K3/0623 ,  B23K1/0016 ,  B23K1/203 ,  H01L21/4853 ,  H01L23/3128 ,  H01L23/49816 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/92 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/92125 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06568 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/18161 ,  H01L2924/351 ,  H01L2924/37001 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2224/45099

Abstract: Provided are apparatuses configured to attach a solder ball, methods of attaching a solder ball, and methods of fabricating a semiconductor package including the same. An apparatus configured to attach a solder ball includes a chuck configured to receive a package substrate on which solder balls are provided; a shielding mask configured to shield the package substrate and including holes configured to expose the solder balls; and a heater configured to melt the solder balls exposed through the holes.

Abstract translation: 提供了构造成附接焊球的装置，附接焊球的方法，以及制造包括该焊球的半导体封装的方法。 构造成附接焊球的装置包括：卡盘，其配置成接收其上设置有焊球的封装基板; 屏蔽掩模，被配置为屏蔽所述封装基板并且包括被配置为暴露所述焊球的孔; 以及被配置为熔化通过孔暴露的焊球的加热器。

公开(公告)号：US09202716B2

公开(公告)日：2015-12-01

申请号：US13626012

申请日：2012-09-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jin-Woo Park ,  Hogeon Song ,  Seokhyun Lee

IPC: H01L23/34 ,  H01L21/56 ,  H01L23/538 ,  H01L25/065 ,  H01L25/00 ,  H01L23/13 ,  H01L23/12 ,  H01L23/057 ,  H01L23/055 ,  H01L23/24 ,  H01L23/053 ,  H01L23/02 ,  H01L23/04 ,  H01L23/495 ,  H01L23/08 ,  H01L23/492 ,  H01L23/31 ,  H01L23/00

CPC classification number: H01L21/568 ,  H01L21/561 ,  H01L23/02 ,  H01L23/04 ,  H01L23/053 ,  H01L23/055 ,  H01L23/057 ,  H01L23/08 ,  H01L23/12 ,  H01L23/13 ,  H01L23/24 ,  H01L23/3128 ,  H01L23/34 ,  H01L23/4926 ,  H01L23/49575 ,  H01L23/5389 ,  H01L24/13 ,  H01L24/24 ,  H01L24/73 ,  H01L24/82 ,  H01L24/96 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2224/24011 ,  H01L2224/24146 ,  H01L2224/32145 ,  H01L2224/73209 ,  H01L2224/73253 ,  H01L2224/73267 ,  H01L2224/82031 ,  H01L2224/82101 ,  H01L2224/96 ,  H01L2225/06524 ,  H01L2225/06548 ,  H01L2225/06562 ,  H01L2225/06568 ,  H01L2225/06586 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2224/82 ,  H01L2924/014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A fan-out wafer level package may include at least two semiconductor chips; an insulating layer covering portions of a first semiconductor chip; a mold layer covering portions of a second semiconductor chip; a redistribution line pattern in the insulating layer; and/or an external terminal on the insulating layer. The first semiconductor chip may be stacked relative to the second semiconductor chip. The redistribution line pattern may be electrically connected to the at least two semiconductor chips. The external terminal may be electrically connected to the redistribution line pattern. A fan-out wafer level package may include at least three semiconductor chips; an insulating layer covering portions of first semiconductor chips; a mold layer covering portions of a second semiconductor chip; a redistribution line pattern in the insulating layer; and/or an external terminal on the insulating layer. The first semiconductor chips may be stacked relative to the second semiconductor chip.

Abstract translation: 扇出晶片级封装可以包括至少两个半导体芯片; 覆盖第一半导体芯片的部分的绝缘层; 覆盖第二半导体芯片的部分的模具层; 绝缘层中的再分布线图案; 和/或绝缘层上的外部端子。 第一半导体芯片可以相对于第二半导体芯片堆叠。 再分布线图案可以电连接到至少两个半导体芯片。 外部端子可以电连接到再分配线图案。 扇出晶片级封装可以包括至少三个半导体芯片; 覆盖第一半导体芯片的部分的绝缘层; 覆盖第二半导体芯片的部分的模具层; 绝缘层中的再分布线图案; 和/或绝缘层上的外部端子。 第一半导体芯片可以相对于第二半导体芯片堆叠。

公开(公告)号：US20250112193A1

公开(公告)日：2025-04-03

申请号：US18976931

申请日：2024-12-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Inhyung Song ,  Seokhyun Lee ,  Jongyoun Kim

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/538 ,  H01L25/065 ,  H01L25/10

Abstract: A semiconductor package includes a base substrate; a redistribution substrate disposed on the base substrate, and that includes first insulating layers and redistribution pattern layers disposed on the first insulating layers, respectively; a semiconductor chip disposed on the redistribution substrate and electrically connected to the redistribution pattern layers; and a chip structure disposed on the redistribution substrate adjacent to the semiconductor chip and electrically connected to the semiconductor chip through the redistribution pattern layers, wherein the semiconductor chip includes a body that has an active surface that faces the redistribution substrate; first and second contact pads spaced apart from each other below the active surface; a first bump structure and a passive device electrically connected to the first connection pad at a lower level from the first connection pad; and a second bump structure electrically connected to the second connection pad at a lower level from the second connection pad.

公开(公告)号：US12261106B2

公开(公告)日：2025-03-25

申请号：US17535093

申请日：2021-11-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyeonjeong Hwang ,  Kyoung Lim Suk ,  Seokhyun Lee ,  Jaegwon Jang

IPC: H01L23/48 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L25/065 ,  H01L25/10

Abstract: A semiconductor package comprises a first redistribution substrate including first interconnection layers sequentially stacked on each other, a semiconductor chip mounted on the first redistribution substrate, a mold layer disposed on the first redistribution substrate and surrounding the semiconductor chip, a second redistribution substrate disposed on the mold layer and including second interconnection layers sequentially stacked on each other, a connection terminal disposed beside the semiconductor chip to connect the first and second redistribution substrates to each other, and outer terminals disposed on a bottom surface of the first redistribution substrate. Each of the first and second interconnection layers may include an insulating layer and a wire pattern in the insulating layer. The first redistribution substrate may have substantially the same thickness as the second redistribution substrate, and the first interconnection layers may be thinner than the second interconnection layers.

公开(公告)号：US12237250B2

公开(公告)日：2025-02-25

申请号：US17498893

申请日：2021-10-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dongkyu Kim ,  Minjung Kim ,  Kyounglim Suk ,  Seokhyun Lee

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/29 ,  H01L23/538 ,  H01L25/065 ,  H01L25/10

Abstract: A semiconductor package includes a redistribution substrate having first and second surfaces opposing one another, a first semiconductor chip on the first surface of the redistribution substrate, a passive device and a metal post on the second surface of the redistribution substrate and electrically connected to the redistribution pattern, a second encapsulant encapsulating at least side surfaces of the passive device and the metal post, a second insulating layer on a lower surface of the metal post and a lower surface of the second encapsulant, and having an opening exposing at least a portion of the lower surface of the metal post, and a connection bump filling the opening of the second insulating layer and in direct contact with the lower surface of the exposed metal post, wherein the metal post has a height greater than a height of each of the redistribution pattern and the redistribution via.

公开(公告)号：US12205914B2

公开(公告)日：2025-01-21

申请号：US17648425

申请日：2022-01-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Inhyung Song ,  Seokhyun Lee ,  Jongyoun Kim

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/538 ,  H01L25/065 ,  H01L25/10

Abstract: A semiconductor package includes a base substrate; a redistribution substrate disposed on the base substrate, and that includes first insulating layers and redistribution pattern layers disposed on the first insulating layers, respectively; a semiconductor chip disposed on the redistribution substrate and electrically connected to the redistribution pattern layers; and a chip structure disposed on the redistribution substrate adjacent to the semiconductor chip and electrically connected to the semiconductor chip through the redistribution pattern layers, wherein the semiconductor chip includes a body that has an active surface that faces the redistribution substrate; first and second contact pads spaced apart from each other below the active surface; a first bump structure and a passive device electrically connected to the first connection pad at a lower level from the first connection pad; and a second bump structure electrically connected to the second connection pad at a lower level from the second connection pad.

公开(公告)号：US12057435B2

公开(公告)日：2024-08-06

申请号：US17723981

申请日：2022-04-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyeonseok Lee ,  Jongyoun Kim ,  Seokhyun Lee

IPC: H01L21/00 ,  H01L23/00 ,  H01L23/498 ,  H01L23/522 ,  H01L23/528 ,  H01L25/065

CPC classification number: H01L25/0655 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/5226 ,  H01L23/5283 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L2224/13008 ,  H01L2224/13017 ,  H01L2224/13019 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/13082 ,  H01L2224/13147 ,  H01L2224/13166 ,  H01L2224/13184 ,  H01L2224/13541 ,  H01L2224/13553 ,  H01L2224/1357 ,  H01L2224/16014 ,  H01L2224/16055 ,  H01L2224/16058 ,  H01L2224/16235 ,  H01L2224/1703 ,  H01L2224/17055 ,  H01L2924/182

Abstract: A semiconductor package includes a redistribution substrate having first and second surfaces, a first semiconductor chip on the first surface, external terminals on the second surface, a second semiconductor chip above the first semiconductor chip, external connection members below the second semiconductor chip, conductive pillars electrically connecting the external connection members to the redistribution substrate. The second semiconductor chip includes a device layer, a wiring layer, and a redistribution layer on a semiconductor substrate. The wiring layer includes intermetallic dielectric layers, wiring lines, and a conductive pad connected to an uppermost wiring line. The redistribution layer includes a first redistribution dielectric layer, a first redistribution pattern, and a second redistribution dielectric layer. A vertical distance between the semiconductor substrate and the conductive pillars is less than that between the first semiconductor chip and the external terminals.

公开(公告)号：US12034949B2

公开(公告)日：2024-07-09

申请号：US17575414

申请日：2022-01-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seokhyun Lee ,  Taesung Kim

IPC: H04N19/159 ,  H04N19/137 ,  H04N19/186 ,  H04N19/423 ,  H04N19/593 ,  H04N19/91

CPC classification number: H04N19/423 ,  H04N19/137 ,  H04N19/159 ,  H04N19/186 ,  H04N19/593 ,  H04N19/91

Abstract: A video decoding apparatus includes a first buffer storing input data received from an entropy decoder, a first motion compensation processor extracting motion compensation reference data based on the input data, and store the motion compensation reference data in a pixel cache, a second buffer, and a controller. The input data comprises one of first data including motion information and second data including intra prediction information. The controller controls the second buffer to store the motion compensation reference data stored in the pixel cache when the input data is the first data, and controls the second buffer to store the second data stored in the first buffer when the input data is the second data.

公开(公告)号：US11942586B2

公开(公告)日：2024-03-26

申请号：US17693704

申请日：2022-03-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dahye Kim ,  Seokhyun Lee ,  Jungho Park

IPC: H01L33/62 ,  H01L23/29 ,  H01L23/31 ,  H01L23/485 ,  H01L23/525 ,  H01L25/075 ,  H01L25/16 ,  H01L27/15 ,  H01L33/48 ,  H01L33/56 ,  H01L25/00

CPC classification number: H01L33/62 ,  H01L33/486 ,  H01L33/56

Abstract: A display module package includes a semiconductor chip, a wiring member disposed on the semiconductor chip, including an insulating layer and a wiring layer, and contacting at least a portion of the semiconductor chip, a light emitting device array disposed on the wiring member and including a plurality of light emitting devices disposed on one surface, wherein the wiring member is between the semiconductor chip and the light emitting device, and a molding member disposed on the wiring member, sealing part of the light emitting device array, and having an opening for exposing the plurality of light emitting devices.