公开(公告)号：US08110869B2

公开(公告)日：2012-02-07

申请号：US11906476

申请日：2007-10-01

申请人： Anup Bhalla

发明人： Anup Bhalla

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L29/7811 ,  H01L29/0619 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/4236 ,  H01L29/456 ,  H01L29/47 ,  H01L29/66734 ,  H01L29/7806 ,  H01L29/7813 ,  H01L29/872 ,  H01L29/8725

摘要： A semiconductor power device supported on a semiconductor substrate of a first conductivity type with a bottom layer functioning as a bottom electrode and an epitaxial layer overlying the bottom layer with a same conductivity type as the bottom layer. The semiconductor power device includes a plurality of FET cells and each cell further includes a body region of a second conductivity type extending from a top surface into the epitaxial layer. The body region encompasses a heavy body dopant region of second conductivity type. An insulated gate is disposed on the top surface of the epitaxial layer, overlapping a first portion of the body region. A barrier control layer is disposed on the top surface of the epitaxial layer next to the body region away from the insulated gate. A conductive layer overlies the top surface of the epitaxial layer covering a second portion of the body region and the heavy body dopant region extending over the barrier control layer forming a Schottky junction diode.

摘要翻译： 一种半导体功率器件，其被支撑在第一导电类型的半导体衬底上，底层用作底部电极，外延层覆盖在与底层相同的导电类型的底层上。 半导体功率器件包括多个FET单元，并且每个单元还包括从顶表面延伸到外延层中的第二导电类型的体区。 身体区域包括第二导电类型的重体掺杂区域。 绝缘栅极设置在外延层的顶表面上，与身体区域的第一部分重叠。 屏障控制层设置在远离绝缘栅极的身体区域旁边的外延层的顶表面上。 覆盖覆盖主体区域的第二部分的外延层的顶表面上的导电层和在形成肖特基结二极管的势垒控制层上延伸的重体掺杂区域。

公开(公告)号：US07994005B2

公开(公告)日：2011-08-09

申请号：US11934040

申请日：2007-11-01

申请人： François Hébert

发明人： François Hébert

IPC分类号： H01L21/336

CPC分类号： H01L29/7813 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/456 ,  H01L29/66734

摘要： High-mobility vertical trench DMOSFETs and methods for manufacturing are disclosed. A source region, a drain region or a channel region of a high-mobility vertical trench DMOSFET may comprise silicon germanium (SiGe) that increases the mobility of the charge carriers in the channel region. In some embodiments the channel region may be strained to increase channel charge carriers mobility.

摘要翻译： 公开了高迁移率垂直沟槽DMOSFET及其制造方法。 高迁移率垂直沟槽DMOSFET的源极区，漏极区或沟道区可以包括增加沟道区中电荷载流子迁移率的硅锗（SiGe）。 在一些实施例中，通道区域可能被应变以增加沟道电荷载流子迁移率。

公开(公告)号：US07977930B2

公开(公告)日：2011-07-12

申请号：US12468770

申请日：2009-05-19

申请人： Yu Cheng Chang

发明人： Yu Cheng Chang

IPC分类号： G05F1/575 ,  G05F1/618

CPC分类号： H02M3/1588 ,  H02M3/157 ,  Y02B70/1466

摘要： A voltage/current control apparatus and method are disclosed. The apparatus includes a low-side field effect transistor (FET) having a source, a gate and a drain, a high-side field effect transistor (FET) having a source, a gate and a drain, a gate driver integrated circuit (IC), a sample and hold circuit, and a comparator configured to produce a trigger signal at the output when a sum of the first and second input signals is equal to a sum of the third and fourth input signals, wherein the trigger signal is configured to trigger a beginning of a new cycle by turning the gate of the high-side FET “on” and the gate of the low-side FET “off”.

摘要翻译： 公开了电压/电流控制装置和方法。 该装置包括具有源极，栅极和漏极的低侧场效应晶体管（FET），具有源极，栅极和漏极的高侧场效应晶体管（FET），栅极驱动器集成电路（IC ），采样保持电路和比较器，被配置为当第一和第二输入信号的和等于第三和第四输入信号的和时在输出端产生触发信号，其中触发信号被配置为 通过使高侧FET的栅极“开”并且低边FET的栅极“关闭”来触发新周期的开始。

公开(公告)号：US07955893B2

公开(公告)日：2011-06-07

申请号：US12023921

申请日：2008-01-31

申请人： Tao Feng ,  François Hébert ,  Ming Sun ,  Yueh-Se Ho

发明人： Tao Feng ,  François Hébert ,  Ming Sun ,  Yueh-Se Ho

IPC分类号： H01L21/00

CPC分类号： H01L29/7827 ,  H01L21/76898 ,  H01L23/481 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/16 ,  H01L24/81 ,  H01L29/0657 ,  H01L29/41741 ,  H01L29/4175 ,  H01L29/45 ,  H01L29/49 ,  H01L29/7802 ,  H01L2224/02371 ,  H01L2224/03464 ,  H01L2224/0347 ,  H01L2224/0401 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/06181 ,  H01L2224/06183 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/81815 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/00

摘要： Power wafer level chip scale package (CSP) and process of manufacture are enclosed. The power wafer level chip scale package includes all source, gate and drain electrodes located on one side of the device, which is convenient for mounting to a printed circuit board (PCB) with solder paste.

摘要翻译： 封装了功率晶圆级芯片级封装（CSP）和制造工艺。 功率晶片级芯片级封装包括位于器件一侧的所有源极，栅极和漏极，便于用焊膏安装到印刷电路板（PCB）。

公开(公告)号：US07952144B2

公开(公告)日：2011-05-31

申请号：US12860777

申请日：2010-08-20

申请人： Yi Su ,  Anup Bhalla ,  Daniel Ng

发明人： Yi Su ,  Anup Bhalla ,  Daniel Ng

IPC分类号： H01L29/66

CPC分类号： H01L29/7813 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/0646 ,  H01L29/0653 ,  H01L29/0696 ,  H01L29/66734 ,  H01L29/7815 ,  H01L2224/0603 ,  H01L2924/13091 ,  H01L2924/00

摘要： A semiconductor device includes a main field effect transistor (FET) and one or more sense FETs, and a common gate pad. The main FET and the one or more sense FETs are formed in a common substrate. The main FET and each of the sense FETs include a source terminal, a gate terminal and a drain terminal. The common gate pad connects the gate terminals of the main FET and the one or more sense FETs. An electrical isolation is disposed between the gate terminals of the main FET and the one or more sense FETs. Embodiments of this invention may be applied to both N-channel and P-channel MOSFET devices.

摘要翻译： 半导体器件包括主场效应晶体管（FET）和一个或多个感测FET以及公共栅极焊盘。 主FET和一个或多个感测FET形成在公共衬底中。 主FET和每个感测FET包括源极端子，栅极端子和漏极端子。 公共栅极焊盘连接主FET和一个或多个感测FET的栅极端子。 在主FET和一个或多个感测FET的栅极端子之间设置电隔离。 本发明的实施例可以应用于N沟道和P沟道MOSFET器件。

公开(公告)号：US07933102B2

公开(公告)日：2011-04-26

申请号：US12454333

申请日：2009-05-15

申请人： Shekar Mallikararjunaswamy

发明人： Shekar Mallikararjunaswamy

IPC分类号： H02H9/00

CPC分类号： H01L27/0262 ,  H01L29/87

摘要： This invention discloses an electronic device formed as an integrated circuit (IC) wherein the electronic device further includes a transient voltage suppressing (TVS) circuit. The TVS circuit includes a triggering Zener diode connected between an emitter and a collector of a bipolar-junction transistor (BJT) wherein the Zener diode having a reverse breakdown voltage BV less than or equal to a BVceo of the BJT where BVceo stands for a collector to emitter breakdown voltage with base left open. The TVS circuit further includes a rectifier connected in parallel to the BJT for triggering a rectified current through the rectifier for further limiting an increase of a reverse blocking voltage. In a preferred embodiment, the triggering Zener diode, the BJT and the rectifier are formed in a semiconductor substrate by implanting and configuring dopant regions of a first and a second conductivity types in a N-well and a P-well whereby the TVS can be formed in parallel as part of the manufacturing processes of the electronic device.

摘要翻译： 本发明公开了一种形成为集成电路（IC）的电子设备，其中电子设备还包括瞬态电压抑制（TVS）电路。 TVS电路包括连接在双极结型晶体管（BJT）的发射极和集电极之间的触发齐纳二极管，其中齐纳二极管的反向击穿电压BV小于或等于BJT的BVceo，其中BVceo代表集电极 到发射极击穿电压，基极左开。 TVS电路还包括与BJT并联连接的整流器，用于触发整流器的整流电流，用于进一步限制反向阻断电压的增加。 在优选实施例中，触发齐纳二极管，BJT和整流器通过在N阱和P阱中注入和配置第一和第二导电类型的掺杂区而形成在半导体衬底中，由此TVS可以 作为电子设备的制造过程的一部分并行形成。

公开(公告)号：US07851856B2

公开(公告)日：2010-12-14

申请号：US12345467

申请日：2008-12-29

申请人： François Hébert

发明人： François Hébert

IPC分类号： H01L29/76 ,  H01L29/94

CPC分类号： H01L29/7835 ,  H01L24/05 ,  H01L24/45 ,  H01L29/0692 ,  H01L29/402 ,  H01L29/4175 ,  H01L29/41758 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/456 ,  H01L29/781 ,  H01L2224/04042 ,  H01L2224/05093 ,  H01L2224/05094 ,  H01L2224/05556 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/05042 ,  H01L2924/1306 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2224/48 ,  H01L2924/00

摘要： A semiconductor package may comprise a semiconductor substrate, a MOSFET device having a plurality cells formed on the substrate, and a source region common to all cells disposed on a bottom of the substrate. Each cell comprises a drain region on a top of the semiconductor device, a gate to control a flow of electrical current between the source and drain regions, a source contact proximate the gate; and an electrical connection between the source contact and source region. At least one drain connection is electrically coupled to the drain region. Source, drain and gate pads are electrically connected to the source region, drain region and gates of the devices. The drain, source and gate pads are formed on one surface of the semiconductor package. The cells are distributed across the substrate, whereby the electrical connections between the source contact of each device and the source region are distributed across the substrate.

摘要翻译： 半导体封装可以包括半导体衬底，具有形成在衬底上的多个单元的MOSFET器件和设置在衬底的底部上的所有单元共用的源极区域。 每个单元包括在半导体器件的顶部上的漏极区域，用于控制源极和漏极区域之间的电流流动的栅极，靠近栅极的源极接触; 以及源极接触和源极区域之间的电连接。 至少一个漏极连接电连接到漏极区域。 源极，漏极和栅极焊盘电连接到器件的源极区域，漏极区域和栅极。 漏极，源极和栅极焊盘形成在半导体封装的一个表面上。 电池分布在衬底上，由此每个器件的源极接触和源极区之间的电连接分布在衬底上。

公开(公告)号：US07829989B2

公开(公告)日：2010-11-09

申请号：US11318300

申请日：2005-12-22

申请人： Ming Sun ,  Yueh Se Ho

发明人： Ming Sun ,  Yueh Se Ho

IPC分类号： H01L23/02

CPC分类号： H01L23/5389 ,  H01L23/3677 ,  H01L23/49816 ,  H01L23/49844 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/10253 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/30107 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： An electronic package for containing at least a top packaging module vertically stacked on a bottom packaging module. Each of the packaging modules includes a semiconductor chip packaged and connected by via connectors and connectors disposed on a laminated board fabricated with a standard printed-circuit board process wherein the top and bottom packaging module further configured as a surface mountable modules for conveniently stacking and mounting to prearranged electrical contacts without using a leadframe. At least one of the top and bottom packaging modules is a multi-chip module (MCM) containing at least two semiconductor chips. At least one of the top and bottom packaging modules includes a ball grid array (BGA) for surface mounting onto the prearranged electrical contacts. At least one of the top and bottom packaging modules includes a plurality of solder bumps on one of the semiconductor chips for surface mounting onto the prearranged electrical contacts. The laminated board of the bottom packaging modules further has a thermal expansion coefficient substantially the same as a printed circuit board (PCB) whereby a surface mount onto the PCB is less impacted by a temperature change.

摘要翻译： 一种用于至少包含垂直堆叠在底部包装模块上的顶部包装模块的电子包装。 每个封装模块包括通过通孔连接器和连接器连接的半导体芯片，该连接器和连接器设置在用标准印刷电路板工艺制造的层压板上，其中顶部和底部封装模块还被配置为用于方便地堆叠和安装的表面可安装模块 以预先布置的电触点，而不使用引线框架。 顶部和底部封装模块中的至少一个是包含至少两个半导体芯片的多芯片模块（MCM）。 顶部和底部封装模块中的至少一个包括用于表面安装到预先布置的电触点上的球栅阵列（BGA）。 顶部和底部封装模块中的至少一个包括在半导体芯片之一上的多个焊料凸块，用于表面安装到预先布置的电触点上。 底部包装模块的层压板还具有与印刷电路板（PCB）基本相同的热膨胀系数，由此PCB上的表面安装件较少受到温度变化的影响。

公开(公告)号：US07795108B2

公开(公告)日：2010-09-14

申请号：US12399632

申请日：2009-03-06

申请人： Tiesheng Li ,  Yu Wang ,  Yingying Lou ,  Anup Bhalla

发明人： Tiesheng Li ,  Yu Wang ,  Yingying Lou ,  Anup Bhalla

IPC分类号： H01L21/76

CPC分类号： H01L22/34 ,  H01L22/12 ,  H01L22/14 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for determining the depth etch, a method of forming a shielded gate trench (SGT) structure and a semiconductor device wafer are disclosed. A material layer is formed over part of a substrate having a trench. The material fills the trench. A resist mask is placed over a test portion of the material layer thereby defining a test structure that lies underneath the resist mask. The resist mask does not cover the trench. The material is isotropically etched and a signal related to a resistance change of the test structure is measured. A lateral undercut DL of the test structure is determined from the signal and an etch depth DT is determined from DL. The wafer may comprise one or more test structures forming a bridge circuit; one or more metal contacts that electrically connect the test structures through contact holes: and resist layer including over the test structures.

摘要翻译： 公开了一种用于确定深度蚀刻的方法，形成屏蔽栅沟槽（SGT）结构的方法和半导体器件晶片。 在具有沟槽的衬底的一部分上形成材料层。 材料填充沟槽。 将抗蚀剂掩模放置在材料层的测试部分上，从而限定位于抗蚀剂掩模下方的测试结构。 抗蚀剂掩模不覆盖沟槽。 该材料被各向同性地蚀刻并且测量与测试结构的电阻变化相关的信号。 从信号确定测试结构的横向底切DL，并且从DL确定蚀刻深度DT。 晶片可以包括形成桥接电路的一个或多个测试结构; 通过接触孔将测试结构电连接的一个或多个金属触点和包括在测试结构上的抗蚀剂层。

公开(公告)号：US07764105B2

公开(公告)日：2010-07-27

申请号：US12154948

申请日：2008-05-27

申请人： Anup Bhalla ,  Sik K. Lui

发明人： Anup Bhalla ,  Sik K. Lui

IPC分类号： H03K5/08

CPC分类号： H01L27/088 ,  H01L27/0629 ,  H01L29/7803 ,  H01L29/7813 ,  H01L2223/6644 ,  H01L2224/16145 ,  H01L2224/45144 ,  H01L2224/48247 ,  H03K17/165 ,  H01L2924/00

摘要： This invention discloses a new MOSFET device. The MOSFET device has an improved operation characteristic achieved by connecting a shunt FET of low impedance to the MOSFET device. The shunt FET is to shunt a transient current therethrough. The shunt FET is employed for preventing an inadvertent turning on of the MOSFET device. The inadvertent turning on of the MOSFET may occur when a large voltage transient occurs at the drain of the MOSFET device. By connecting the gate of the shunt FET to the drain of the MOSFET device, a low impedance path is provided at the right point of time during the circuit operation to shunt the current without requiring any external circuitry.

摘要翻译： 本发明公开了一种新的MOSFET器件。 MOSFET器件具有通过将低阻抗的并联FET连接到MOSFET器件而实现的改进的操作特性。 并联FET分流瞬态电流。 分流FET用于防止MOSFET器件无意中导通。 当在MOSFET器件的漏极处发生大的电压瞬变时，可能会发生MOSFET的无意开启。 通过将分流FET的栅极连接到MOSFET器件的漏极，在电路操作期间在正确的时间点提供低阻抗路径，以分流电流而不需要任何外部电路。