公开(公告)号：US09135010B2

公开(公告)日：2015-09-15

申请号：US13750345

申请日：2013-01-25

Applicant: Rambus Inc.

Inventor： William C. Moyer ,  Jeffrey W. Scott

IPC: G06F9/38 ,  G06F9/30 ,  G06F11/10

CPC classification number: G06F9/3875 ,  G06F9/3004 ,  G06F9/30181 ,  G06F9/30189 ,  G06F9/38 ,  G06F9/3861 ,  G06F9/3867 ,  G06F11/1004 ,  G06F11/1008 ,  G06F11/1076

Abstract: Systems and methods are disclosed for processing data. In accordance with one implementation, a processor may include an arithmetic logic unit (ALU). The processor may also include pipeline circuitry to, in a non-error correction code (ECC) operating mode, execute a sequence of single-cycle instructions in the ALU in a first execution stage, and in an ECC operating mode, execute the same sequence of single-cycle instructions in the ALU in a second execution stage instead of the first execution stage. Further, the processor may include mode control signaling to configure the pipeline circuitry between the non-ECC and ECC operating modes.

Abstract translation: 公开了用于处理数据的系统和方法。 根据一个实现，处理器可以包括算术逻辑单元（ALU）。 处理器还可以包括流水线电路，以非纠错码（ECC）操作模式，在第一执行阶段中在ALU中执行一个单周期指令序列，并且在ECC操作模式中，执行相同的序列 在第二执行阶段而不是第一执行阶段的ALU中的单循环指令。 此外，处理器可以包括模式控制信令以在非ECC和ECC操作模式之间配置流水线电路。

公开(公告)号：US09129712B2

公开(公告)日：2015-09-08

申请号：US14150659

申请日：2014-01-08

Applicant: RAMBUS INC.

Inventor： Adrian E. Ong ,  Fan Ho

IPC: G11C29/00 ,  G11C29/48 ,  G11C29/44

CPC classification number: G11C29/76 ,  G11C11/401 ,  G11C11/4085 ,  G11C29/027 ,  G11C29/04 ,  G11C29/12 ,  G11C29/4401 ,  G11C29/48 ,  G11C29/78 ,  G11C29/789 ,  G11C29/802 ,  G11C2229/743

Abstract: A controller including a non-volatile memory to store a repair address, and a memory control unit operatively coupled with the non-volatile memory. The memory control unit comprising a memory test function configured to detect a malfunctioning address of primary data storage elements within a memory device. The memory device being another semiconductor device separate from the controller. The memory test function configured to store the repair address in the non-volatile memory, the repair address indicating the malfunctioning address of the primary data storage element.

Abstract translation: 一种包括用于存储修复地址的非易失性存储器的控制器，以及与非易失性存储器可操作地耦合的存储器控​​制单元。 存储器控制单元包括存储器测试功能，其被配置为检测存储器设备内主要数据存储元件的故障地址。 存储器件是与控制器分开的另一个半导体器件。 所述存储器测试功能被配置为将所述修复地址存储在所述非易失性存储器中，所述修复地址指示所述主数据存储元件的故障地址。

公开(公告)号：US20150248936A1

公开(公告)日：2015-09-03

申请号：US14621171

申请日：2015-02-12

Applicant: Rambus Inc.

Inventor： Scott C. Best ,  Brent Steven Haukness

IPC: G11C15/04

CPC classification number: G11C15/046 ,  G11C13/0002

Abstract: A ternary content-addressable memory (TCAM) array of cells features reduced area and improved matching functionality. 1T-3R and 2T-3R embodiments are disclosed as illustrative. A row or block of TCAM memory cells may include a serial string interconnecting the cells so as to provide reduced power consumption during matching operations. In other aspects, Pre-charge/Discharge logic configurations are described utilizing complementary resistive ram (cRRAM) storage for input data to form improved programmable logic circuits.

Abstract translation: 三元内容可寻址存储器（TCAM）单元阵列具有减少的面积和改进的匹配功能。 公开了1T-3R和2T-3R实施例作为说明。 TCAM存储器单元的行或块可以包括互连单元的串行串，以便在匹配操作期间提供降低的功耗。 在其他方面，使用用于输入数据的互补电阻RAM（cRRAM）存储来描述预充电/放电逻辑配置，以形成改进的可编程逻辑电路。

公开(公告)号：US09124390B2

公开(公告)日：2015-09-01

申请号：US13949101

申请日：2013-07-23

Applicant: RAMBUS INC.

Inventor： Scott C Best ,  Abhijit M Abhyankar ,  Kun-Yung Chang ,  Frank Lambrecht

IPC: G06F1/04 ,  H04L7/00 ,  G11C29/02 ,  G11C29/50 ,  H04L7/033 ,  H04L7/10 ,  H04L25/14

CPC classification number: G06F1/08 ,  G06F1/12 ,  G11C29/02 ,  G11C29/022 ,  G11C29/028 ,  G11C29/50012 ,  H04L7/0004 ,  H04L7/0008 ,  H04L7/0033 ,  H04L7/0091 ,  H04L7/033 ,  H04L7/10 ,  H04L25/14

Abstract: A communication channel includes a first component having a transmitter coupled to a normal signal source, and a second component having a receiver coupled to a normal signal destination. A communication link couples the first and second components. Calibration logic provides for setting an operation value for a parameter of the communication channel, such as by executing an exhaustive calibration sequence at initialization of the link. A tracking circuit, including a monitoring function, tracks drift in the parameter by monitoring a feedback signal that has a characteristic that correlates with drift in the communication channel, and updates, or indicates the need for updating of, the operation value of the parameter in response to the monitoring function.

公开(公告)号：US20150234707A1

公开(公告)日：2015-08-20

申请号：US14692092

申请日：2015-04-21

Applicant: Rambus Inc.

Inventor： Thomas Vogelsang ,  Suresh N. Rajan ,  Ian P. Shaeffer ,  Frederick A. Ware ,  Wayne F. Ellis

IPC: G06F11/10 ,  G11C29/44

CPC classification number: G06F11/1076 ,  G06F11/1048 ,  G06F11/108 ,  G11C11/40 ,  G11C29/24 ,  G11C29/42 ,  G11C29/44 ,  G11C29/50016

Abstract: A dynamic random access memory (DRAM) array is configured for selective repair and error correction of a subset of the array. Error-correcting code (ECC) is provided to a selected subset of the array to protect a row or partial row of memory cells where one or more weak memory cells are detected. By adding a sense amplifier stripe to the edge of the memory array, the adjacent edge segment of the array is employed to store ECC information associated with the protected subsets of the array. Bit replacement is also applied to defective memory cells. By implementing ECC selectively rather than to the entire array, integrity of the memory array is maintained at minimal cost to the array in terms of area and energy consumption.

Abstract translation: 动态随机存取存储器（DRAM）阵列被配置用于阵列的子集的选择性修复和纠错。 将纠错码（ECC）提供给阵列的选定子集，以保护检测到一个或多个弱存储器单元的行或部分行的存储单元。 通过向存储器阵列的边缘添加感测放大器条纹，阵列的相邻边缘段用于存储与阵列的受保护子集相关联的ECC信息。 位更换也适用于有缺陷的存储单元。 通过有选择地执行ECC而不是整个阵列，在面积和能量消耗方面，以阵列的最低成本保持存储器阵列的完整性。

公开(公告)号：US09110828B2

公开(公告)日：2015-08-18

申请号：US14321718

申请日：2014-07-01

Applicant: Rambus Inc.

Inventor： Mark A. Horowitz ,  Craig E. Hampel ,  Alfredo Moncayo ,  Kevin S. Donnelly ,  Jared L. Zerbe

IPC: G06F13/10 ,  G06F13/40 ,  G06F13/42 ,  G11C5/04 ,  G11C5/06 ,  G11C7/10 ,  H03K19/003 ,  H03K19/0185 ,  G11C19/00 ,  G11C7/22

CPC classification number: G06F13/4291 ,  G06F3/061 ,  G06F3/0611 ,  G06F3/0619 ,  G06F3/0658 ,  G06F3/0661 ,  G06F3/0679 ,  G06F3/0688 ,  G06F12/0246 ,  G06F12/1081 ,  G06F13/102 ,  G06F13/1689 ,  G06F13/364 ,  G06F13/4072 ,  G06F13/4086 ,  G06F13/4234 ,  G06F13/4243 ,  G06F2206/1014 ,  G06F2212/7201 ,  G11C5/04 ,  G11C5/063 ,  G11C7/1048 ,  G11C7/1072 ,  G11C7/22 ,  G11C7/222 ,  G11C16/32 ,  G11C19/00 ,  H03K19/00384 ,  H03K19/018585

Abstract: An integrated circuit device includes a transmitter circuit including an output driver. The integrated circuit device includes a first register to store a value representative of a drive strength setting associated with the transmitter circuit such that the output driver outputs data in accordance with the drive strength setting. The integrated circuit device also includes a second register to store a value representative of an equalization setting associated with the transmitter circuit such that the output driver outputs data in accordance with the equalization setting. The integrated circuit device further includes a third register to store a value representative of a slew rate setting associated with the transmitter circuit such that the output driver outputs data in accordance with the slew rate setting.

Abstract translation: 集成电路装置包括具有输出驱动器的发送器电路。 集成电路装置包括第一寄存器，用于存储表示与发送器电路相关联的驱动强度设置的值，使得输出驱动器根据驱动强度设置输出数据。 集成电路装置还包括第二寄存器，用于存储代表与发送器电路相关联的均衡设置的值，使得输出驱动器根据均衡设置输出数据。 集成电路装置还包括第三寄存器，用于存储表示与发送器电路相关联的转换速率设置的值，使得输出驱动器根据转换速率设置输出数据。

公开(公告)号：US09106399B2

公开(公告)日：2015-08-11

申请号：US14321723

申请日：2014-07-01

Applicant: Rambus Inc.

Inventor： Hae-Chang Lee ,  Jared L. Zerbe ,  Carl William Werner

IPC: H04L7/033 ,  H03L7/081 ,  H03L7/091 ,  H04L7/00

CPC classification number: H04L7/0278 ,  H03L7/0814 ,  H03L7/0816 ,  H03L7/0818 ,  H03L7/091 ,  H03L2207/50 ,  H04L7/0008 ,  H04L7/0016 ,  H04L7/0079 ,  H04L7/0087 ,  H04L7/033 ,  H04L7/0337 ,  H04L7/0338

Abstract: A circuit for performing clock recovery according to a received digital signal 30. The circuit includes at least an edge sampler 105 and a data sampler 145 for sampling the digital signal, and a clock signal supply circuit. The clock signal supply circuit provides edge clock 25 and data clock 20 signals offset in phase from one another to the respective clock inputs of the edge sampler 105 and the data sampler 145. The clock signal supply circuit is operable to selectively vary a phase offset between the edge and data clock signals.

Abstract translation: 用于根据接收到的数字信号30执行时钟恢复的电路。该电路至少包括用于对数字信号进行采样的边缘采样器105和数据采样器145以及时钟信号提供电路。 时钟信号供应电路提供边缘时钟25和数据时钟20信号，其相位偏移到边缘采样器105和数据采样器145的相应时钟输入。时钟信号供应电路可操作以选择性地改变相位偏移 边沿和数据时钟信号。

公开(公告)号：US20150207651A1

公开(公告)日：2015-07-23

申请号：US14448006

申请日：2014-07-31

Applicant: Rambus Inc.

Inventor： Jaeha Kim ,  Haechang Lee ,  Jung-Hoon Chun ,  Jared Zerbe

IPC: H04L25/03 ,  H04B1/12

CPC classification number: H04L25/03343 ,  H04B1/126 ,  H04L5/04 ,  H04L2025/03356 ,  H04L2025/03477 ,  H04L2025/03802

Abstract: A signaling system supports main and auxiliary communication channels between integrated circuits in the same direction over a single link. An equalizing transmitter applies appropriate filter coefficients to minimize the impact of intersymbol interference when transmitting the main data over a communication channel. The transmitter modulates at least one of the filter coefficients with the auxiliary data to induce apparent ISI in the transmitted signal. A main receiver ignores the apparent ISI to recover the main data, while an auxiliary receiver detects and demodulates the apparent ISI to recover the auxiliary data. The auxiliary data may be encoded using spread-spectrum techniques to reduce the impact of the auxiliary data on the main data.

Abstract translation: 信号系统通过单个链路在相同方向上支持集成电路之间的主要和辅助通信信道。 均衡发射机在通过通信信道发送主数据时，应用适当的滤波器系数来最小化符号间干扰的影响。 发射机利用辅助数据调制至少一个滤波器系数，以在发射信号中引起明显的ISI。 主接收机忽略明显的ISI以恢复主数据，而辅助接收机检测并解调明显的ISI以恢复辅助数据。 可以使用扩频技术对辅助数据进行编码，以减少辅助数据对主数据的影响。

公开(公告)号：US09083280B2

公开(公告)日：2015-07-14

申请号：US14452187

申请日：2014-08-05

Applicant: Rambus Inc.

Inventor： Brian Leibowitz ,  Hae-Chang Lee ,  Farshid Aryanfar ,  Kun-Yung Chang ,  Jie Shen

IPC: H03D13/00 ,  H03L7/08 ,  H03L7/081 ,  H03L7/085

CPC classification number: H03D13/00 ,  H03L7/08 ,  H03L7/0814 ,  H03L7/0816 ,  H03L7/085

Abstract: A phase detection circuit can include two phase detectors that each generate a non-zero output in response to input signals being aligned in phase. The input signals are based on two periodic signals. The phase detection circuit subtracts the output signal of one phase detector from the output signal of the other phase detector to generate a signal having a zero value when the periodic signals are in phase. Alternatively, a phase detector generates a phase comparison signal indicative of a phase difference between periodic signals. The phase comparison signal has a non-zero value in response to input signals to the phase detector being aligned in phase. The input signals are based on the periodic signals. An output circuit receives the phase comparison signal and generates an output having a zero value in response to the periodic signals being aligned in phase.

Abstract translation: 相位检测电路可以包括两个相位检测器，每个相位检测器响应于相位对齐的输入信号而产生非零输出。 输入信号基于两个周期信号。 相位检测电路从另一相位检测器的输出信号中减去一相位检测器的输出信号，当周期信号同相时产生具有零值的信号。 或者，相位检测器产生指示周期信号之间的相位差的相位比较信号。 相位比较信号响应于相位检测器的相位输入信号具有非零值。 输入信号基于周期信号。 输出电路接收相位比较信号，并响应于同相对齐的周期信号产生具有零值的输出。

公开(公告)号：US20150178243A1

公开(公告)日：2015-06-25

申请号：US14539740

申请日：2014-11-12

Applicant: Rambus Inc.

Inventor： Keith LOWERY ,  Vlad FRUCHTER

IPC: G06F15/173 ,  H04L29/08

CPC classification number: G06F15/17331 ,  G06F3/0619 ,  G06F12/0653 ,  G06F12/0692 ,  G06F13/16 ,  H04L67/1097 ,  H04L67/2842

Abstract: A method of processing memory instructions including receiving a memory related command from a client system in communication with a memory appliance via a communication protocol, wherein the memory appliance comprises a processor, a memory unit controller and a plurality of memory devices coupled to said memory unit controller. The memory related command is translated by the processor into a plurality of commands that are formatted to perform prescribed data manipulation operations on data of the plurality of memory devices stored in data structures. The plurality of primitive commands is executed on data stored in the memory devices to produce a result, wherein the executing is performed by the memory unit controller. A direct memory transfer of the result is established over the communication protocol to a network.

Abstract translation: 一种处理存储器指令的方法，包括经由通信协议从与存储设备通信的客户端系统接收与存储器有关的命令，其中所述存储设备包括处理器，存储器单元控制器和耦合到所述存储器单元的多个存储器设备 控制器。 存储器相关命令由处理器转换成多个命令，其被格式化为对存储在数据结构中的多个存储器件的数据执行规定的数据操作操作。 对存储在存储器装置中的数据执行多个原语命令以产生结果，其中执行由存储器单元控制器执行。 通过通信协议建立对网络的直接存储器传输。