公开(公告)号：US08836073B1

公开(公告)日：2014-09-16

申请号：US13959994

申请日：2013-08-06

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Deepak Sekar ,  Brian Cronquist

IPC: H01L21/44 ,  H01L21/48 ,  H01L21/50 ,  H01L23/48 ,  H01L27/06 ,  H01L23/544 ,  H01L27/088 ,  H01L29/66

CPC classification number: H01L23/481 ,  H01L21/743 ,  H01L23/34 ,  H01L23/50 ,  H01L23/544 ,  H01L27/0207 ,  H01L27/0623 ,  H01L27/0688 ,  H01L27/088 ,  H01L27/0886 ,  H01L27/10802 ,  H01L27/10894 ,  H01L27/10897 ,  H01L27/11526 ,  H01L27/11551 ,  H01L27/11573 ,  H01L27/11578 ,  H01L27/11807 ,  H01L27/2436 ,  H01L27/249 ,  H01L29/1066 ,  H01L29/66272 ,  H01L29/66704 ,  H01L29/66825 ,  H01L29/66901 ,  H01L29/732 ,  H01L29/7841 ,  H01L29/808 ,  H01L2224/16225 ,  H01L2224/73253 ,  H01L2924/12032 ,  H01L2924/1305 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/1461 ,  H01L2924/16152 ,  H01L2924/00

Abstract: An Integrated Circuit device including: a first layer of first transistors; a first metal layer overlaying the first transistors and providing at least one connection to the first transistors; a second metal layer overlaying the first metal layer; and a second layer of second transistors overlaying the second metal layer, where the second metal layer is connected to provide power to at least one of the second transistors.

Abstract translation: 一种集成电路装置，包括：第一层第一晶体管; 覆盖所述第一晶体管并且提供至少一个到所述第一晶体管的连接的第一金属层; 覆盖所述第一金属层的第二金属层; 以及覆盖所述第二金属层的第二层第二晶体管，其中所述第二金属层被连接以向所述第二晶体管中的至少一个提供功率。

公开(公告)号：US08754533B2

公开(公告)日：2014-06-17

申请号：US12949617

申请日：2010-11-18

Applicant: Zvi Or-Bach ,  Brian Cronquist ,  Israel Beinglass ,  Jan Lodewijk de Jong ,  Deepak C. Sekar

Inventor： Zvi Or-Bach ,  Brian Cronquist ,  Israel Beinglass ,  Jan Lodewijk de Jong ,  Deepak C. Sekar

IPC: H01L29/40 ,  H01L23/544 ,  H01L27/02 ,  H01L27/115 ,  H01L27/12 ,  H01L29/66 ,  H01L21/822 ,  H01L27/108 ,  H01L27/112 ,  H01L27/11 ,  H01L27/105 ,  H01L27/06 ,  H01L27/118 ,  H01L21/762 ,  H01L21/84 ,  H01L23/48 ,  H01L29/78

CPC classification number: H01L21/8221 ,  H01L21/76254 ,  H01L21/84 ,  H01L23/481 ,  H01L23/544 ,  H01L27/0207 ,  H01L27/0688 ,  H01L27/105 ,  H01L27/10876 ,  H01L27/10879 ,  H01L27/10894 ,  H01L27/10897 ,  H01L27/11 ,  H01L27/1108 ,  H01L27/112 ,  H01L27/11521 ,  H01L27/11551 ,  H01L27/11578 ,  H01L27/11807 ,  H01L27/11898 ,  H01L27/1203 ,  H01L29/66795 ,  H01L29/78 ,  H01L2223/54426 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2924/00011 ,  H01L2924/01322 ,  H01L2924/10253 ,  H01L2924/12032 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2224/80001 ,  H01L2924/00012

Abstract: A semiconductor device includes a first mono-crystallized layer including first transistors, and a first metal layer forming at least a portion of connections between the first transistors; and a second layer including second transistors, the second transistors including mono-crystalline material, the second layer overlying the first metal layer, wherein the first metal layer includes aluminum or copper, and wherein the second layer is less than one micron in thickness and includes logic cells.

Abstract translation: 半导体器件包括包括第一晶体管的第一单结晶层和形成第一晶体管之间的连接的至少一部分的第一金属层; 以及包括第二晶体管的第二层，所述第二晶体管包括单晶材料，所述第二层覆盖所述第一金属层，其中所述第一金属层包括铝或铜，并且其中所述第二层的厚度小于1微米，并且包括 逻辑单元。

公开(公告)号：US08686428B1

公开(公告)日：2014-04-01

申请号：US13678588

申请日：2012-11-16

Applicant: Monolithic 3D Inc.

Inventor： Deepak Sekar ,  Zvi Or-Bach ,  Brian Cronquist

IPC: H01L21/70 ,  H01L21/822

CPC classification number: H01L21/84 ,  H01L21/743 ,  H01L21/76898 ,  H01L21/8221 ,  H01L21/845 ,  H01L27/0688 ,  H01L27/1203 ,  H01L27/1211

Abstract: A device with an external surface, the device including: a substrate including first mono-crystal transistors; a second layer including second mono-crystal transistors, the second mono-crystal transistors overlaying the first mono-crystal transistors; and a plurality of thermal conduction paths from a plurality of the second layer locations to the external surface, wherein at least one of the thermal conduction paths includes an electrically nonconductive contact.

Abstract translation: 一种具有外表面的器件，该器件包括：包括第一单晶晶体管的衬底; 包括第二单晶晶体管的第二层，覆盖第一单晶晶体管的第二单晶晶体管; 以及从多个第二层位置到外表面的多个热传导路径，其中至少一个导热路径包括非导电接触。

公开(公告)号：US08674470B1

公开(公告)日：2014-03-18

申请号：US13726091

申请日：2012-12-22

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Brian Cronquist

IPC: H01L21/00

CPC classification number: H01L25/0657 ,  H01L21/743 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/485 ,  H01L23/522 ,  H01L24/25 ,  H01L25/50 ,  H01L27/0688 ,  H01L27/088 ,  H01L27/092 ,  H01L29/4236 ,  H01L29/66621 ,  H01L29/78 ,  H01L2224/24146 ,  H01L2225/06544 ,  H01L2225/06589 ,  H01L2924/0002 ,  H01L2924/01104 ,  H01L2924/12032 ,  H01L2924/12042 ,  H01L2924/13091 ,  H01L2924/2064 ,  H01L2924/351 ,  H01L2924/00

Abstract: An Integrated Circuit device, including: a base wafer including single crystal, the base wafer including a plurality of first transistors; at least one metal layer providing interconnection between the plurality of first transistors; a second layer of less than 2 micron thickness, the second layer including a plurality of second single crystal transistors, the second layer overlying the at least one metal layer; and at least one conductive layer underneath the second layer, the at least one conductive layer is constructed to provide a back-bias to a portion of the plurality of second single crystal transistors.

Abstract translation: 一种集成电路器件，包括：包括单晶的基底晶片，所述基底晶片包括多个第一晶体管; 提供所述多个第一晶体管之间的互连的至少一个金属层; 第二层小于2微米厚，第二层包括多个第二单晶晶体管，第二层覆盖至少一个金属层; 以及在所述第二层下面的至少一个导电层，所述至少一个导电层被构造成向所述多个第二单晶晶体管的一部分提供反偏压。

公开(公告)号：US08541819B1

公开(公告)日：2013-09-24

申请号：US12963659

申请日：2010-12-09

Applicant: Zvi Or-Bach ,  Brian Cronquist ,  Israel Beinglass ,  Jan Lodewijk de Jong ,  Deepak C. Sekar

Inventor： Zvi Or-Bach ,  Brian Cronquist ,  Israel Beinglass ,  Jan Lodewijk de Jong ,  Deepak C. Sekar

IPC: H01L23/528

CPC classification number: H01L21/8221 ,  H01L21/76254 ,  H01L21/823878 ,  H01L21/84 ,  H01L21/845 ,  H01L24/05 ,  H01L27/0688 ,  H01L27/10802 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11551 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11578 ,  H01L27/1203 ,  H01L27/1211 ,  H01L27/2436 ,  H01L27/249 ,  H01L29/7841 ,  H01L29/785 ,  H01L2224/73253 ,  H01L2924/12032 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/15788 ,  H01L2924/351 ,  H01L2924/00

Abstract: A semiconductor device including: a first mono-crystal layer and a second mono-crystal layer and at least one conductive layer in-between; where the at least one conductive layer includes a first conductive layer overlaying a second conductive layer overlying a third conductive layer, and where the second conductive layer having a predetermined second layer current carrying capacity greater than the current carrying capacity of the first conductive layer, and the second conductive layer current carrying capacity being greater than the current carrying capacity of the third conductive layer.

Abstract translation: 一种半导体器件，包括：第一单晶层和第二单晶层及其中的至少一个导电层; 其中所述至少一个导电层包括覆盖覆盖在第三导电层上的第二导电层的第一导电层，并且其中所述第二导电层具有大于所述第一导电层的载流能力的预定的第二层载流容量，以及 第二导电层电流承载能力大于第三导电层的载流能力。

公开(公告)号：US08427200B2

公开(公告)日：2013-04-23

申请号：US12941073

申请日：2010-11-07

Applicant: Zvi Or-Bach

Inventor： Zvi Or-Bach

IPC: H03K19/096

CPC classification number: H03K19/17748 ,  H01L2224/16145 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2924/14 ,  H01L2924/181 ,  H03K19/17736 ,  H03K19/1778 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A semiconductor device includes a first mono-crystallized semiconductor layer; and a second mono-crystallized semiconductor layer; wherein said first and second mono-crystallized semiconductor layers are overlaying one on top of the other, and wherein said first mono-crystallized semiconductor layer comprise repeating memory structure with sub structures defined by etching.

Abstract translation: 半导体器件包括第一单结晶半导体层; 和第二单结晶半导体层; 其中所述第一和第二单结晶半导体层重叠在另一个之上，并且其中所述第一单结晶半导体层包括具有通过蚀刻定义的子结构的重复存储结构。

公开(公告)号：US08384426B2

公开(公告)日：2013-02-26

申请号：US12423214

申请日：2009-04-14

Applicant: Zvi Or-Bach

Inventor： Zvi Or-Bach

IPC: H03K19/177 ,  H01L23/02

CPC classification number: H03K19/17748 ,  H01L2224/16145 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2924/181 ,  H03K19/17736 ,  H03K19/1778 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A novel Integrated Circuit device including a plurality of antifuse-configurable interconnect circuits, each circuit including: at least two interconnects, and at least one antifuse, wherein the antifuse is adapted to directly connect at least two interconnects. The Integrated Circuit device also includes a plurality of transistors adapted to configure at least one antifuse of the antifuse-configurable interconnect circuits, wherein the transistors are above the antifuse-configurable interconnect circuits.

Abstract translation: 一种新颖的集成电路器件，包括多个反熔丝可配置互连电路，每个电路包括：至少两个互连件和至少一个反熔丝，其中反熔丝适于直接连接至少两个互连。 集成电路器件还包括适于配置反熔丝可配置互连电路的至少一个反熔丝的多个晶体管，其中晶体管位于反熔丝可配置互连电路之上。

公开(公告)号：US08378715B2

公开(公告)日：2013-02-19

申请号：US13593620

申请日：2012-08-24

Applicant: Zvi Or-Bach ,  Ze'ev Wurman

Inventor： Zvi Or-Bach ,  Ze'ev Wurman

IPC: H01L25/00 ,  H03K19/00

CPC classification number: H01L23/544 ,  H01L21/76816 ,  H01L21/76898 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/18 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2225/06541 ,  H01L2225/06562 ,  H01L2225/06565 ,  H01L2225/06568 ,  H01L2225/06593 ,  H01L2924/1305 ,  H01L2924/1431 ,  H01L2924/1433 ,  H01L2924/1434 ,  H01L2924/1435 ,  H01L2924/1436 ,  H01L2924/15311 ,  H01L2924/3011 ,  H01L2924/3511 ,  H01L2924/37001 ,  H01L2924/00 ,  H01L2924/00014

Abstract: A method to construct first and second configurable systems including: providing a first configurable system including a first die and a second die, where the first die is diced from a first wafer and the second die is diced from a second wafer and the first die is connected to the second die using at least one through-silicon-via (TSV); providing a second configurable system including a third die and a fourth die, where the third die is diced from a third wafer and the fourth die is diced from a fourth wafer and the third die is connected to the fourth die using at least one through-silicon-via (TSV); where processing the first wafer and the third wafer utilizes a majority of masks that are substantially same; and where the first die is larger than the third die.

Abstract translation: 一种构建第一和第二可配置系统的方法，包括：提供包括第一管芯和第二管芯的第一可配置系统，其中第一管芯从第一晶片切割，第二管芯从第二晶片切割，第一管芯为 使用至少一个穿硅通孔（TSV）连接到第二管芯; 提供包括第三管芯和第四管芯的第二可配置系统，其中第三管芯从第三晶片切割，并且第四管芯从第四晶片切割，并且第三管芯使用至少一个通孔连接到第四管芯， 硅通孔（TSV）; 其中处理第一晶片和第三晶片利用大体相同的掩模; 并且其中第一管芯大于第三管芯。

公开(公告)号：US08373439B2

公开(公告)日：2013-02-12

申请号：US12941075

申请日：2010-11-07

Applicant: Zvi Or-Bach

Inventor： Zvi Or-Bach

IPC: H03K19/173

CPC classification number: H03K19/17748 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2924/14 ,  H01L2924/15311 ,  H03K19/17736 ,  H03K19/1778 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A wafer includes a group of tiles of programmable logic formed thereon, wherein each tile comprises a micro control unit (MCU) communicating with adjacent MCUs, and wherein each MCU is controlled in a predetermined order of priority by adjacent MCUs; and dice lines on the wafer to separate the group into one or more end-devices.

Abstract translation: 晶片包括在其上形成的一组可编程逻辑块，其中每个瓦片包括与相邻MCU通信的微控制单元（MCU），并且其中每个MCU由相邻MCU以预定的优先级顺序控制; 和晶片上的骰子线将组分离成一个或多个终端装置。

公开(公告)号：US20130020707A1

公开(公告)日：2013-01-24

申请号：US13623756

申请日：2012-09-20

Applicant: Zvi Or-Bach ,  Deepak Sekar ,  Brian Cronquist ,  Ze'ev Wurman

Inventor： Zvi Or-Bach ,  Deepak Sekar ,  Brian Cronquist ,  Ze'ev Wurman

IPC: H01L23/48

CPC classification number: B82Y10/00 ,  G11C11/41 ,  G11C16/0408 ,  G11C16/0483 ,  G11C16/10 ,  G11C17/18 ,  G11C29/32 ,  G11C29/44 ,  H01L21/6835 ,  H01L21/76254 ,  H01L21/84 ,  H01L23/544 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L25/0655 ,  H01L27/0207 ,  H01L27/0688 ,  H01L27/0694 ,  H01L27/088 ,  H01L27/092 ,  H01L27/1052 ,  H01L27/10802 ,  H01L27/10894 ,  H01L27/10897 ,  H01L27/1104 ,  H01L27/1108 ,  H01L27/1116 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/11551 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11578 ,  H01L27/11807 ,  H01L27/1203 ,  H01L29/1033 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7841 ,  H01L29/785 ,  H01L29/78696 ,  H01L29/7881 ,  H01L29/792 ,  H01L2221/6835 ,  H01L2221/68381 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/81001 ,  H01L2924/00014 ,  H01L2924/10253 ,  H01L2924/12032 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/00012 ,  H01L2924/00015 ,  H01L2924/014 ,  H01L2924/3512 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A 3D IC based system including: a first semiconductor layer including first alignment marks and first transistors, wherein the first transistors are interconnected by at least one metal layer including aluminum or copper; a second mono-crystallized semiconductor layer including second transistors and overlaying the at least one metal layer, wherein the at least one metal layer is in-between the first semiconductor layer and the second mono-crystallized semiconductor layer; and wherein the second transistors include a plurality of N-type transistors and P-type transistors, and wherein the second mono-crystallized semiconductor layer is transferred from a reusable donor wafer.

Abstract translation: 一种基于3D IC的系统，包括：包括第一对准标记和第一晶体管的第一半导体层，其中所述第一晶体管通过包括铝或铜的至少一个金属层互连; 包括第二晶体管并覆盖所述至少一个金属层的第二单结晶半导体层，其中所述至少一个金属层位于所述第一半导体层和所述第二单结晶半导体层之间; 并且其中所述第二晶体管包括多个N型晶体管和P型晶体管，并且其中所述第二单结晶半导体层从可重复使用的施主晶片转移。