公开(公告)号：US07202154B2

公开(公告)日：2007-04-10

申请号：US10707693

申请日：2004-01-05

Applicant: Jon A. Casey ,  Brian R. Sundlof

Inventor： Jon A. Casey ,  Brian R. Sundlof

IPC: H01L21/4763

CPC classification number: H05K3/4061 ,  H01L21/76898 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/09701 ,  H05K1/092 ,  H05K2201/068 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A metallization process and material system for metallizing either blind or through vias in silicon, involving forming a low coefficient of thermal expansion composite or suspension, relative to pure metals, such as copper, silver, or gold, and filling the via holes in the silicon with the paste or suspension. The suspensions sinter with minimal bulk shrinkage, forming highly conductive structures without the formation of macroscopic voids. The selected suspension maintains a coefficient of thermal expansion closer to that of silicon.

公开(公告)号：US07078259B2

公开(公告)日：2006-07-18

申请号：US10707746

申请日：2004-01-08

Applicant: Jon A. Casey ,  William J. Ferrante ,  Edward W. Kiewra ,  Carl J. Radens ,  William R. Tonti

Inventor： Jon A. Casey ,  William J. Ferrante ,  Edward W. Kiewra ,  Carl J. Radens ,  William R. Tonti

IPC: H01L21/00

CPC classification number: H01L21/76895 ,  G01K7/226 ,  H01C7/006 ,  H01L21/76224 ,  H01L21/76838

Abstract: A structure and method are provided for forming a thermistor. Isolation structures are formed in a substrate including at least an upper layer of a single crystal semiconductor. A layer of salicide precursor is deposited over the isolation region and the upper layer. The salicide precursor is then reacted with the upper layer to form a salicide self-aligned to the upper layer. Finally, the unreacted portions of the salicide precursor are then removed while preserving a portion of the salicide precursor over the isolation region as a body of the thermistor. An alternative integrated circuit thermistor is formed from a region of thermistor material in an embossed region of an interlevel dielectric (ILD).

Abstract translation: 提供了用于形成热敏电阻的结构和方法。 隔离结构形成在至少包括单晶半导体的上层的基板中。 一层自杀化合物前体沉积在隔离区和上层上。 然后将自对准硅化物前体与上层反应以形成与上层自对准的自对准硅化物。 最后，除去自对准硅胶前体的未反应部分，同时在作为热敏电阻体的隔离区域上保留一部分自杀化合物前体。 一种替代的集成电路热敏电阻由层间电介质（ILD）的压花区域中的热敏电阻材料的区域形成。

公开(公告)号：US06916670B2

公开(公告)日：2005-07-12

申请号：US10358431

申请日：2003-02-04

Applicant: Jon A. Casey ,  James G. Balz ,  Michael Berger ,  Jerome Cohen ,  Charles Hendricks ,  Richard Indyk ,  Mark LaPlante ,  David C. Long ,  Lori A. Maiorino ,  Arthur G. Merryman ,  Glenn A. Pomerantz ,  Robert A. Rita ,  Krystyna W. Semkow ,  Patrick E. Spencer ,  Brian R. Sundlof ,  Richard P. Surprenant ,  Donald R. Wall ,  Thomas A. Wassick ,  Kathleen M. Wiley

Inventor： Jon A. Casey ,  James G. Balz ,  Michael Berger ,  Jerome Cohen ,  Charles Hendricks ,  Richard Indyk ,  Mark LaPlante ,  David C. Long ,  Lori A. Maiorino ,  Arthur G. Merryman ,  Glenn A. Pomerantz ,  Robert A. Rita ,  Krystyna W. Semkow ,  Patrick E. Spencer ,  Brian R. Sundlof ,  Richard P. Surprenant ,  Donald R. Wall ,  Thomas A. Wassick ,  Kathleen M. Wiley

IPC: H05K3/46 ,  H01L21/48 ,  H01L23/12 ,  H01L23/498 ,  H05K1/03 ,  H05K3/00 ,  H05K3/22 ,  H01L21/00

CPC classification number: H05K3/225 ,  H01L21/4846 ,  H01L23/49811 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01L2924/3011 ,  H05K1/0306 ,  H05K3/0029 ,  H05K3/4629 ,  H05K2203/173 ,  Y10T29/49124 ,  Y10T29/49135 ,  H01L2924/00

Abstract: A multilayer ceramic repair process which provides a new electrical repair path to connect top surface vias. The repair path is established between a defective net and a redundant repair net contained within the multilayer ceramic substrate. The defective net and the repair net each terminate at surface vias of the substrate. A laser is used to form post fired circuitry on and in the substrate. This is followed by the electrical isolation of the defective net from the electrical repair structure and passivation of the electrical repair line.

Abstract translation: 一种多层陶瓷修复工艺，提供了一种新的电气修复路径，以连接顶部表面通孔。 修复路径是建立在有缺陷的网和包含在多层陶瓷基片内的冗余修复网之间。 有缺陷的网和修复网各自终止在基板的表面通孔处。 使用激光器在基板上和基板上形成点火电路。 之后是有缺陷的网络与电气修复结构的电气隔离和电气修复线路的钝化。

公开(公告)号：US06878616B1

公开(公告)日：2005-04-12

申请号：US10719704

申请日：2003-11-21

Applicant: Jon A. Casey ,  Daniel C. Edelstein

Inventor： Jon A. Casey ,  Daniel C. Edelstein

IPC: H01L21/316 ,  H01L21/768 ,  H01L21/4763

CPC classification number: H01L21/02129 ,  H01L21/02142 ,  H01L21/02164 ,  H01L21/02203 ,  H01L21/02318 ,  H01L21/02343 ,  H01L21/31625 ,  H01L21/31695 ,  H01L21/7682

Abstract: A low-k dielectric for use as an interlayer for an interconnect structure is provided. The dielectric of the present invention is an alkaline boron silicate glass which when formulated in certain compositional ranges can undergo spinodal decomposition when processed using certain thermal profiles. Spinodal decomposition is a chemical and physical separation of the silicate glass into a distinct interpenetrating microstructure which contains a substantially pure silicon dioxide network and a boron-rich network. The dimension (i.e., scale), and the amount of separation can be controlled through compositional and thermal control during the processing of the silicate glass.

Abstract translation: 提供了用作互连结构的中间层的低k电介质。 本发明的电介质是碱性硼硅酸盐玻璃，当在某些组成范围内配制时，当使用某些热分布进行加工时，可以发生旋节分解。 晶间分解是将硅酸盐玻璃化学和物理分离成独特的互穿微结构，其包含基本上纯的二氧化硅网络和富含硼的网络。 通过在硅酸盐玻璃的加工过程中的组合和热控制可以控制尺寸（即刻度）和分离量。

公开(公告)号：US06823585B2

公开(公告)日：2004-11-30

申请号：US10249305

申请日：2003-03-28

Applicant: Mark J. LaPlante ,  Jon A. Casey ,  Thomas A. Wassick ,  David C. Long ,  Krystyna W. Semkow ,  Patrick E. Spencer ,  Robert A. Rita ,  Richard F. Indyk ,  Kathleen M. Wiley ,  Brian R. Sundlof ,  James Balz ,  Lori A. Maiorino ,  Donald R. Wall ,  Glenn A. Pomerantz

Inventor： Mark J. LaPlante ,  Jon A. Casey ,  Thomas A. Wassick ,  David C. Long ,  Krystyna W. Semkow ,  Patrick E. Spencer ,  Robert A. Rita ,  Richard F. Indyk ,  Kathleen M. Wiley ,  Brian R. Sundlof ,  James Balz ,  Lori A. Maiorino ,  Donald R. Wall ,  Glenn A. Pomerantz

IPC: H01R4300

CPC classification number: H05K3/242 ,  H05K1/0306 ,  H05K3/0035 ,  H05K3/048 ,  H05K3/184 ,  H05K3/225 ,  H05K2203/0191 ,  H05K2203/0264 ,  H05K2203/0574 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49158 ,  Y10T29/49163 ,  Y10T29/49165 ,  Y10T29/49171 ,  Y10T29/49172 ,  Y10T29/49721 ,  Y10T29/49732 ,  Y10T29/49737 ,  Y10T29/49746

Abstract: A method and structure to form surface plating metallization on a substrate. Two layers of tape are applied to the surface of the substrate. A first path is cut through both layers of tape exposing the substrate surface. The first path connects at least one conductive via on the top surface of the substrate. A second path is cut through the second layer of tape exposing the first layer of tape. The second path is routed from the first path to an edge of the substrate A seed layer is deposited over the surface of the second layer of tape thereby creating a seeded plating path in the first path and a sacrificial seeded conduction path in the second path. Connecting the sacrificial seeded conduction path to a plating potential at the edge of the substrate creates a plated path on the surface of the substrate. The sacrificial path is removed when the tape is removed.

Abstract translation: 在基板上形成表面电镀金属化的方法和结构。 将两层胶带施加到基材的表面。 通过暴露衬底表面的两层带切割第一路径。 第一路径在衬底的顶表面上连接至少一个导电通孔。 通过暴露第一层胶带的第二层胶带切割第二条路径。 第二路径从第一路径路由到衬底的边缘。种子层沉积在第二层带的表面上，从而在第一路径中形成种子电镀路径，并在第二路径中形成牺牲种子传导路径。 将牺牲种子传导路径连接到衬底边缘处的电镀电位在衬底的表面上产生电镀路径。 去除胶带时，去除牺牲路径。

公开(公告)号：US06423174B1

公开(公告)日：2002-07-23

申请号：US08668291

申请日：1996-06-21

Applicant: Jon A. Casey ,  Govindarajan Natarajan ,  Robert W. Pasco ,  Vincent P. Peterson

Inventor： Jon A. Casey ,  Govindarajan Natarajan ,  Robert W. Pasco ,  Vincent P. Peterson

IPC: B32B3120

CPC classification number: B32B18/00 ,  B32B37/0023 ,  B32B2038/042 ,  B32B2309/12 ,  B32B2315/02 ,  C04B35/10 ,  C04B35/581 ,  C04B35/6455 ,  C04B2235/658 ,  C04B2237/343 ,  C04B2237/366 ,  C04B2237/62 ,  C04B2237/64 ,  H01L21/4807

Abstract: The present invention relates generally to a new apparatus and method for forming cavities in semiconductor substrates without the necessity of using an insert. More particularly, the invention encompasses an apparatus and a method for fabricating cavities in semiconductor substrates wherein a coated membrane sheet is placed over the cavity prior to lamination and caused to conform to the contour of the cavity, thus preventing collapse of, or damage to, the cavity shelves during the lamination process. After the lamination process, the coated membrane is conveniently removed without causing damage to the cavity shelves or paste pull-outs.

Abstract translation: 本发明一般涉及一种用于在半导体衬底中形成空腔的新装置和方法，而不需要使用插入件。 更具体地，本发明包括一种用于在半导体衬底中制造空腔的装置和方法，其中在层压之前将涂覆的膜片放置在空腔上方并使其符合空腔的轮廓，从而防止凹陷或损坏， 层压过程中的腔架。 在层压处理之后，方便地去除涂覆的膜，而不会损坏腔架或糊状物拉出。

公开(公告)号：US06413339B1

公开(公告)日：2002-07-02

申请号：US09470457

申请日：1999-12-22

Applicant: Govindarajan Natarajan ,  Jon A. Casey ,  Martin E. Klepeis ,  John U. Knickerbocker ,  Srinivasa S. N. Reddy ,  Robert A. Rita ,  Subhash L. Shinde

Inventor： Govindarajan Natarajan ,  Jon A. Casey ,  Martin E. Klepeis ,  John U. Knickerbocker ,  Srinivasa S. N. Reddy ,  Robert A. Rita ,  Subhash L. Shinde

IPC: B32B3116

CPC classification number: C04B35/2683 ,  C04B35/64 ,  H01F1/0027 ,  H01F41/0253 ,  Y10T156/1056 ,  Y10T156/1057

Abstract: The present invention relates generally to a new metal/magnetic-ceramic laminate with through-holes and process thereof. More particularly, the invention encompasses a new process for fabrication of a large area ceramic laminate magnet with a significant number of holes, integrated metal plate(s) and co-sintered electrodes for electron and electron beam control. The present invention also relates to a magnetic matrix display (MMD), and electron beam source, and methods of manufacture thereof.

Abstract translation: 本发明一般涉及具有通孔的新的金属/磁陶瓷层压体及其工艺。 更具体地，本发明包括用于制造具有大量孔的大面积陶瓷层压体磁体的新方法，用于电子和电子束控制的集成金属板和共烧结电极。 本发明还涉及磁矩阵显示器（MMD）和电子束源，及其制造方法。

公开(公告)号：US6015517A

公开(公告)日：2000-01-18

申请号：US057306

申请日：1998-04-08

Applicant: Jon A. Casey

Inventor： Jon A. Casey

IPC: B22F3/10 ,  B22F3/11 ,  C04B35/638 ,  C04B35/64 ,  C04B38/06 ,  B29C65/00

CPC classification number: B22F3/1021 ,  B22F3/1121 ,  C04B35/638 ,  C04B35/64 ,  C04B38/06 ,  C04B38/068 ,  C04B2111/00267 ,  C04B2111/00482 ,  C04B2111/00793

Abstract: A ceramic contact sheet and setter tile with controlled porosity is introduced, along with the method for making the same. The amount of porosity is controlled by the volume percentage, particle size, and particle shape of a fugitive phase which can be added to the original refractory material slurry used to fabricate setter tiles and contact sheets. The fugitive phase can be used independently to introduce porosity in setter tiles and contact sheets or in conjunction with partial densification. Since porosity is not solely dependent upon partial sintering, higher porosity levels can be achieved with less impact on subsequent mechanical properties of the resultant refractory material.

Abstract translation: 引入了具有受控孔隙率的陶瓷接触片和固定器片及其制造方法。 孔隙度的量由易位相的体积百分比，粒度和颗粒形状控制，这可以添加到用于制造安装器瓦片和接触片材的原始耐火材料浆料中。 逸散相可以独立地用于在固化剂砖和接触片中引入孔隙率，或与部分致密化相结合。 由于孔隙度不仅仅取决于部分烧结，所以可以实现较高的孔隙率水平，而对所得到的耐火材料的随后的机械性能的影响较小。

公开(公告)号：US5870823A

公开(公告)日：1999-02-16

申请号：US756362

申请日：1996-11-27

Applicant: Raschid J. Bezama ,  Jon A. Casey ,  John B. Pavelka ,  Glenn A. Pomerantz

Inventor： Raschid J. Bezama ,  Jon A. Casey ,  John B. Pavelka ,  Glenn A. Pomerantz

IPC: H01L23/473 ,  H05K3/22 ,  H05K3/46

CPC classification number: H01L23/473 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49175 ,  H01L2924/09701 ,  H01L2924/15312 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49158 ,  Y10T29/49163

Abstract: Disclosed is an electronic packaging substrate which includes a sintered ceramic body having at least one internal layer of wiring and at least one cooling channel internal to and integral with the sintered ceramic body for cooling a heat-generating electronic device placed on the sintered body. Also disclosed is a method of making the electronic packaging substrate.

Abstract translation: 公开了一种电子封装基板，其包括具有至少一个布线内层和至少一个内部并与烧结陶瓷体一体的冷却通道的烧结陶瓷体，用于冷却放置在烧结体上的发热电子器件。 还公开了制造电子封装基板的方法。

公开(公告)号：US5480503A

公开(公告)日：1996-01-02

申请号：US175727

申请日：1993-12-30

Applicant: Jon A. Casey ,  David B. Goland ,  Dinesh Gupta ,  Lester W. Herron ,  James N. Humenik ,  Thomas E. Lombardi ,  John U. Knickerbocker ,  Robert J. Sullivan ,  James R. Wylder

Inventor： Jon A. Casey ,  David B. Goland ,  Dinesh Gupta ,  Lester W. Herron ,  James N. Humenik ,  Thomas E. Lombardi ,  John U. Knickerbocker ,  Robert J. Sullivan ,  James R. Wylder

IPC: H01L21/48 ,  H01L21/68 ,  H01L23/538 ,  H05K1/03 ,  H05K3/20 ,  H05K3/40 ,  H05K3/46 ,  B32B31/04 ,  B32B31/12 ,  B32B31/26 ,  B32B31/28

CPC classification number: H01L21/568 ,  H01L21/4857 ,  H01L21/6835 ,  H01L23/5383 ,  H01L23/5385 ,  H05K3/20 ,  H05K3/4061 ,  H05K3/4617 ,  H05K3/4629 ,  H01L2924/0002 ,  H01L2924/09701 ,  H05K1/0306 ,  Y10T156/1056 ,  Y10T156/1142 ,  Y10T29/49126 ,  Y10T29/49128

Abstract: Process for producing circuitized greensheets including multi-layer ceramic sub-laminates and composites comprising thin ceramic greensheets carrying and thin, fine line patterned conductive metal layers. The invention comprises releasably-supporting the thin greensheets on a temporary carrier support having an ablatable release layer, preferably over a patterned conductive layer, and filling the vias with conductive metal paste, whereby the thin greensheets are supported against warpage and distortion. The supported greensheets are formed as single layers, pairs and stacks thereof, as desired, and thereafter separated from the temporary support for use.

Abstract translation: 用于生产包括多层陶瓷亚层压板和复合材料的电路化滤纸的方法，该复合材料包括载有薄的陶瓷片材和薄的精细线图案化的导电金属层。 本发明包括在具有可消融脱模层的临时载体支撑件上可释放地支撑薄片，优选地在图案化的导电层之上，并且用导电金属浆料填充该通孔，从而支撑薄的薄片以防止翘曲和变形。 支撑的格子根据需要形成为单层，成对和堆叠，然后与临时支撑件分离使用。