公开(公告)号：US07449067B2

公开(公告)日：2008-11-11

申请号：US10700327

申请日：2003-11-03

Applicant: Paul S. Andry ,  Jon A. Casey ,  Raymond R. Horton ,  Chiraq S. Patel ,  Edmund J. Sprogis ,  Brian R. Sundlof

Inventor： Paul S. Andry ,  Jon A. Casey ,  Raymond R. Horton ,  Chiraq S. Patel ,  Edmund J. Sprogis ,  Brian R. Sundlof

IPC: B05C1/00 ,  B05C3/00 ,  B05C3/18

CPC classification number: H01L21/486 ,  H01L23/147 ,  H01L2224/16225 ,  H01L2924/10253 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/00

Abstract: A method for filling vias, and in particular initially blind vias, in a wafer, and various apparatus for performing the method, comprising evacuating air from the vias; trapping at least a portion of the wafer and a paste for filling the vias between two surfaces; and pressurizing the paste to fill the vias.

Abstract translation: 一种用于在晶片中填充通孔，特别是初始盲孔的方法，以及用于执行该方法的各种装置，包括从通孔排出空气; 捕获晶片的至少一部分和用于在两个表面之间填充通孔的糊状物; 并对该糊状物加压以填充通孔。

公开(公告)号：US07288474B2

公开(公告)日：2007-10-30

申请号：US11544220

申请日：2006-10-10

Applicant: Jon A. Casey ,  Brian R. Sundlof

Inventor： Jon A. Casey ,  Brian R. Sundlof

IPC: H01L21/4763

CPC classification number: H05K3/4061 ,  H01L21/76898 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/09701 ,  H05K1/092 ,  H05K2201/068 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A metallization process and material system for metallizing either blind or through vias in silicon, involving forming a low coefficient of thermal expansion composite or suspension, relative to pure metals, such as copper, silver, or gold, and filling the via holes in the silicon with the paste or suspension. The suspensions sinter with minimal bulk shrinkage, forming highly conductive structures without the formation of macroscopic voids. The selected suspension maintains a coefficient of thermal expansion closer to that of silicon.

Abstract translation: 一种金属化工艺和材料系统，用于在硅中金属化盲孔或通孔，涉及相对于纯金属（例如铜，银或金）形成低热膨胀复合材料或悬浮系数，并填充硅中的通孔 用糊或悬浮液。 悬浮液以最小的体积收缩率烧结，形成高导电性结构，而不形成宏观空隙。 所选择的悬架保持更接近于硅的热膨胀系数。

公开(公告)号：US07294909B2

公开(公告)日：2007-11-13

申请号：US11099161

申请日：2005-04-05

Applicant: Jon A. Casey ,  James G. Balz ,  Michael Berger ,  Jerome Cohen ,  Charles Hendricks ,  Richard Indyk ,  Mark LaPlante ,  David C. Long ,  Lori A. Maiorino ,  Arthur G. Merryman ,  Glenn A. Pomerantz ,  Robert A. Rita ,  Krystyna W. Semkow ,  Patrick E. Spencer ,  Brian R. Sundlof ,  Richard P. Surprenant ,  Donald R. Wall ,  Thomas A. Wassick ,  Kathleen M. Wiley

Inventor： Jon A. Casey ,  James G. Balz ,  Michael Berger ,  Jerome Cohen ,  Charles Hendricks ,  Richard Indyk ,  Mark LaPlante ,  David C. Long ,  Lori A. Maiorino ,  Arthur G. Merryman ,  Glenn A. Pomerantz ,  Robert A. Rita ,  Krystyna W. Semkow ,  Patrick E. Spencer ,  Brian R. Sundlof ,  Richard P. Surprenant ,  Donald R. Wall ,  Thomas A. Wassick ,  Kathleen M. Wiley

IPC: H01L27/148 ,  H01L29/768

CPC classification number: H05K3/225 ,  H01L21/4846 ,  H01L23/49811 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01L2924/3011 ,  H05K1/0306 ,  H05K3/0029 ,  H05K3/4629 ,  H05K2203/173 ,  Y10T29/49124 ,  Y10T29/49135 ,  H01L2924/00

Abstract: A multilayer ceramic repair process which provides a new electrical repair path to connect top surface vias. The repair path is established between a defective net and a redundant repair net contained within the multilayer ceramic substrate. The defective net and the repair net each terminate at surface vias of the substrate. A laser is used to form post fired circuitry on and in the substrate. This is followed by the electrical isolation of the defective net from the electrical repair structure and passivation of the electrical repair line.

Abstract translation: 一种多层陶瓷修复工艺，提供了一个新的电气修复路径，以连接顶面通孔。 修复路径是建立在有缺陷的网和包含在多层陶瓷基板内的冗余修复网之间。 有缺陷的网和修复网各自终止在基板的表面通孔处。 使用激光器在基板上和基板上形成点火电路。 之后是有缺陷的网络与电气修复结构的电气隔离和电气修复线路的钝化。

公开(公告)号：US07202154B2

公开(公告)日：2007-04-10

申请号：US10707693

申请日：2004-01-05

Applicant: Jon A. Casey ,  Brian R. Sundlof

Inventor： Jon A. Casey ,  Brian R. Sundlof

IPC: H01L21/4763

CPC classification number: H05K3/4061 ,  H01L21/76898 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/09701 ,  H05K1/092 ,  H05K2201/068 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A metallization process and material system for metallizing either blind or through vias in silicon, involving forming a low coefficient of thermal expansion composite or suspension, relative to pure metals, such as copper, silver, or gold, and filling the via holes in the silicon with the paste or suspension. The suspensions sinter with minimal bulk shrinkage, forming highly conductive structures without the formation of macroscopic voids. The selected suspension maintains a coefficient of thermal expansion closer to that of silicon.

公开(公告)号：US06916670B2

公开(公告)日：2005-07-12

申请号：US10358431

申请日：2003-02-04

Applicant: Jon A. Casey ,  James G. Balz ,  Michael Berger ,  Jerome Cohen ,  Charles Hendricks ,  Richard Indyk ,  Mark LaPlante ,  David C. Long ,  Lori A. Maiorino ,  Arthur G. Merryman ,  Glenn A. Pomerantz ,  Robert A. Rita ,  Krystyna W. Semkow ,  Patrick E. Spencer ,  Brian R. Sundlof ,  Richard P. Surprenant ,  Donald R. Wall ,  Thomas A. Wassick ,  Kathleen M. Wiley

Inventor： Jon A. Casey ,  James G. Balz ,  Michael Berger ,  Jerome Cohen ,  Charles Hendricks ,  Richard Indyk ,  Mark LaPlante ,  David C. Long ,  Lori A. Maiorino ,  Arthur G. Merryman ,  Glenn A. Pomerantz ,  Robert A. Rita ,  Krystyna W. Semkow ,  Patrick E. Spencer ,  Brian R. Sundlof ,  Richard P. Surprenant ,  Donald R. Wall ,  Thomas A. Wassick ,  Kathleen M. Wiley

IPC: H05K3/46 ,  H01L21/48 ,  H01L23/12 ,  H01L23/498 ,  H05K1/03 ,  H05K3/00 ,  H05K3/22 ,  H01L21/00

CPC classification number: H05K3/225 ,  H01L21/4846 ,  H01L23/49811 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01L2924/3011 ,  H05K1/0306 ,  H05K3/0029 ,  H05K3/4629 ,  H05K2203/173 ,  Y10T29/49124 ,  Y10T29/49135 ,  H01L2924/00

Abstract: A multilayer ceramic repair process which provides a new electrical repair path to connect top surface vias. The repair path is established between a defective net and a redundant repair net contained within the multilayer ceramic substrate. The defective net and the repair net each terminate at surface vias of the substrate. A laser is used to form post fired circuitry on and in the substrate. This is followed by the electrical isolation of the defective net from the electrical repair structure and passivation of the electrical repair line.

Abstract translation: 一种多层陶瓷修复工艺，提供了一种新的电气修复路径，以连接顶部表面通孔。 修复路径是建立在有缺陷的网和包含在多层陶瓷基片内的冗余修复网之间。 有缺陷的网和修复网各自终止在基板的表面通孔处。 使用激光器在基板上和基板上形成点火电路。 之后是有缺陷的网络与电气修复结构的电气隔离和电气修复线路的钝化。

公开(公告)号：US06823585B2

公开(公告)日：2004-11-30

申请号：US10249305

申请日：2003-03-28

Applicant: Mark J. LaPlante ,  Jon A. Casey ,  Thomas A. Wassick ,  David C. Long ,  Krystyna W. Semkow ,  Patrick E. Spencer ,  Robert A. Rita ,  Richard F. Indyk ,  Kathleen M. Wiley ,  Brian R. Sundlof ,  James Balz ,  Lori A. Maiorino ,  Donald R. Wall ,  Glenn A. Pomerantz

Inventor： Mark J. LaPlante ,  Jon A. Casey ,  Thomas A. Wassick ,  David C. Long ,  Krystyna W. Semkow ,  Patrick E. Spencer ,  Robert A. Rita ,  Richard F. Indyk ,  Kathleen M. Wiley ,  Brian R. Sundlof ,  James Balz ,  Lori A. Maiorino ,  Donald R. Wall ,  Glenn A. Pomerantz

IPC: H01R4300

CPC classification number: H05K3/242 ,  H05K1/0306 ,  H05K3/0035 ,  H05K3/048 ,  H05K3/184 ,  H05K3/225 ,  H05K2203/0191 ,  H05K2203/0264 ,  H05K2203/0574 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49158 ,  Y10T29/49163 ,  Y10T29/49165 ,  Y10T29/49171 ,  Y10T29/49172 ,  Y10T29/49721 ,  Y10T29/49732 ,  Y10T29/49737 ,  Y10T29/49746

Abstract: A method and structure to form surface plating metallization on a substrate. Two layers of tape are applied to the surface of the substrate. A first path is cut through both layers of tape exposing the substrate surface. The first path connects at least one conductive via on the top surface of the substrate. A second path is cut through the second layer of tape exposing the first layer of tape. The second path is routed from the first path to an edge of the substrate A seed layer is deposited over the surface of the second layer of tape thereby creating a seeded plating path in the first path and a sacrificial seeded conduction path in the second path. Connecting the sacrificial seeded conduction path to a plating potential at the edge of the substrate creates a plated path on the surface of the substrate. The sacrificial path is removed when the tape is removed.

Abstract translation: 在基板上形成表面电镀金属化的方法和结构。 将两层胶带施加到基材的表面。 通过暴露衬底表面的两层带切割第一路径。 第一路径在衬底的顶表面上连接至少一个导电通孔。 通过暴露第一层胶带的第二层胶带切割第二条路径。 第二路径从第一路径路由到衬底的边缘。种子层沉积在第二层带的表面上，从而在第一路径中形成种子电镀路径，并在第二路径中形成牺牲种子传导路径。 将牺牲种子传导路径连接到衬底边缘处的电镀电位在衬底的表面上产生电镀路径。 去除胶带时，去除牺牲路径。

公开(公告)号：US08493746B2

公开(公告)日：2013-07-23

申请号：US12704592

申请日：2010-02-12

Applicant: Charles L. Arvin ,  Alexandre Blander ,  Peter J. Brofman ,  Donald W. Henderson ,  Gareth G. Hougham ,  Hsichang Liu ,  Eric D. Perfecto ,  Srinivasa S. N. Reddy ,  Krystyna W. Semkow ,  Kamalesh K. Srivastava ,  Brian R. Sundlof ,  Julien Sylvestre ,  Renee L. Weisman

Inventor： Charles L. Arvin ,  Alexandre Blander ,  Peter J. Brofman ,  Donald W. Henderson ,  Gareth G. Hougham ,  Hsichang Liu ,  Eric D. Perfecto ,  Srinivasa S. N. Reddy ,  Krystyna W. Semkow ,  Kamalesh K. Srivastava ,  Brian R. Sundlof ,  Julien Sylvestre ,  Renee L. Weisman

IPC: H05K7/00 ,  H05K1/03 ,  H05K1/11 ,  H05K7/10 ,  H01L23/48

CPC classification number: H01B1/02 ,  B23K35/0244 ,  B23K35/262 ,  B23K35/36 ,  B23K35/3602 ,  B82Y30/00 ,  C22C13/00 ,  H01B13/00 ,  H01L23/49866 ,  H01L2924/0002 ,  H05K3/3436 ,  H05K3/3463 ,  H05K2201/0209 ,  H05K2201/0257 ,  Y10T29/49117 ,  H01L2924/00

Abstract: In one embodiment of the present invention, inert nano-sized particles having dimensions from 1 nm to 1,000 nm are added into a solder ball. The inert nano-sized particles may comprise metal oxides, metal nitrides, metal carbides, metal borides, etc. The inert nano-sized particles may be a single compound, or may be a metallic material having a coating of a different material. In another embodiment of the present invention, a small quantity of at least one elemental metal that forms stable high melting intermetallic compound with tin is added to a solder ball. The added at least one elemental metal forms precipitates of intermetallic compounds with tin, which are dispersed as fine particles in the solder.

Abstract translation: 在本发明的一个实施方案中，将尺寸为1nm至1000nm的惰性纳米尺寸颗粒加入到焊球中。 惰性纳米尺寸颗粒可以包括金属氧化物，金属氮化物，金属碳化物，金属硼化物等。惰性纳米尺寸颗粒可以是单一化合物，或者可以是具有不同材料的涂层的金属材料。 在本发明的另一个实施方案中，将少量与锡形成稳定的高熔点金属间化合物的元素金属添加到焊料球中。 添加的至少一种元素金属与锡形成金属间化合物的沉淀物，其作为细颗粒分散在焊料中。

公开(公告)号：US20120211159A1

公开(公告)日：2012-08-23

申请号：US11758457

申请日：2007-06-05

Applicant: Gareth Hougham ,  Paul A. Lauro ,  Brian R. Sundlof ,  Jeffrey D. Gelorme

Inventor： Gareth Hougham ,  Paul A. Lauro ,  Brian R. Sundlof ,  Jeffrey D. Gelorme

IPC: C09K5/00 ,  C09J5/00 ,  B82Y40/00

CPC classification number: H01L23/3733 ,  B82Y30/00 ,  H01L23/373 ,  H01L23/3736 ,  H01L23/40 ,  H01L2224/16225 ,  H01L2924/00011 ,  H01L2924/00014 ,  Y10S977/788 ,  Y10T156/10 ,  Y10T428/24994 ,  H01L2224/0401

Abstract: The present invention relates generally to thermally-conductive pastes for use with integrated circuits, and particularly, but not by way of limitation, to self-orienting microplates of graphite.

Abstract translation: 本发明一般涉及用于集成电路的导热膏，特别是但不限于石墨的自取向微孔板。

公开(公告)号：US20110193218A1

公开(公告)日：2011-08-11

申请号：US12700863

申请日：2010-02-05

Applicant: Charles L. Arvin ,  Raschid J. Bezama ,  Timothy H. Daubenspeck ,  Jeffrey P. Gambino ,  Christopher D. Muzzy ,  David L. Questad ,  Wolfgang Sauter ,  Timothy D. Sullivan ,  Brian R. Sundlof

Inventor： Charles L. Arvin ,  Raschid J. Bezama ,  Timothy H. Daubenspeck ,  Jeffrey P. Gambino ,  Christopher D. Muzzy ,  David L. Questad ,  Wolfgang Sauter ,  Timothy D. Sullivan ,  Brian R. Sundlof

IPC: H01L23/498 ,  H01L21/768

CPC classification number: H01L24/13 ,  H01L23/49811 ,  H01L24/11 ,  H01L24/16 ,  H01L2224/0401 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/10126 ,  H01L2224/11334 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2224/1182 ,  H01L2224/119 ,  H01L2224/13017 ,  H01L2224/13018 ,  H01L2224/1308 ,  H01L2224/13083 ,  H01L2224/13084 ,  H01L2224/13101 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13565 ,  H01L2224/1357 ,  H01L2224/13687 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/3841 ,  H01L2924/00014 ,  H01L2924/01024 ,  H01L2924/01026 ,  H01L2924/01032 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A solder interconnect structure is provided with non-wettable sidewalls and methods of manufacturing the same. The method includes forming a nickel or nickel alloy pillar on an underlying surface. The method further includes modifying the sidewall of the nickel or nickel alloy pillar to prevent solder wetting on the sidewall.

Abstract translation: 焊接互连结构设置有不可润湿的侧壁及其制造方法。 该方法包括在下面的表面上形成镍或镍合金支柱。 该方法还包括修改镍或镍合金柱的侧壁以防止在侧壁上的焊料润湿。

公开(公告)号：US20080202386A1

公开(公告)日：2008-08-28

申请号：US12039309

申请日：2008-02-28

Applicant: Gareth Hougham ,  Paul A. Lauro ,  Brian R. Sundlof ,  Jeffrey D. Gelorme

Inventor： Gareth Hougham ,  Paul A. Lauro ,  Brian R. Sundlof ,  Jeffrey D. Gelorme

IPC: C09C1/44 ,  C09K5/10

CPC classification number: H01L23/3733 ,  B82Y30/00 ,  H01L23/373 ,  H01L23/3736 ,  H01L23/40 ,  H01L2224/16225 ,  H01L2924/00011 ,  H01L2924/00014 ,  Y10S977/788 ,  Y10T156/10 ,  Y10T428/24994 ,  H01L2224/0401

Abstract: The present invention relates generally to thermally-conductive pastes for use with integrated circuits, and particularly, but not by way of limitation, to self-orienting microplates of graphite.

Abstract translation: 本发明一般涉及用于集成电路的导热膏，特别是但不限于石墨的自取向微孔板。