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    Semiconductor intergrated circuit
    53.
    发明授权
    Semiconductor intergrated circuit 失效
    半导体集成电路

    公开(公告)号：US5027167A

    公开(公告)日：1991-06-25

    申请号：US175705

    申请日：1988-03-31

    申请人： Osamu Kagaya ,  Yasunari Umemoto ,  Junji Shigeta

    发明人： Osamu Kagaya ,  Yasunari Umemoto ,  Junji Shigeta

    IPC分类号： H01L21/761 ,  H01L21/338 ,  H01L21/76 ,  H01L21/765 ,  H01L27/10 ,  H01L29/812

    CPC分类号： H01L21/765 ,  H01L21/7605

    摘要： The semiconductor integrated circuit of the present invention includes an electrode to which potential is supplied to apply an electric field to an isolation layer between similar semiconductor layers having ohmic electrodes and implanted into a compound semiconductor substrate. By this construction this invention reduces the development of temporary conduction in the isolation layer due to disturbance of potential barrier by .alpha. particles, and can improve pronouncedly the tolerance to .alpha. particle induced soft errors.

    摘要翻译： 本发明的半导体集成电路包括提供电位的电极，用于向具有欧姆电极的类似半导体层之间的隔离层施加电场并注入到化合物半导体衬底中。 通过这种结构，本发明减少了由于α粒子对势垒的干扰而导致的隔离层临时传导的发展，并且可以显着改善对α粒子诱导的软错误的耐受性。

    Semiconductor integrated circuit memory
    54.
    发明授权
    Semiconductor integrated circuit memory 失效
    半导体集成电路存储器

    公开(公告)号：US4954866A

    公开(公告)日：1990-09-04

    申请号：US247250

    申请日：1988-09-21

    申请人： Hirotoshi Tanaka ,  Hiroki Yamashita ,  Noboru Masuda ,  Junji Shigeta ,  Yasunari Umemoto ,  Osamu Kagaya

    发明人： Hirotoshi Tanaka ,  Hiroki Yamashita ,  Noboru Masuda ,  Junji Shigeta ,  Yasunari Umemoto ,  Osamu Kagaya

    IPC分类号： H01L27/06 ,  H01L27/105 ,  H01L27/11

    CPC分类号： H01L27/1104 ,  H01L27/0605 ,  H01L27/1116 ,  H01L27/105

    摘要： A semiconductor integrated circuit memory is disclosed in which a first impurity-doped layer for making circuit elements such as MESFET's and a second impurity-doped layer opposite in conductivity type to the first impurity-doped layer are formed in a semi-insulating substrate in such a manner that the second impurity-doped layer is formed under and between circuit elements for making up a memory cell array part and a peripheral circuit part, and is divided into at least first and second regions. For example, the first region formed under and between the circuit elements of the memory cell array part is made of a P-type layer which is high in carrier density, and the second region formed under and between the circuit elements of the peripheral circuit part is made of a P-type layer which is low in carrier density. The high carrier-density P-type layer formed under the memory cell array part allows a memory cell having a minimum critical charge for alpha-particles to gain satisfactory alpha-particle immunity even when the memory cell is made fine in size. Further, the low carrier-density P-type layer formed under the peripheral circuit part having a critical charge larger than that of the memory cell can improve the alpha-particle immunity of the peripheral circuit part and can suppress an increase in parasitic capacitance at the peripheral circuit part to maintain the high-speed operation of the memory.

    摘要翻译： 公开了一种半导体集成电路存储器，其中在半绝缘衬底中形成用于制造电路元件的第一杂质掺杂层，例如MESFET和与第一杂质掺杂层的导电类型相反的第二杂质掺杂层 第二杂质掺杂层形成在用于构成存储单元阵列部分的电路元件和外围电路部分之间的方式，并且被划分为至少第一和第二区域。 例如，形成在存储单元阵列部分的电路元件之下和之间的第一区域由载流子密度高的P型层制成，并且第二区域形成在外围电路部分的电路元件之下 由载流子浓度低的P型层构成。 形成在存储单元阵列部分下方的高载流子密度P型层允许具有最小临界电荷的存储单元获得满意的α粒子免疫，即使当存储单元的尺寸精细时。 此外，形成在具有大于存储单元的临界电荷的外围电路部分下的低载流子密度P型层可以改善外围电路部分的α粒子免疫力，并且可以抑制在外部电路部分的寄生电容的增加 外围电路部分保持高速运行的内存。

    Differential transmission circuit and information processing system
    55.
    发明授权
    Differential transmission circuit and information processing system 有权
    差分传输电路和信息处理系统

    公开(公告)号：US08676058B2

    公开(公告)日：2014-03-18

    申请号：US13450516

    申请日：2012-04-19

    申请人： Osamu Kagaya

    发明人： Osamu Kagaya

    IPC分类号： H04B10/00 ,  H05K7/00 ,  H01P3/08 ,  H04B10/80

    CPC分类号： H04B10/801 ,  H01P3/026 ,  H05K1/0218 ,  H05K1/0245 ,  H05K1/0246 ,  H05K1/025 ,  H05K1/162 ,  H05K2201/09727 ,  H05K2201/10121

    摘要： A differential transmission circuit includes a grounded conductive layer, a pair of transmission line conductors, a conductive film and a via hole which connects the grounded conductive layer to the conductive film. The differential transmission circuit further includes a straight-line region which is present in the differential transmission circuit through which a differential transmission signal output by a driving circuit is transmitted and in which the pair of transmission line conductors extends parallel so as to have a first width, and a band rejection filter region in which the pair of transmission line conductors planarly overlaps the conductive film and extends parallel so as to have a second width narrower than the first width and a common mode of the differential transmission signal is attenuated at one of the frequencies which are natural number multiples of a frequency corresponding to the predetermined bit rate.

    摘要翻译： 差分传输电路包括接地导电层，一对传输线导体，导电膜和将接地导电层连接到导电膜的通孔。 差分传输电路还包括存在于差分传输电路中的直线区域，通过该直线区域传输由驱动电路输出的差分传输信号，并且其中一对传输线导体平行延伸，以便具有第一宽度 以及阻带滤波器区域，其中所述一对传输线导体与导电膜平面重叠并且平行延伸，以具有比第一宽度窄的第二宽度，并且差分传输信号的共模在第 是与预定比特率对应的频率的自然数倍数的频率。

    DIFFERENTIAL TRANSMISSION CIRCUIT, OPTICAL MODULE, AND INFORMATION PROCESSING SYSTEM
    57.
    发明申请
    DIFFERENTIAL TRANSMISSION CIRCUIT, OPTICAL MODULE, AND INFORMATION PROCESSING SYSTEM 有权
    差分传输电路，光模块和信息处理系统

    公开(公告)号：US20120229998A1

    公开(公告)日：2012-09-13

    申请号：US13403048

    申请日：2012-02-23

    申请人： Osamu KAGAYA

    发明人： Osamu KAGAYA

    IPC分类号： H05K7/02 ,  H01P3/08

    CPC分类号： H01P3/08 ,  H01P1/02 ,  H01P3/085 ,  H01P3/088 ,  H05K1/111

    摘要： A differential transmission circuit includes a pair of transmission line conductors and a ground conductor layer, wherein the pair of transmission line conductors include a first straight line region where both the pair of transmission line conductors extend in parallel to each other in a first direction with a first width in a first layer, a first cross region where one of the pair of transmission line conductors is formed in the first layer, the other thereof is formed in a second layer, and the pair of transmission line conductors cross the each other in a three-dimensional manner, the first cross region being disposed on the front side of the first straight line region, and wherein each of the widths of the pair of transmission line conductors in the first cross region is smaller than the first width.

    摘要翻译： 差分传输电路包括一对传输线导体和接地导体层，其中所述一对传输线导体包括第一直线区域，其中所述一对传输线导体在第一方向上彼此平行延伸， 在第一层中的第一宽度，在第一层中形成一对传输线导体中的一个的第一交叉区域，另一个形成在第二层中，并且一对传输线导体以 第一交叉区域设置在第一直线区域的前侧，并且其中，第一交叉区域中的一对传输线导体的宽度小于第一宽度。

    OPTICAL TRANSMITTER DEVICE AND OPTICAL TRANSMITTER MODULE
    58.
    发明申请
    OPTICAL TRANSMITTER DEVICE AND OPTICAL TRANSMITTER MODULE 有权
    光传输器件和光传输模块

    公开(公告)号：US20100232806A1

    公开(公告)日：2010-09-16

    申请号：US12626033

    申请日：2009-11-25

    申请人： Osamu Kagaya ,  Satoshi Motohiro ,  Masahiro Hirai

    发明人： Osamu Kagaya ,  Satoshi Motohiro ,  Masahiro Hirai

    IPC分类号： H04B10/04

    CPC分类号： H04B10/2504 ,  H05K1/0246 ,  H05K1/141 ,  H05K1/147 ,  H05K1/189 ,  H05K2201/10022 ,  H05K2201/10121

    摘要： Provided are an optical transmitter device and an optical transmitter module which are capable of reducing the optical transmitter module size while maintaining a state where an excellent optical transmission waveform quality is obtained over a wide range of frequencies. The optical transmission module (2) includes a semiconductor laser diode device (10), an optical modulator device (12), and a first termination resistor circuit (14-1). A printed circuit board (4) includes a driver IC (16) and a second termination resistor circuit (14-2). A lower cutoff frequency of the first termination resistor circuit (14-1) and an upper cutoff frequency of the second termination resistor circuit (14-2) correspond to each other. An impedance of the first termination resistor circuit (14-1) in a pass frequency band thereof and an impedance of the second termination resistor circuit (14-2) in a pass frequency band thereof correspond to each other.

    摘要翻译： 提供了一种能够在保持在宽频率范围内获得良好的光传输波形质量的状态的同时降低光发射机模块尺寸的光发射机设备和光发射机模块。 光传输模块（2）包括半导体激光二极管装置（10），光调制装置（12）和第一终端电阻电路（14-1）。 印刷电路板（4）包括驱动器IC（16）和第二终端电阻电路（14-2）。 第一终端电阻电路（14-1）的下限截止频率和第二终端电阻电路（14-2）的上截止频率彼此对应。 其通过频带中的第一终端电阻电路（14-1）的阻抗和通过频带中的第二终端电阻电路（14-2）的阻抗彼此对应。

    PRINTED CIRCUIT BOARD AND OPTICAL TRANSMISSION DEVICE
    59.
    发明申请
    PRINTED CIRCUIT BOARD AND OPTICAL TRANSMISSION DEVICE 有权
    印刷电路板和光传输装置

    公开(公告)号：US20100124423A1

    公开(公告)日：2010-05-20

    申请号：US12618861

    申请日：2009-11-16

    申请人： Osamu KAGAYA ,  Koyu Takahashi ,  Taichi Kogure

    发明人： Osamu KAGAYA ,  Koyu Takahashi ,  Taichi Kogure

    IPC分类号： H04B10/04 ,  H01P1/20

    CPC分类号： H01P1/20345 ,  H01P1/2039 ,  H04B10/40 ,  H05K1/0233 ,  H05K1/0243 ,  H05K1/162 ,  H05K1/165 ,  H05K2201/09309 ,  H05K2201/09627 ,  H05K2201/10121 ,  H05K2201/10689

    摘要： To reduce emission of an unintentional electromagnetic wave even if a frequency of a clock signal being output is high, a printed circuit board (10) includes: a substrate (101); signal output circuits (102 and 103) formed on the substrate (101), for outputting a clock signal; power supply wirings (109 and 110) for connecting the signal output circuits (102 and 103) and a power source; and trap filters (107 and 108) provided to the power supply wirings (109 and 110), for attenuating a frequency component corresponding to a frequency of the clock signal.

    摘要翻译： 为了减少输出时钟信号的频率高的无意的电磁波的发射，印刷电路板（10）包括：基板（101）; 形成在基板（101）上的信号输出电路（102和103），用于输出时钟信号; 用于连接信号输出电路（102和103）和电源的电源布线（109和110）; 以及提供给电源配线（109和110）的陷波滤波器（107和108），用于衰减对应于时钟信号频率的频率分量。

    Optical transceiver module
    60.
    发明授权
    Optical transceiver module 有权
    光收发模块

    公开(公告)号：US07703994B2

    公开(公告)日：2010-04-27

    申请号：US12338205

    申请日：2008-12-18

    申请人： Osamu Kagaya ,  Hiroyoshi Ishii ,  Yasushi Kitajima

    发明人： Osamu Kagaya ,  Hiroyoshi Ishii ,  Yasushi Kitajima

    IPC分类号： G02B6/36

    CPC分类号： G02B6/4201 ,  G02B6/4246 ,  G02B6/4277

    摘要： Provided is a metal casing structure capable of avoiding a cavity resonance at 10 GHz and 20 GHz by controlling an eigenmode frequency in an inner space of a casing without involving an increase in cost, and a 10 Gbit/s optical transceiver module which achieves reduction in unnecessary electromagnetic waves and cost. In the optical transceiver module, a metal casing having a cavity therein is formed by an upper casing (100) and a lower casing (101), a metal partition wall (103, 104) is provided on at least one of the upper casing (100) and the lower casing (101) near a central portion of the casing in a direction parallel to a direction connecting a front and a rear thereof, and a length of a gap between the partition wall (103, 104) and a printed circuit board (102) is adjusted.

    摘要翻译： 提供一种金属外壳结构，能够通过控制壳体的内部空间中的本征模式频率而不涉及成本增加来避免10GHz和20GHz的谐振腔谐振，以及实现减少的10Gbit / s的光收发模块 不必要的电磁波和成本。 在光收发器模块中，由上壳体（100）和下壳体（101）形成具有空腔的金属壳体，金属隔壁（103,104）设置在上壳体 100）和下壳体（101）在与连接其前后方向平行的方向上的壳体的中心部分附近，以及间隔壁（103,104）和印刷电路 板（102）被调整。