公开(公告)号：US10262942B2

公开(公告)日：2019-04-16

申请号：US15661029

申请日：2017-07-27

Applicant: GLOBALFOUNDRIES INC.

Inventor： Qiang Fang ,  Haigou Huang ,  Shafaat Ahmed ,  Changhong Wu ,  Dinesh R. Koli

IPC: H01L21/4763 ,  H01L23/12 ,  H01L23/532 ,  H01L21/768 ,  H01L21/288 ,  H01L21/285 ,  H01L21/3213

Abstract: The disclosure relates to a method of forming a Co contact module, the method including depositing a liner layer on a trench block, partially plating the lined trenches with Co as a first metal such that the resulting Co layer has a top surface below an opening top surface of a shallowest trench, depositing a second metal on the Co layer and exposed surfaces of the liner layer, planarizing the second metal layer, and etching the second metal layer and portions of the liner layer. The disclosure also relates to a Co contact module formed by the noted method.

公开(公告)号：US10217846B1

公开(公告)日：2019-02-26

申请号：US15873156

申请日：2018-01-17

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ruilong Xie ,  Steven Bentley ,  Min Gyu Sung ,  Chanro Park ,  Steven Soss ,  Hui Zang ,  Xusheng Wu ,  Yi Qi ,  Ajey P. Jacob ,  Murat K. Akarvardar ,  Siva P. Adusumilli ,  Jiehui Shu ,  Haigou Huang ,  John H. Zhang

IPC: H01L21/00 ,  H01L21/8238 ,  H01L21/336 ,  H01L29/66 ,  H01L21/02 ,  H01L29/423 ,  H01L29/165 ,  H01L29/16 ,  H01L29/78

Abstract: Disclosed are a method of forming vertical field effect transistor(s) and the resulting structure. In the method, five semiconductor layers are formed in a stack by epitaxial deposition. The first and fifth layers are one semiconductor material, the second and fourth layers are another and the third layer is yet another. The stack is patterned into fin(s). Vertical surfaces of the second and fourth layers of the fin(s) are etched to form upper and lower spacer cavities and these cavities are filled with upper and lower spacers. Vertical surfaces of the third layer of the fin(s) are etched to form a gate cavity and this cavity is filled with a gate. Since epitaxial deposition is used to form the semiconductor layers, the thicknesses of these layers and thereby the heights of the spacer cavities and gate cavity and the corresponding lengths of the spacers and gate can be precisely controlled.

公开(公告)号：US10211103B1

公开(公告)日：2019-02-19

申请号：US15787257

申请日：2017-10-18

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Haigou Huang ,  Dinesh Koli ,  Yuan Zhou ,  Xingzhao Shi ,  Chih-Chiang Chang ,  Tai Fong Chao

IPC: H01L21/28 ,  H01L21/768 ,  H01L29/66 ,  H01L23/522 ,  H01L23/532

Abstract: Methods of forming a SAC cap with SiN U-shaped and oxide T-shaped structures and the resulting devices are provided. Embodiments include forming a substrate with a trench and a plurality of gate structures; forming a nitride liner over portions of the substrate and along sidewalls of each gate structure; forming an ILD between each gate structure and in the trench; recessing each gate structure between the ILD; forming a U-shaped nitride liner over each recessed gate structure; forming an a-Si layer over the nitride liner and the U-shaped nitride liner; removing portions of the nitride liner, the U-shaped nitride liner and the a-Si layer; forming a W layer over portions of the substrate adjacent to and between the a-Si layer; forming an oxide liner over the nitride liner, the U-shaped nitride liner and along sidewalls of the W layer; and forming an oxide layer over portions of the oxide liner.

公开(公告)号：US10204797B1

公开(公告)日：2019-02-12

申请号：US15890210

申请日：2018-02-06

Applicant: GLOBALFOUNDRIES INC.

Inventor： Jinsheng Gao ,  Daniel Jaeger ,  Michael Aquilino ,  Patrick Carpenter ,  Junsic Hong ,  Jessica Dechene ,  Haigou Huang

IPC: H01L21/00 ,  H01L21/3105 ,  H01L21/02 ,  C23C16/36 ,  H01L21/67 ,  C23C16/56 ,  C23C16/26

Abstract: The disclosed methods may include depositing an amorphous carbon layer, a SiCN layer, and a TEOS layer; planarizing the semiconductor structure; performing a non-selective etch to remove the SiCN layer, the TEOS layer, and a portion of the amorphous carbon layer; and performing a selective etch of the amorphous carbon layer. The methods may reduce step height differences between first and second regions of the semiconductor structure.

公开(公告)号：US10204784B1

公开(公告)日：2019-02-12

申请号：US15797633

申请日：2017-10-30

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jinsheng Gao ,  Hui Zang ,  Haigou Huang

IPC: H01L21/033 ,  H01L29/66 ,  H01L21/308 ,  H01L21/8238 ,  H01L27/092

Abstract: One illustrative method disclosed herein includes, among other things, forming an initial patterned etch mask above a feature-formation etch mask, the initial patterned etch mask including a plurality of laterally spaced-apart features having a non-uniform spacing, and performing at least one first etching process to remove an entire axial length of at least one of the plurality of features so as to thereby form a modified final patterned etch mask comprised of a plurality of features with a uniform spacing that defines a feature-formation pattern. In this example, the method also includes performing at least one second etching process so as to form a patterned feature-formation etch mask comprising the feature-formation pattern and performing at least one third etching process so as to form a plurality of features in a first layer, the features being formed with the feature-formation pattern.

公开(公告)号：US10103238B1

公开(公告)日：2018-10-16

申请号：US15652890

申请日：2017-07-18

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui Zang ,  Tek Po Rinus Lee ,  Haigou Huang ,  Ruilong Xie ,  Min Gyu Sung ,  Chanro Park

IPC: H01L21/336 ,  H01L29/423 ,  H01L29/66 ,  H01L21/768 ,  H01L29/06 ,  H01L21/311 ,  H01L29/786 ,  H01L21/02

Abstract: Methods for forming a structure for a nanosheet field-effect transistor. A body feature is formed that includes a plurality of nanosheet channel layers and a plurality of first sacrificial layers that are alternatingly arranged with the nanosheet channel layers. The body feature is located on a second sacrificial layer. The first sacrificial layers are recessed relative to the nanosheet channel layers to form a plurality of first cavities indented into a sidewall of the body feature. A plurality of dielectric spacers are formed that fill the first cavities. After forming the dielectric spacers, the second sacrificial layer is removed with an etching process to define a second cavity that extends completely beneath the body feature. A dielectric layer is formed in the second cavity.

公开(公告)号：US20180286965A1

公开(公告)日：2018-10-04

申请号：US15475272

申请日：2017-03-31

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hui Zang ,  Haigou Huang

IPC: H01L29/66 ,  H01L21/28 ,  H01L21/02 ,  H01L21/321 ,  H01L29/49 ,  H01L21/3105

Abstract: The disclosure is directed to methods of forming an integrated circuit structure. One method may include: forming a metal gate within a dielectric layer over a substrate; forming an opening within the metal gate; recessing the metal gate such that a height of the metal gate is reduced; forming an insulator over the recessed metal gate and filling the opening; and planarizing the insulator to a top surface of the dielectric layer.

公开(公告)号：US09837553B1

公开(公告)日：2017-12-05

申请号：US15282415

申请日：2016-09-30

Applicant: GLOBALFOUNDRIES INC.

Inventor： Xusheng Wu ,  John H. Zhang ,  Haigou Huang

IPC: H01L29/786 ,  H01L29/423 ,  H01L29/66

CPC classification number: H01L29/78696 ,  H01L29/0847 ,  H01L29/42372 ,  H01L29/66666 ,  H01L29/7827 ,  H01L29/78618 ,  H01L29/78642

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to vertical field effect transistors (VFETs) and methods of manufacture. The VFET includes: one or more vertical fin structures; a source region positioned at a first location on a top surface of the one or more vertical fin structures; a drain region positioned at a second location on the top surface of the one or more vertical fin structures at a predetermined distance away from the source region, along a length thereof; and a gate channel along the predetermined distance and in electrical contact with the source region and the drain region.

公开(公告)号：US20170345913A1

公开(公告)日：2017-11-30

申请号：US15165294

申请日：2016-05-26

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xintuo Dai ,  Haigou Huang ,  Xusheng Wu

IPC: H01L29/66 ,  H01L29/78

CPC classification number: H01L29/66545 ,  H01L29/66795 ,  H01L29/7851

Abstract: A method includes forming a placeholder gate structure embedded in a dielectric layer. The placeholder gate structure includes a sacrificial material. A first hard mask layer is formed above the dielectric layer. The first hard mask layer and the sacrificial material are the same material. A second hard mask layer is formed above the first hard mask layer. The second hard mask layer is patterned to define an opening therein exposing a portion of the first hard mask layer and being disposed above a portion of the placeholder gate structure. The exposed portion of the first hard mask layer and the portion of the sacrificial material of the placeholder gate structure disposed below the opening are removed to define a gate cut cavity and divide the placeholder gate structure into first and second segments. A dielectric material is formed in the gate cut cavity.

公开(公告)号：US09589807B1

公开(公告)日：2017-03-07

申请号：US15164146

申请日：2016-05-25

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Haigou Huang ,  Jinping Liu ,  Huang Liu ,  Yuanfang Lu

IPC: H01L21/283 ,  H01L21/762 ,  H01L21/3213 ,  H01L29/66

CPC classification number: H01L21/283 ,  H01L21/32137 ,  H01L21/76224 ,  H01L21/76837 ,  H01L21/7684 ,  H01L29/66545 ,  H01L29/6656

Abstract: A method for eliminating interlayer dielectric (ILD) dishing and controlling gate height uniformity is provided. Embodiments include forming a plurality of polysilicon gates over a substrate, each gate having spacers formed on sides of the polysilicon gates and a nitride cap formed on an upper surface; forming a gapfill material between adjacent polysilicon gates; forming an oxide over the gapfill material between the adjacent polysilicon gates; removing the nitride caps; removing a portion of the oxide between the adjacent polysilicon gates, forming a recess; and forming an ILD cap layer in the recess between the adjacent polysilicon gates.

Abstract translation: 提供消除层间电介质（ILD）凹陷并控制栅极高度均匀性的方法。 实施例包括在衬底上形成多个多晶硅栅极，每个栅极具有形成在多晶硅栅极侧面上的隔离物和形成在上表面上的氮化物盖; 在相邻的多晶硅栅极之间形成间隙填充材料; 在相邻的多晶硅栅极之间的间隙填充材料上形成氧化物; 去除氮化物盖; 去除相邻多晶硅栅极之间的氧化物的一部分，形成凹陷; 以及在相邻的多晶硅栅极之间的凹槽中形成ILD覆盖层。