公开(公告)号：US20090305486A1

公开(公告)日：2009-12-10

申请号：US12482101

申请日：2009-06-10

申请人： Hans-Joachim Schulze ,  Helmut Strack ,  Hans-Joerg Timme ,  Rainer Winkler

发明人： Hans-Joachim Schulze ,  Helmut Strack ,  Hans-Joerg Timme ,  Rainer Winkler

IPC分类号： H01L21/20

CPC分类号： H01L29/04 ,  C30B25/18 ,  C30B29/06 ,  C30B33/02 ,  H01L21/02381 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/02543 ,  H01L21/02546 ,  H01L21/02658 ,  H01L21/263 ,  H01L21/3225 ,  H01L29/0657

摘要： A method for producing a semiconductor layer is disclosed. One embodiment provides for a semiconductor layer on a semiconductor substrate containing oxygen. Crystal defects are produced at least in a near-surface region of the semiconductor substrate. A thermal process is carried out wherein the oxygen is taken up at the crystal defects. The semiconductor layer is deposited epitaxially over the near-surface region of the semiconductor substrate.

摘要翻译： 公开了半导体层的制造方法。 一个实施例提供了含有氧的半导体衬底上的半导体层。 晶体缺陷至少在半导体衬底的近表面区域产生。 进行热处理，其中氧被吸收在晶体缺陷处。 外延在半导体衬底的近表面区域上沉积半导体层。

公开(公告)号：US20090087632A1

公开(公告)日：2009-04-02

申请号：US11864584

申请日：2007-09-28

申请人： Hans-Joachim Schulze ,  Hans-Joerg Timme ,  Helmut Strack

发明人： Hans-Joachim Schulze ,  Hans-Joerg Timme ,  Helmut Strack

IPC分类号： B32B7/02 ,  B05D5/12

CPC分类号： H01L21/26506 ,  H01L21/263 ,  H01L21/3221 ,  Y10T428/2495 ,  Y10T428/26

摘要： A wafer includes a wafer frontside surface and a region adjacent to the wafer frontside surface. The region includes oxygen precipitates and the wafer frontside includes a predetermined surface structure to form thereon a device with a desired property.

摘要翻译： 晶片包括晶片前侧表面和与晶片前侧表面相邻的区域。 该区域包括氧沉淀物，并且晶片正面包括预定的表面结构以在其上形成具有所需性质的器件。

公开(公告)号：US20050212076A1

公开(公告)日：2005-09-29

申请号：US11081787

申请日：2005-03-16

申请人： Hans-Joachim Schulze ,  Helmut Strack

发明人： Hans-Joachim Schulze ,  Helmut Strack

IPC分类号： H01L23/482 ,  H01L29/00 ,  H01L29/417 ,  H01L29/43 ,  H01L29/739 ,  H01L29/861

CPC分类号： H01L29/7395 ,  H01L23/4827 ,  H01L29/41741 ,  H01L2224/04026 ,  H01L2924/01068 ,  H01L2924/01322 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/00

摘要： The invention relates to a power semiconductor component with increased robustness, in which a contact layer (13, 14) applied directly to a main surface (7, 11) of the semiconductor body (1) is composed of a metal (13) having a high melting point or of a thin aluminum layer (14), the layer thickness of which preferably lies between 1 and 5 nm. This contact layer is reinforced with a customary multilayer metallization system (15). The aluminum layer may, if appropriate, be patterned (14′).

摘要翻译： 本发明涉及具有增强的鲁棒性的功率半导体部件，其中直接施加于半导体本体（1）的主表面（7,11）的接触层（13,14）由金属（13）组成，金属（13）具有 高熔点或薄铝层（14），其厚度优选在1至5nm之间。 该接触层用常规的多层金属化系统（15）加固。 如果合适，铝层可以被图案化（14'）。

公开(公告)号：US20120019284A1

公开(公告)日：2012-01-26

申请号：US12843181

申请日：2010-07-26

申请人： Anton Mauder ,  Helmut Strack ,  Wolfgang Werner

发明人： Anton Mauder ,  Helmut Strack ,  Wolfgang Werner

IPC分类号： H03K19/094 ,  H01L21/336 ,  H01L29/792 ,  H01L29/78

CPC分类号： H01L29/7828 ,  H01L29/0623 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/402 ,  H01L29/408 ,  H01L29/51 ,  H01L29/513 ,  H01L29/66068 ,  H01L29/66666 ,  H01L29/7787 ,  H01L29/7838 ,  H01L29/788 ,  H01L29/792

摘要： A normally-off power field-effect transistor semiconductor structure is provided. The structure includes a channel, a source electrode, a gate electrode and trapped charges which arranged between the gate electrode and the channel such that the channel is in an off-state when the source electrode and the gate electrode are on the same electric potential. Further, a method for forming a semiconductor device and a method for programming a power field effect transistor are provided.

摘要翻译： 提供了常关的功率场效应晶体管半导体结构。 该结构包括沟道，源电极，栅电极和被布置在栅电极和沟道之间的俘获电荷，使得当源电极和栅电极处于相同电位时，沟道处于截止状态。 此外，提供了一种用于形成半导体器件的方法和用于编程功率场效应晶体管的方法。

公开(公告)号：US20070099373A1

公开(公告)日：2007-05-03

申请号：US11638612

申请日：2006-12-13

申请人： Franz Hirler ,  Helmut Strack

发明人： Franz Hirler ,  Helmut Strack

IPC分类号： H01L21/8238

CPC分类号： H01L29/7802 ,  H01L29/0847 ,  H01L29/086 ,  H01L29/1604 ,  H01L29/165 ,  H01L29/41766 ,  H01L29/7813

摘要： To attain a comparatively high breakdown voltage at a high avalanche strength and with the physical size simultaneously being as small as possible, the invention proposes constructing a transistor device in a semiconductor material region in which a first source/drain region is used as a source region and in which the source region has a comparatively reduced surface charge or surface charge density.

摘要翻译： 为了在高雪崩强度下获得相当高的击穿电压并且物理尺寸同时尽可能小，本发明提出在其中使用第一源极/漏极区域作为源极区域的半导体材料区域中构造晶体管器件 并且其中源区具有相对减小的表面电荷或表面电荷密度。

公开(公告)号：US06670244B2

公开(公告)日：2003-12-30

申请号：US09943538

申请日：2001-08-30

申请人： Helmut Gassel ,  Werner Kanert ,  Helmut Strack ,  Franz Hirler ,  Herbert Pairitsch

发明人： Helmut Gassel ,  Werner Kanert ,  Helmut Strack ,  Franz Hirler ,  Herbert Pairitsch

IPC分类号： H01L21336

CPC分类号： H01L29/7802 ,  H01L29/0634 ,  H01L29/1095 ,  H01L29/66333 ,  H01L29/66348 ,  H01L29/66712 ,  H01L29/66734 ,  H01L29/7397 ,  H01L29/7813

摘要： A method is provided for fabricating a body region of a first conduction type for a vertical MOS transistor configuration in a semiconductor body such that the body region has a reduced resistivity without a corresponding reduction in the breakdown voltage of the transistor. The method includes, inter alia: performing a first implantation of a doping material of a first conduction type into the semiconductor body such that an implantation maximum of the first implantation lies within the semiconductor body set back from the channel region; and performing a second implantation of a doping material of the first conduction type such that an implantation maximum of the second implantation lies within the semiconductor body below the implantation maximum of the first implantation. The dose of the second implantation is less than the dose of the first implantation.

公开(公告)号：US08415219B2

公开(公告)日：2013-04-09

申请号：US11638612

申请日：2006-12-13

申请人： Franz Hirler ,  Helmut Strack

发明人： Franz Hirler ,  Helmut Strack

IPC分类号： H01L21/336

CPC分类号： H01L29/7802 ,  H01L29/0847 ,  H01L29/086 ,  H01L29/1604 ,  H01L29/165 ,  H01L29/41766 ,  H01L29/7813

摘要： To attain a comparatively high breakdown voltage at a high avalanche strength and with the physical size simultaneously being as small as possible, the invention proposes constructing a transistor device in a semiconductor material region in which a first source/drain region is used as a source region and in which the source region has a comparatively reduced surface charge or surface charge density.

摘要翻译： 为了在高雪崩强度下获得相当高的击穿电压并且物理尺寸同时尽可能小，本发明提出在其中使用第一源极/漏极区域作为源极区域的半导体材料区域中构造晶体管器件 并且其中源区具有相对减小的表面电荷或表面电荷密度。

公开(公告)号：US4893165A

公开(公告)日：1990-01-09

申请号：US313045

申请日：1989-02-21

申请人： Gerhard Miller ,  Helmut Strack ,  Jenoe Tihanyi

发明人： Gerhard Miller ,  Helmut Strack ,  Jenoe Tihanyi

IPC分类号： H01L29/68 ,  H01L29/08 ,  H01L29/45 ,  H01L29/739 ,  H01L29/78

CPC分类号： H01L29/7395 ,  H01L29/0834 ,  H01L29/456

摘要： A field effect controllable bipolar transistor or isolated gate bipolar transistor (IGBT) has a drastically reduced inhibit delay charge, given identical on-state behavior, in that the anode zone has a thickness of less that 1 micrometer, it is doped with implanted ions with a dose of about 1.times.10.sup.12 through 1.times.10.sup.15 cm.sup.-2, and in that the life time of the minority charge carriers in the inner zone amounts to at least 1 microsecond.

摘要翻译： 给定相同的导通状态，场效应可控双极晶体管或隔离栅双极晶体管（IGBT）具有显着降低的抑制延迟电荷，因为阳极区具有小于1微米的厚度，其掺杂有注入离子 约1×10 12至1×10 15 cm -2的剂量，并且内区中少数电荷载体的寿命至少为1微秒。

公开(公告)号：US07947532B2

公开(公告)日：2011-05-24

申请号：US12850902

申请日：2010-08-05

申请人： Ralf Otremba ,  Helmut Strack

发明人： Ralf Otremba ,  Helmut Strack

IPC分类号： H01L21/50 ,  H01L21/44

CPC分类号： H01L23/5389 ,  H01L23/49524 ,  H01L23/49537 ,  H01L23/49562 ,  H01L23/49575 ,  H01L23/49861 ,  H01L24/24 ,  H01L24/37 ,  H01L24/40 ,  H01L24/41 ,  H01L24/48 ,  H01L24/73 ,  H01L24/82 ,  H01L25/071 ,  H01L2224/06181 ,  H01L2224/24226 ,  H01L2224/32245 ,  H01L2224/371 ,  H01L2224/40 ,  H01L2224/40245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/48472 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/82039 ,  H01L2224/83801 ,  H01L2224/83825 ,  H01L2224/8384 ,  H01L2224/8385 ,  H01L2224/83855 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01068 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/351 ,  H01L2224/8382 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A power semiconductor device and a method for its production. The power semiconductor device has at least one power semiconductor chip, which has on its top side and on its back side large-area electrodes. The electrodes are electrically in connection with external contacts by means of connecting elements, the power semiconductor chip and the connecting elements being embedded in a plastic package. This plastic package has a number of layers of plastic, which are pressed one on top of the other and have plane-parallel upper sides. The connecting elements are arranged on at least one of the plane-parallel upper sides, between the layers of plastic pressed one on top of the other, as a patterned metal layer and are electrically in connection with the external contacts by means of contact vias through at least one of the layers of plastic.

摘要翻译： 一种功率半导体器件及其制造方法。 功率半导体器件具有至少一个功率半导体芯片，其在其顶侧和其后侧具有大面积电极。 电极通过连接元件与外部触点电连接，功率半导体芯片和连接元件嵌入塑料封装中。 该塑料包装具有多个塑料层，它们一个被压在另一个之上并具有平面平行的上侧。 连接元件布置在至少一个平面平行的上侧，在塑料层之间压迫的层之间，作为图案化的金属层，并且通过接触通孔与外部触点电连接 塑料层中的至少一层。

公开(公告)号：US07759163B2

公开(公告)日：2010-07-20

申请号：US12105837

申请日：2008-04-18

申请人： Werner Kroeninger ,  Josef Schwaiger ,  Ludwig Schneider ,  Ottmar Geitner ,  Markus Brunnbauer ,  Thorsten Meyer ,  Ralf Otremba ,  Josef Hoeglauer ,  Helmut Strack ,  Xaver Schloegel

发明人： Werner Kroeninger ,  Josef Schwaiger ,  Ludwig Schneider ,  Ottmar Geitner ,  Markus Brunnbauer ,  Thorsten Meyer ,  Ralf Otremba ,  Josef Hoeglauer ,  Helmut Strack ,  Xaver Schloegel

IPC分类号： H01L21/00 ,  H01L23/48

CPC分类号： H01L21/568 ,  H01L21/6835 ,  H01L23/3107 ,  H01L24/25 ,  H01L24/82 ,  H01L24/96 ,  H01L24/97 ,  H01L25/072 ,  H01L2221/68345 ,  H01L2224/04105 ,  H01L2224/06181 ,  H01L2224/12105 ,  H01L2224/2518 ,  H01L2224/32245 ,  H01L2224/73153 ,  H01L2224/73267 ,  H01L2224/76155 ,  H01L2224/82039 ,  H01L2224/82047 ,  H01L2224/82102 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01068 ,  H01L2924/01072 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/12032 ,  H01L2924/12044 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2224/82 ,  H01L2924/00

摘要： A semiconductor module. One embodiment provides at least two semiconductor chips placed on a carrier. The at least two semiconductor chips are then covered with a molding material to form a molded body. The molded body is thinned until the at least two semiconductor chips are exposed. Then, the carrier is removed from the at least two semiconductor chips. The at least two semiconductor chips are singulated.

摘要翻译： 半导体模块。 一个实施例提供放置在载体上的至少两个半导体芯片。 然后将至少两个半导体芯片用模制材料覆盖以形成模制体。 成型体变薄，直到暴露出至少两个半导体芯片。 然后，从至少两个半导体芯片移除载体。 将至少两个半导体芯片分割。