公开(公告)号：US10802532B2

公开(公告)日：2020-10-13

申请号：US16429872

申请日：2019-06-03

Applicant: Intel Corporation

Inventor： George Vergis ,  Kuljit S. Bains ,  Bill Nale

IPC: G06F1/06 ,  G06F13/42 ,  G11C7/10 ,  G11C5/04 ,  H01L23/00 ,  G11C5/06 ,  G06F3/06 ,  G06F12/00

Abstract: Examples include techniques to mirror a command/address or interpret command/address logic at a memory device. A memory device located on a dual in-line memory module (DIMM) may include circuitry having logic capable of receiving a command/address signal and mirror a command/address or interpret command/address logic indicated in the command/address signal based on one or more strap pins for the memory device.

公开(公告)号：US10592445B2

公开(公告)日：2020-03-17

申请号：US16208224

申请日：2018-12-03

Applicant: Intel Corporation

Inventor： Bill Nale ,  Christopher E. Cox ,  Kuljit S. Bains ,  George Vergis ,  James A. McCall ,  Chong J. Zhao ,  Suneeta Sah ,  Pete D. Vogt ,  John R. Goles

IPC: G06F11/16 ,  G06F13/16 ,  G11C11/4096 ,  G06F13/40 ,  G11C14/00 ,  G11C5/04 ,  G11C7/10

Abstract: Examples include techniques to access or operate a dual in-line memory module (DIMM) via one or multiple data channels. In some examples, memory devices at or on the DIMM may be accessed via one or more data channels. The one or more data channels arranged such that the DIMM is configured to operate in a dual channel mode that includes two data channels or to operate in a single channel mode that includes a single data channel.

公开(公告)号：US10395722B2

公开(公告)日：2019-08-27

申请号：US15721052

申请日：2017-09-29

Applicant: Intel Corporation

Inventor： Christopher E. Cox ,  Bill Nale

IPC: G11C8/18 ,  G11C11/4076 ,  G06F12/06 ,  G11C7/22 ,  G11C11/409 ,  G06F13/16 ,  G11C7/10 ,  G11C8/06

Abstract: A system provides a mailbox communication register for communication between a host and a mode register. The mode register is to store configuration information, and write of configuration information to the mode register by the host takes less time than a read of the configuration information from the mode register by the host. The communication register is separate from the mode register and provides a location to store the configuration information for a read by the host. In response to a read request by the host, the mode register can copy the configuration information to the communication register and allow the host to read the register based on different timing rules than those that apply to the mode register. Instead of reading directly from a register that has timing variance between read and write, the host can read from a communication register.

公开(公告)号：US20180189207A1

公开(公告)日：2018-07-05

申请号：US15857992

申请日：2017-12-29

Applicant: Intel Corporation

Inventor： Bill Nale ,  Raj K. Ramanujan ,  Muthukumar P. Swaminathan ,  Tessil Thomas ,  Taarinya Polepeddi

IPC: G06F13/16 ,  G06F13/40 ,  G06F13/42

CPC classification number: G06F13/1694 ,  G06F9/467 ,  G06F11/1064 ,  G06F12/0238 ,  G06F12/0802 ,  G06F12/0804 ,  G06F12/0811 ,  G06F12/0868 ,  G06F12/0897 ,  G06F13/1668 ,  G06F13/4068 ,  G06F13/42 ,  G06F13/4234 ,  G06F2212/1008 ,  G06F2212/1016 ,  G06F2212/1044 ,  G06F2212/2024 ,  G06F2212/7203 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/151

Abstract: A semiconductor chip comprising memory controller circuitry having interface circuitry to couple to a memory channel. The memory controller includes first logic circuitry to implement a first memory channel protocol on the memory channel. The first memory channel protocol is specific to a first volatile system memory technology. The interface also includes second logic circuitry to implement a second memory channel protocol on the memory channel. The second memory channel protocol is specific to a second non volatile system memory technology. The second memory channel protocol is a transactional protocol

公开(公告)号：US20180181504A1

公开(公告)日：2018-06-28

申请号：US15389462

申请日：2016-12-23

Applicant: Intel Corporation

Inventor： Tonia Morris ,  John Van Lovelace ,  Christopher Mozak ,  Bill Nale

IPC: G06F13/16 ,  G06F3/06 ,  G11C11/4076 ,  G11C11/4093

CPC classification number: G06F13/1689 ,  G06F12/0238 ,  G06F12/0868 ,  G06F13/1673 ,  G06F2212/7203 ,  G11C5/04 ,  G11C11/4076 ,  G11C11/4093

Abstract: The present disclosure relates to an apparatus for training one or more signal timing relations of a control interface between a registering clock driver and one or more data buffers of a memory module comprising a plurality of memory chips, the control interface comprising a clock signal and at least one control signal. The apparatus includes control circuitry which is configured to adjust a relative timing between the at least one control signal and the clock signal based on samples of the at least one control signal sampled based on the clock signal

公开(公告)号：US09990246B2

公开(公告)日：2018-06-05

申请号：US13977653

申请日：2013-03-15

Applicant: Intel Corporation

Inventor： Bill Nale ,  Murugasamy K. Nachimuthu ,  Jun Zhu ,  Tuan M. Quach

IPC: G06F12/00 ,  G06F11/07 ,  G11C29/02 ,  G06F12/0813 ,  G06F13/16 ,  G06F3/06 ,  G06F12/0802 ,  G06F12/02 ,  G06F13/42 ,  G11C7/22 ,  G11C11/406 ,  G11C5/14 ,  H04L9/08 ,  G11C5/04 ,  G11C7/10

CPC classification number: G06F11/0793 ,  G06F3/0604 ,  G06F3/061 ,  G06F3/0629 ,  G06F3/0638 ,  G06F3/0673 ,  G06F3/0683 ,  G06F11/0727 ,  G06F11/0751 ,  G06F11/0772 ,  G06F11/079 ,  G06F12/023 ,  G06F12/0802 ,  G06F12/0813 ,  G06F13/1663 ,  G06F13/1678 ,  G06F13/1689 ,  G06F13/1694 ,  G06F13/4234 ,  G06F13/4243 ,  G06F13/4282 ,  G06F2212/1044 ,  G06F2212/2532 ,  G06F2212/60 ,  G11C5/04 ,  G11C5/148 ,  G11C7/1003 ,  G11C7/1063 ,  G11C7/1072 ,  G11C7/222 ,  G11C11/40618 ,  G11C29/023 ,  G11C29/028 ,  H04L9/0869

Abstract: Provided is a device for use in a memory module coupled to a host memory controller over a bus, comprising memory module control logic to generate a request signal to a host memory controller having a pulse width greater than or equal to a minimum pulse width, wherein the minimum pulse width comprises a number of clock cycles needed to guarantee that the host memory controller detects the request signal, and wherein the pulse width of the request signal indicates at least one function in addition to the request signal to the host memory controller.

公开(公告)号：US20180060259A1

公开(公告)日：2018-03-01

申请号：US15669197

申请日：2017-08-04

Applicant: Intel Corporation

Inventor： Brian S. Morris ,  Bill Nale ,  Robert G. Blankenship ,  Jeffrey C. Swanson

IPC: G06F13/28 ,  G06F13/42 ,  G06F13/16 ,  G06F13/38

CPC classification number: G06F13/28 ,  G06F13/1642 ,  G06F13/382 ,  G06F13/4221

Abstract: A sequence of read returns are to be sent to a host device over a transactional buffered memory interface, where the sequence includes at least a first read return to a first read request and a second read return to a second read request. A tracker identifier of the second read return is encoded in the first read return and the first read return is sent with the tracker identifier of the second read return to the host device. The second read return is sent to the host device after the first read return is sent.

公开(公告)号：US20180018267A1

公开(公告)日：2018-01-18

申请号：US15602996

申请日：2017-05-23

Applicant: Intel Corporation

Inventor： Brian S. Morris ,  Bill Nale ,  Robert G. Blankenship ,  Yen-Cheng Liu

IPC: G06F12/0862 ,  G06F12/0831

CPC classification number: G06F12/0862 ,  G06F12/0835 ,  G06F12/0884 ,  G06F2212/1016 ,  G06F2212/507 ,  G06F2212/6026 ,  Y02D10/13

Abstract: A speculative read request is received from a host device over a buffered memory access link for data associated with a particular address. A read request is sent for the data to a memory device. The data is received from the memory device in response to the read request and the received data is sent to the host device as a response to a demand read request received subsequent to the speculative read request.

公开(公告)号：US09852021B2

公开(公告)日：2017-12-26

申请号：US14967226

申请日：2015-12-11

Applicant: INTEL CORPORATION

Inventor： Bill Nale ,  John V. Lovelace ,  Murugasamy M. Nachimuthu ,  Tuan M. Quach

IPC: G06F12/00 ,  G06F11/07 ,  G11C29/02 ,  G06F12/0813 ,  G06F13/16 ,  G06F3/06 ,  G06F12/0802 ,  G06F12/02 ,  G06F13/42 ,  G11C7/22 ,  G11C11/406 ,  G11C5/14 ,  H04L9/08 ,  G11C5/04 ,  G11C7/10

CPC classification number: G06F11/0793 ,  G06F3/0604 ,  G06F3/061 ,  G06F3/0629 ,  G06F3/0638 ,  G06F3/0673 ,  G06F3/0683 ,  G06F11/0727 ,  G06F11/0751 ,  G06F11/0772 ,  G06F11/079 ,  G06F12/023 ,  G06F12/0802 ,  G06F12/0813 ,  G06F13/1663 ,  G06F13/1678 ,  G06F13/1689 ,  G06F13/1694 ,  G06F13/4234 ,  G06F13/4243 ,  G06F13/4282 ,  G06F2212/1044 ,  G06F2212/2532 ,  G06F2212/60 ,  G11C5/04 ,  G11C5/148 ,  G11C7/1003 ,  G11C7/1063 ,  G11C7/1072 ,  G11C7/222 ,  G11C11/40618 ,  G11C29/023 ,  G11C29/028 ,  H04L9/0869

Abstract: Provided are a method and apparatus for method and apparatus for encoding registers in a memory module. A mode register command is sent to the memory module over a bus, initialization of the memory module before the bus to the memory module is trained for bus operations, to program one of a plurality of mode registers in the memory module, wherein the mode register command indicates one of the mode registers and includes data for the indicated mode register.

公开(公告)号：US20170255404A1

公开(公告)日：2017-09-07

申请号：US15266991

申请日：2016-09-15

Applicant: Intel Corporation

Inventor： George Vergis ,  Kuljit S. Bains ,  Bill Nale

IPC: G06F3/06

CPC classification number: G06F13/4243 ,  Y02D10/14 ,  Y02D10/151

Abstract: Examples include techniques to mirror a command/address or interpret command/address logic at a memory device. A memory device located on a dual in-line memory module (DIMM) may include circuitry having logic capable of receiving a command/address signal and mirror a command/address or interpret command/address logic indicated in the command/address signal based on one or more strap pins for the memory device.