公开(公告)号：US09917175B1

公开(公告)日：2018-03-13

申请号：US15581140

申请日：2017-04-28

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Karthik Balakrishnan ,  Kangguo Cheng ,  Pouya Hashemi ,  Alexander Reznicek

IPC: H01L29/10 ,  H01L29/66 ,  H01L21/02 ,  H01L21/3213

CPC classification number: H01L29/7827 ,  H01L21/02546 ,  H01L21/32133 ,  H01L29/0657 ,  H01L29/0847 ,  H01L29/20 ,  H01L29/517 ,  H01L29/66522 ,  H01L29/66545 ,  H01L29/66666 ,  H01L29/66977

Abstract: A vertical field effect transistor includes a first source/drain region formed on or in a substrate. A tapered fin is formed a vertical device channel and has a first end portion attached to the first source/drain region. A second source/drain region is formed on a second end portion of the tapered fin. A gate structure surrounds the tapered fin.

公开(公告)号：US09875896B2

公开(公告)日：2018-01-23

申请号：US15258144

申请日：2016-09-07

Applicant: International Business Machines Corporation

Inventor： Karthik Balakrishnan ,  Kangguo Cheng ,  Pouya Hashemi ,  Alexander Reznicek

IPC: H01L21/784 ,  H01L21/02 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/324 ,  H01L21/3105

CPC classification number: H01L21/02694 ,  H01L21/02164 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02488 ,  H01L21/02505 ,  H01L21/02532 ,  H01L21/02639 ,  H01L21/28255 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/32055 ,  H01L21/324 ,  H01L21/7624 ,  H01L21/76264 ,  H01L21/76283 ,  H01L29/0649 ,  H01L29/0692 ,  H01L29/1054 ,  H01L29/161 ,  H01L29/165 ,  H01L29/267 ,  H01L29/7378 ,  H01L29/7848 ,  H01L29/785 ,  H01L31/1816 ,  H01L2924/10271

Abstract: A semiconductor device comprising a substrate having a region protruding from the substrate surface; a relaxed semiconductor disposed on the region; an additional semiconductor disposed on the relaxed semiconductor; and low density dielectric disposed next to and at least partially underneath the relaxed semiconductor and adjacent to the protruding region of the substrate.

公开(公告)号：US09859301B1

公开(公告)日：2018-01-02

申请号：US15177941

申请日：2016-06-09

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Karthik Balakrishnan ,  Kangguo Cheng ,  Pouya Hashemi ,  Alexander Reznicek

IPC: H01L21/00 ,  H01L27/12 ,  H01L29/78 ,  H01L29/66 ,  H01L29/16 ,  H01L29/06 ,  H01L29/165 ,  H01L21/02 ,  H01L21/84 ,  H01L21/82 ,  H01L21/8234

CPC classification number: H01L27/1207 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/8213 ,  H01L21/823481 ,  H01L21/84 ,  H01L29/0649 ,  H01L29/1608 ,  H01L29/165 ,  H01L29/66068 ,  H01L29/66666 ,  H01L29/7827

Abstract: A method for forming a hybrid semiconductor device includes growing a stack of layers on a semiconductor substrate. The stack of layers includes a bottom layer in contact with the substrate, a middle layer on the bottom layer and a top layer on the middle layer. First and second transistors are formed on the top layer. A protective dielectric is deposited over the first and second transistors. A trench is formed adjacent to the first transistors to expose the middle layer. The middle layer is removed from below the first transistors to form a cavity. A dielectric material is deposited in the cavity to provide a transistor on insulator structure for the first transistors and a bulk substrate structure for the second transistors.

公开(公告)号：US20170352738A1

公开(公告)日：2017-12-07

申请号：US15175694

申请日：2016-06-07

Applicant: International Business Machines Corporation

Inventor： Karthik Balakrishnan ,  Pouya Hashemi ,  Bahman Hekmatshoartabari ,  Alexander Reznicek

IPC: H01L29/49 ,  H01L29/24 ,  H01L21/3065 ,  H01L21/02 ,  H01L21/30 ,  H01L21/28 ,  H01L29/40 ,  H01L29/16

CPC classification number: H01L29/4941 ,  H01L21/02271 ,  H01L21/02592 ,  H01L21/28097 ,  H01L21/3003 ,  H01L21/3065 ,  H01L29/16 ,  H01L29/24 ,  H01L29/401 ,  H01L29/41783 ,  H01L29/66575

Abstract: A method and structure is provided in which germanium or a germanium tin alloy can be used as a channel material in either planar or non-planar architectures, with a functional gate structure formed utilizing either a gate first or gate last process. After formation of the functional gate structure, and contact openings within a middle-of-the-line (MOL) dielectric material, a hydrogenated silicon layer is formed that includes hydrogenated crystalline silicon regions disposed over the germanium or a germanium tin alloy, and hydrogenated amorphous silicon regions disposed over dielectric material. The hydrogenated amorphous silicon regions can be removed selective to the hydrogenated crystalline silicon regions, and thereafter a contact structure is formed on the hydrogenated crystalline silicon regions.

公开(公告)号：US20170338308A1

公开(公告)日：2017-11-23

申请号：US15159982

申请日：2016-05-20

Applicant: International Business Machines Corporation

Inventor： Karthik Balakrishnan ,  Stephen W. Bedell ,  Pouya Hashemi ,  Bahman Hekmatshoartabari ,  Alexander Reznicek

IPC: H01L29/10 ,  H01L29/66 ,  H01L29/165 ,  H01L29/78 ,  H01L29/161

CPC classification number: H01L29/1054 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/785 ,  H01L29/7851

Abstract: After forming semiconductor fins including vertically oriented alternating first digital alloy sublayer portions comprised of SiGe and second digital alloy sublayer portions comprised of Si on sidewalls of a sacrificial fin located on a substrate, the sacrificial fin is removed, leaving the semiconductor fins protruding from a top surface of the substrate. The SiGe and Si digital alloy sublayer portions are formed using isotopically enriched Si and Ge source gases to minimize isotopic mass variation in the SiGe and Si digital alloy sublayer portions.

公开(公告)号：US09818647B2

公开(公告)日：2017-11-14

申请号：US14729464

申请日：2015-06-03

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Karthik Balakrishnan ,  Kangguo Cheng ,  Pouya Hashemi ,  Alexander Reznicek

IPC: H01L29/78 ,  H01L21/8234 ,  H01L29/165 ,  H01L29/08 ,  H01L21/308 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L21/033 ,  H01L21/768 ,  H01L29/161 ,  H01L29/66

CPC classification number: H01L21/823431 ,  H01L21/0337 ,  H01L21/308 ,  H01L21/76877 ,  H01L21/823412 ,  H01L21/823418 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/165 ,  H01L29/41791 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785 ,  H01L2029/7858

Abstract: In one example, a field effect transistor includes a pair of fins positioned in a spaced apart relation. Each of the fins includes germanium. Source and drain regions are formed on opposite ends of the pair of fins and include silicon. A gate is wrapped around the pair of fins, between the source and drain regions.

公开(公告)号：US09793263B1

公开(公告)日：2017-10-17

申请号：US15164092

申请日：2016-05-25

Applicant: International Business Machines Corporation

Inventor： Karthik Balakrishnan ,  Stephen W. Bedell ,  Pouya Hashemi ,  Bahman Hekmatshoartabari ,  Alexander Reznicek

IPC: H01L27/11 ,  H01L27/06 ,  H01L29/78 ,  H01L29/10 ,  H01L49/02 ,  H01L29/161 ,  H01L29/201 ,  H01L21/8234 ,  H01L29/66 ,  H01L21/225 ,  H01L21/24

CPC classification number: H01L27/0629 ,  H01L21/225 ,  H01L21/242 ,  H01L21/823431 ,  H01L28/20 ,  H01L29/1054 ,  H01L29/161 ,  H01L29/201 ,  H01L29/66545 ,  H01L29/785

Abstract: A method for integrating fin field effect transistors (FinFETs) and resistors on a common substrate is provided. By employing a digital alloy as a channel material for each FinFET and as a resistor body for each resistor, FinFETs with improved charge carrier mobility, and resistors with good temperature coefficient of resistance are obtained.

公开(公告)号：US09786782B2

公开(公告)日：2017-10-10

申请号：US14921547

申请日：2015-10-23

Applicant: International Business Machines Corporation

Inventor： Karthik Balakrishnan ,  Kangguo Cheng ,  Pouya Hashemi ,  Alexander Reznicek

IPC: H01L29/78 ,  H01L29/165 ,  H01L29/66

CPC classification number: H01L29/7848 ,  H01L29/165 ,  H01L29/66795 ,  H01L29/785

Abstract: A semiconductor structure includes a material stack of, from bottom to top, an insulator structure and a semiconductor fin portion located on a pedestal portion of a semiconductor substrate portion, wherein a doped epitaxial semiconductor material structure extends from each sidewall surface of the semiconductor fin portion, each doped epitaxial semiconductor material structure introduces a stress on the semiconductor fin portion. A gate structure straddles the semiconductor fin portion. A source-side stressor structure having a bottommost surface contacting a first subsurface of the semiconductor substrate portion and covering one of the doped epitaxial semiconductor material structure is located on a source-side of the gate structure. A drain-side stressor structure having a bottommost surface contacting a second subsurface of the semiconductor substrate portion and covering another of the doped epitaxial semiconductor material structure is located on a drain-side of the gate structure.

公开(公告)号：US09779995B2

公开(公告)日：2017-10-03

申请号：US15070501

申请日：2016-03-15

Applicant: International Business Machines Corporation

Inventor： Karthik Balakrishnan ,  Kangguo Cheng ,  Pouya Hashemi ,  Alexander Reznicek

IPC: H01L29/06 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/165 ,  H01L29/78 ,  H01L29/51 ,  H01L21/306 ,  H01L29/08 ,  H01L29/167 ,  H01L29/423 ,  H01L27/088 ,  H01L29/161 ,  H01L29/45 ,  H01L29/49 ,  H01L21/84 ,  H01L29/10 ,  H01L21/02 ,  H01L27/12

CPC classification number: H01L21/823425 ,  H01L21/02532 ,  H01L21/30604 ,  H01L21/823431 ,  H01L21/84 ,  H01L27/088 ,  H01L27/1203 ,  H01L29/0657 ,  H01L29/0847 ,  H01L29/1041 ,  H01L29/1054 ,  H01L29/1066 ,  H01L29/161 ,  H01L29/165 ,  H01L29/167 ,  H01L29/41775 ,  H01L29/42376 ,  H01L29/45 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/4975 ,  H01L29/517 ,  H01L29/518 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/66977 ,  H01L29/78 ,  H01L29/7848 ,  H01L29/785

Abstract: A structure includes a substrate and a tunnel field effect transistor (TFET). The TFET includes a source region disposed in the substrate having an overlying source contact, the source region containing first semiconductor material having a first doping type; a drain region disposed in the substrate having an overlying drain contact, the drain region containing second semiconductor material having a second, opposite doping type; and a gate structure that overlies a channel region between the source and the drain. The source region and the drain region are asymmetric with respect to one another such that one contains a larger volume of semiconductor material than the other one. A method is disclosed to fabricate a plurality of the TFETs using a plurality of spaced apart mandrels having spacers. A pair of the mandrels and the associated spacers is processed to form four adjacent TFETs without requiring intervening lithographic processes.

公开(公告)号：US09761608B1

公开(公告)日：2017-09-12

申请号：US15236547

申请日：2016-08-15

Applicant: International Business Machines Corporation

Inventor： Karthik Balakrishnan ,  Pouya Hashemi ,  Tak H. Ning ,  Alexander Reznicek

IPC: H01L29/735 ,  H01L27/12 ,  H01L21/84 ,  H01L21/3105 ,  H01L21/762 ,  H01L21/3065 ,  H01L21/225 ,  H01L29/10 ,  H01L29/16 ,  H01L29/161 ,  H01L29/66 ,  H01L21/8222

CPC classification number: H01L27/1203 ,  H01L21/2253 ,  H01L21/3065 ,  H01L21/31053 ,  H01L21/76283 ,  H01L21/8222 ,  H01L21/84 ,  H01L27/082 ,  H01L29/0808 ,  H01L29/0821 ,  H01L29/1008 ,  H01L29/16 ,  H01L29/161 ,  H01L29/6625 ,  H01L29/735

Abstract: A method comprises forming shallow trenches in an intrinsic base semiconductor layer and forming a first base layer thereon; applying a first mask to the layer; etching the first base layer; forming a second base layer on the intrinsic base semiconductor layer adjacent the first base layer; removing the first mask; applying a second mask to the base layers; simultaneously etching the layers to produce extrinsic bases of reduced cross dimensions; disposing spacers on the extrinsic bases; etching around the bases leaving the intrinsic base semiconductor layer under the bases and spacers; implanting ions into sides of the intrinsic base semiconductor layer under the first extrinsic base to form a first emitter/collector junction and into sides of the intrinsic base semiconductor layer under the second extrinsic base to form a second emitter/collector junction; depositing semiconductor material adjacent to the junctions and the trenches; and removing the applied second mask.