公开(公告)号：US20210082894A1

公开(公告)日：2021-03-18

申请号：US16572619

申请日：2019-09-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Weiming Chris Chen ,  Chi-Hsi Wu ,  Chih-Wei Wu ,  Kuo-Chiang Ting ,  Szu-Wei Lu ,  Shang-Yun Hou ,  Ying-Ching Shih ,  Hsien-Ju Tsou ,  Cheng-Chieh Li

IPC: H01L25/18 ,  H01L23/367 ,  H01L25/00 ,  H01L23/00 ,  H01L21/82 ,  H01L23/48 ,  H01L21/56

Abstract: A package structure includes a circuit element, a first semiconductor die, a second semiconductor die, a heat dissipating element, and an insulating encapsulation. The first semiconductor die and the second semiconductor die are located on the circuit element. The heat dissipating element connects to the first semiconductor die, and the first semiconductor die is between the circuit element and the heat dissipating element, where a sum of a first thickness of the first semiconductor die and a third thickness of the heat dissipating element is substantially equal to a second thickness of the second semiconductor die. The insulating encapsulation encapsulates the first semiconductor die, the second semiconductor die and the heat dissipating element, wherein a surface of the heat dissipating element is substantially leveled with the insulating encapsulation.

公开(公告)号：US10656351B1

公开(公告)日：2020-05-19

申请号：US16230652

申请日：2018-12-21

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Sung-Hui Huang ,  Jui-Hsieh Lai ,  Shang-Yun Hou

IPC: G02B6/42 ,  H01L25/16

Abstract: A package structure is provided. The package structure includes an optical component over a substrate, and a reflector disposed over the substrate. The reflector includes a first semiconductor layer over a second semiconductor layer, and a dielectric layer between the first semiconductor layer and the second semiconductor layer. The reflector also includes a metal layer between the second semiconductor layer and the substrate. In addition, the package structure includes a waveguide between the metal layer and the optical component.

公开(公告)号：US12148719B2

公开(公告)日：2024-11-19

申请号：US17869296

申请日：2022-07-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wen Hsin Wei ,  Hsien-Pin Hu ,  Shang-Yun Hou ,  Weiming Chris Chen

IPC: H01L23/00 ,  H01L21/768 ,  H01L23/58 ,  H01L23/31 ,  H01L23/532 ,  H01L25/00 ,  H01L25/065

Abstract: A method includes performing a first light-exposure and a second a second light-exposure on a photo resist. The first light-exposure is performed using a first lithograph mask, which covers a first portion of the photo resist. The first portion of the photo resist has a first strip portion exposed in the first light-exposure. The second light-exposure is performed using a second lithograph mask, which covers a second portion of the photo resist. The second portion of the photo resist has a second strip portion exposed in the second light-exposure. The first strip portion and the second strip portion have an overlapping portion that is double exposed. The method further includes developing the photo resist to remove the first strip portion and the second strip portion, etching a dielectric layer underlying the photo resist to form a trench, and filling the trench with a conductive feature.

公开(公告)号：US20240312898A1

公开(公告)日：2024-09-19

申请号：US18672546

申请日：2024-05-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Weiming Chris Chen ,  Kuo-Chiang Ting ,  Shang-Yun Hou

IPC: H01L23/498 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01L23/538

CPC classification number: H01L23/49861 ,  H01L21/486 ,  H01L21/56 ,  H01L23/3121 ,  H01L23/5384

Abstract: A method of forming a semiconductor structure includes bonding a first die and a second die to a first side of a first interposer and to a first side of a second interposer, respectively, where the first interposer is laterally adjacent to the second interposer; encapsulating the first interposer and the second interposer with a first molding material; forming a first recess in a second side of the first interposer opposing the first side of the first interposer; forming a second recess in a second side of the second interposer opposing the first side of the second interposer; and filling the first recess and the second recess with a first dielectric material.

公开(公告)号：US20240222242A1

公开(公告)日：2024-07-04

申请号：US18609836

申请日：2024-03-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shang-Yun Hou ,  Hsien-Pin Hu ,  Sao-Ling Chiu ,  Wen-Hsin Wei ,  Ping-Kang Huang ,  Chih-Ta Shen ,  Szu-Wei Lu ,  Ying-Ching Shih ,  Wen-Chih Chiou ,  Chi-Hsi Wu ,  Chen-Hua Yu

IPC: H01L23/498 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/538

CPC classification number: H01L23/49816 ,  H01L21/4853 ,  H01L21/56 ,  H01L23/3121 ,  H01L23/49861 ,  H01L24/13 ,  H01L23/5385 ,  H01L2224/023 ,  H01L2225/107

Abstract: A semiconductor structure includes a first interposer; a second interposer laterally adjacent to the first interposer, where the second interposer is spaced apart from the first interposer; and a first die attached to a first side of the first interposer and attached to a first side of the second interposer, where the first side of the first interposer and the first side of the second interposer face the first die.

公开(公告)号：US12015023B2

公开(公告)日：2024-06-18

申请号：US17355433

申请日：2021-06-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shang-Yun Hou ,  Sung-Hui Huang ,  Kuan-Yu Huang ,  Hsien-Pin Hu ,  Yushun Lin ,  Heh-Chang Huang ,  Hsing-Kuo Hsia ,  Chih-Chieh Hung ,  Ying-Ching Shih ,  Chin-Fu Kao ,  Wen-Hsin Wei ,  Li-Chung Kuo ,  Chi-Hsi Wu ,  Chen-Hua Yu

IPC: H01L25/00 ,  H01L21/48 ,  H01L23/24 ,  H01L23/31 ,  H01L23/498 ,  H01L25/065 ,  H01L25/18 ,  H01L23/00

CPC classification number: H01L25/50 ,  H01L21/4803 ,  H01L21/4853 ,  H01L23/24 ,  H01L23/3128 ,  H01L23/49827 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/18 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/92 ,  H01L24/97 ,  H01L2224/0401 ,  H01L2224/1144 ,  H01L2224/1145 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/17181 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/81191 ,  H01L2224/81815 ,  H01L2224/92125 ,  H01L2224/92225 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/14 ,  H01L2924/1431 ,  H01L2924/1432 ,  H01L2924/1434 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/18161 ,  H01L2224/97 ,  H01L2224/83 ,  H01L2224/97 ,  H01L2224/81

Abstract: An integrated circuit package and a method of forming the same are provided. The method includes attaching an integrated circuit die to a first substrate. A dummy die is formed. The dummy die is attached to the first substrate adjacent the integrated circuit die. An encapsulant is formed over the first substrate and surrounding the dummy die and the integrated circuit die. The encapsulant, the dummy die and the integrated circuit die are planarized, a topmost surface of the encapsulant being substantially level with a topmost surface of the dummy die and a topmost surface of the integrated circuit die. An interior portion of the dummy die is removed. A remaining portion of the dummy die forms an annular structure.

公开(公告)号：US11990443B2

公开(公告)日：2024-05-21

申请号：US17226643

申请日：2021-04-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuan-Yu Huang ,  Sung-Hui Huang ,  Shang-Yun Hou ,  Shu Chia Hsu ,  Yu-Yun Huang ,  Wen-Yao Chang ,  Yu-Jen Cheng

IPC: H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H01L21/683 ,  H01L23/31 ,  H01L23/498 ,  H01L25/00 ,  H01L25/065

CPC classification number: H01L24/17 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/563 ,  H01L21/565 ,  H01L21/6835 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/562 ,  H01L24/08 ,  H01L24/16 ,  H01L24/80 ,  H01L25/0655 ,  H01L25/50 ,  H01L2221/68331 ,  H01L2224/08225 ,  H01L2224/16227 ,  H01L2224/17517 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2924/3511

Abstract: In an embodiment, an interposer has a first side, a first integrated circuit device attached to the first side of the interposer with a first set of conductive connectors, each of the first set of conductive connectors having a first height, a first die package attached to the first side of the interposer with a second set of conductive connectors, the second set of conductive connectors including a first conductive connector and a second conductive connector, the first conductive connector having a second height, the second conductive connector having a third height, the third height being different than the second height, a first dummy conductive connector being between the first side of the interposer and the first die package, an underfill disposed beneath the first integrated circuit device and the first die package, and an encapsulant disposed around the first integrated circuit device and the first die package.

公开(公告)号：US11854983B2

公开(公告)日：2023-12-26

申请号：US17873876

申请日：2022-07-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shang-Yun Hou ,  Hsien-Pin Hu

IPC: H01L23/48 ,  H01L23/538 ,  H01L23/498 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31

CPC classification number: H01L23/5381 ,  H01L21/486 ,  H01L21/56 ,  H01L23/3121 ,  H01L23/49861 ,  H01L23/5384

Abstract: Semiconductor devices and methods of manufacture are provided. In embodiments the semiconductor device includes a substrate, a first interposer bonded to the substrate, a second interposer bonded to the substrate, a bridge component electrically connecting the first interposer to the second interposer, two or more first dies bonded to the first interposer; and two or more second dies bonded to the second interposer.

公开(公告)号：US11810793B2

公开(公告)日：2023-11-07

申请号：US17873640

申请日：2022-07-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Yu Lu ,  Ping-Kang Huang ,  Sao-Ling Chiu ,  Shang-Yun Hou

IPC: H01L21/48 ,  H01L23/00 ,  H01L23/538 ,  H01L25/065 ,  H01L25/18 ,  H01L25/00 ,  H01L23/498 ,  H01L21/56

CPC classification number: H01L21/486 ,  H01L21/481 ,  H01L21/4853 ,  H01L23/49827 ,  H01L23/5384 ,  H01L24/81 ,  H01L25/0655 ,  H01L25/18 ,  H01L25/50 ,  H01L21/563 ,  H01L23/49894 ,  H01L2224/81815

Abstract: One embodiment includes partially forming a first through via in a substrate of an interposer, the first through via extending into a first side of the substrate of the interposer. The method also includes bonding a first die to the first side of the substrate of the interposer. The method also includes recessing a second side of the substrate of the interposer to expose the first through via, the first through via protruding from the second side of the substrate of the interposer, where after the recessing, the substrate of the interposer is less than 50 μm thick. The method also includes and forming a first set of conductive bumps on the second side of the substrate of the interposer, at least one of the first set of conductive bumps being electrically coupled to the exposed first through via.

公开(公告)号：US20230307375A1

公开(公告)日：2023-09-28

申请号：US18151583

申请日：2023-01-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hao-Cheng Hou ,  Tsung-Ding Wang ,  Jung Wei Cheng ,  Yu-Min Liang ,  Chien-Hsun Lee ,  Shang-Yun Hou ,  Wei-Yu Chen ,  Collin Jordon Fleshman ,  Kuo-Lung Pan ,  Shu-Rong Chun ,  Sheng-Chi Lin

IPC: H01L23/538 ,  H01L23/31 ,  H01L23/00 ,  H01L25/00 ,  H10B80/00 ,  H01L25/18 ,  H01L21/56 ,  H01L23/48

CPC classification number: H01L23/5385 ,  H01L23/3121 ,  H01L24/19 ,  H01L24/20 ,  H01L25/50 ,  H10B80/00 ,  H01L25/18 ,  H01L21/561 ,  H01L23/481 ,  H01L23/562 ,  H01L2224/16227 ,  H01L24/16 ,  H01L24/29 ,  H01L2224/2929 ,  H01L2924/0665 ,  H01L2224/29386 ,  H01L2924/05442 ,  H01L2924/05432 ,  H01L2924/0503 ,  H01L24/32 ,  H01L2224/32225 ,  H01L24/73 ,  H01L2224/73204 ,  H01L2224/19 ,  H01L2224/211

Abstract: A method includes forming a composite package substrate. The formation of the composite package substrate includes encapsulating an interconnect die in an encapsulant, with the interconnect die including a plurality of through-vias therein, and forming a first plurality of redistribution lines (RDLs) and a second plurality of RDLs on opposite sides of the interconnect die. The method further includes bonding an organic package substrate to the composite package substrate, and bonding a first package component and a second package component to the first plurality of RDLs. The first package component and the second package component are electrically interconnected through the interconnect die and the first plurality of RDLs.