公开(公告)号：US20170076817A1

公开(公告)日：2017-03-16

申请号：US15363808

申请日：2016-11-29

申请人： KABUSHIKI KAISHA TOSHIBA

发明人： Hiroshi NAKAMURA ,  Kenichi Imamiya ,  Toshio Yamamura ,  Koji Hosono ,  Koichi Kawai

IPC分类号： G11C16/34 ,  G11C16/10 ,  G11C16/08 ,  G11C16/26

CPC分类号： G11C16/3459 ,  G06F3/0659 ,  G06F12/0246 ,  G11C7/065 ,  G11C7/1006 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1063 ,  G11C16/06 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26 ,  G11C2207/104 ,  G11C2216/14

摘要： In a semiconductor integrated circuit, an internal circuit is capable of executing a first operation and a second operation concurrently, and an output circuit outputs to the outside of the semiconductor integrated circuit information indicating whether or not the first operation is being executed and information indicating whether or not the second operation is executable.

摘要翻译： 在半导体集成电路中，内部电路能够同时执行第一操作和第二操作，并且输出电路向半导体集成电路的外部输出指示是否正在执行第一操作的信息以及指示是否 或者不是第二操作是可执行的。

公开(公告)号：US20170068617A1

公开(公告)日：2017-03-09

申请号：US15355621

申请日：2016-11-18

申请人： MICRON TECHNOLOGY, INC.

发明人： Terry Grunzke

IPC分类号： G06F12/06 ,  G06F13/16

CPC分类号： G06F12/0653 ,  G06F12/0661 ,  G06F13/16 ,  G06F13/18 ,  G11C5/00 ,  G11C7/10 ,  G11C7/20 ,  G11C7/22 ,  G11C16/06 ,  H04L25/0278 ,  H04L25/0298 ,  Y02D10/14

摘要： Methods for termination of signal lines within a memory system include appointing a particular memory device of a plurality of memory devices to act as a termination device during a memory device operation on a memory device of the plurality of memory devices corresponding to a particular address of the memory system, wherein appointing the particular memory device to act as a termination device comprises storing termination information in the particular memory device corresponding to the particular address.

摘要翻译： 用于在存储器系统内终止信号线的方法包括在存储器件操作期间指定多个存储器件的特定存储器件用作终端器件，该存储器器件操作对应于多个存储器器件的特定地址的多个存储器件的存储器器件 存储器系统，其中指定所述特定存储器设备充当终端设备包括将终止信息存储在对应于所述特定地址的所述特定存储设备中。

公开(公告)号：US09558829B2

公开(公告)日：2017-01-31

申请号：US14957270

申请日：2015-12-02

申请人： SK hynix Inc.

发明人： Bo Kyeom Kim

IPC分类号： G11C11/34 ,  G11C16/06 ,  G11C16/26

CPC分类号： G11C16/06 ,  G11C16/26

摘要： A semiconductor memory apparatus including a latch unit configured to be driven in response to activation of a reset selection signal and resetting a first node and a second node; and an auxiliary driving unit configured to support a driving force of the latch unit in response to the reset selection signal and a voltage logic level of the first node or the second node, wherein the first node and the second node have substantially opposite voltage logic levels.

摘要翻译： 一种半导体存储装置，包括锁存单元，配置为响应于复位选择信号的激活而被驱动并且重置第一节点和第二节点; 以及辅助驱动单元，被配置为响应于所述复位选择信号和所述第一节点或所述第二节点的电压逻辑电平来支持所述锁存单元的驱动力，其中所述第一节点和所述第二节点具有基本相反的电压逻辑电平 。

公开(公告)号：US09530470B2

公开(公告)日：2016-12-27

申请号：US14705717

申请日：2015-05-06

申请人： Micron Technology, Inc.

发明人： Jae-Kwan Park

IPC分类号： G11C7/12 ,  G11C16/28 ,  G11C7/14 ,  G11C16/24

CPC分类号： G11C7/12 ,  G11C7/14 ,  G11C16/06 ,  G11C16/24 ,  G11C16/28

摘要： Memories, pre-charge circuits, and methods for pre-charging memory are described. One such method includes providing a voltage to a data line and adjusting the voltage provided to the data line based at least in part on a voltage difference between a target voltage and a voltage of the data line being pre-charged. An example pre-charge circuit includes a voltage generator configured to generate an output voltage having a magnitude based at least in part on a reference voltage and a feedback signal, first and second drivers, and a voltage detector. The voltage detector is configured to determine a voltage difference between the reference voltage and a sample voltage of a data line coupled to the second driver and generate the feedback signal based at least in part on the difference.

公开(公告)号：US20160373111A1

公开(公告)日：2016-12-22

申请号：US15187861

申请日：2016-06-21

申请人： Rambus Inc.

发明人： Ian Shaeffer

IPC分类号： H03K19/00 ,  G11C5/14 ,  H03K19/0175

CPC分类号： H03K19/0005 ,  G11C5/063 ,  G11C5/14 ,  G11C7/1084 ,  G11C11/4063 ,  G11C11/413 ,  G11C16/06 ,  H03K19/017545

摘要： Local on-die termination controllers for effecting termination of a high-speed signaling links simultaneously engage on-die termination structures within multiple integrated-circuit memory devices disposed on the same memory module, and/or within the same integrated-circuit package, and coupled to the high-speed signaling link. A termination control bus is coupled to memory devices on a module, and provides for peer-to-peer communication of termination control signals.

公开(公告)号：US20160372209A1

公开(公告)日：2016-12-22

申请号：US15257773

申请日：2016-09-06

申请人： KABUSHIKI KAISHA TOSHIBA

发明人： Naoki MATSUNAGA

IPC分类号： G11C16/34 ,  G06F3/06 ,  G11C29/52 ,  G11C16/04 ,  G11C16/26

CPC分类号： G11C16/26 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0655 ,  G06F3/0679 ,  G06F11/1068 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/04 ,  G11C16/0483 ,  G11C16/06 ,  G11C16/3404 ,  G11C16/349 ,  G11C16/3495 ,  G11C29/52

摘要： According to one embodiment, there is provided a non-volatile semiconductor storage device including a non-volatile memory, a monitoring section, a determining section, and a notification processing section. The non-volatile memory includes a plurality of memory cells driven by word lines and a voltage generating section that generates a read voltage to be applied to the word lines. The monitoring section monitors a change in a threshold distribution of the plurality of memory cells upon performing a read processing to read data from the plurality of memory cells by applying the read voltage to the word lines. The determining section determines a degree of deterioration of the non-volatile memory in accordance with a monitoring result by the monitoring section. The notification processing section notifies a life of the non-volatile memory in accordance with a determining result by the determining section.

公开(公告)号：US20160371335A1

公开(公告)日：2016-12-22

申请号：US15253965

申请日：2016-09-01

申请人： MICRON TECHNOLOGY, INC.

发明人： Luca De Santis ,  Giulio G. Marotta ,  Marco-Domenico Tiburzi ,  Tommaso Vali ,  Frankie F. Roohparvar ,  Agostino Macerola

IPC分类号： G06F17/30 ,  G11C15/04 ,  G06F12/0802 ,  G11C29/50 ,  G06F7/20

CPC分类号： G06F17/30495 ,  G06F3/0628 ,  G06F7/20 ,  G06F12/0802 ,  G06F2212/1021 ,  G06F2212/608 ,  G11C7/1006 ,  G11C15/046 ,  G11C16/0483 ,  G11C16/06 ,  G11C29/50004 ,  G11C29/50016

摘要： Memory devices for facilitating pattern matching and having an array of memory cells, a plurality of key registers to store a representation of a key word, and a plurality of multiplexers, each multiplexer of the plurality of multiplexers to select a representation of a bit from a key register of the plurality of key registers to compare to data stored in the array of memory cells.

摘要翻译： 用于促进图案匹配并具有存储器单元阵列的存储器件，用于存储关键字的表示的多个键寄存器和多个复用器，多个多路复用器的每个复用器用于从一个或多个多路复用器中选择一个位的表示 多个密钥寄存器的密钥寄存器与存储在存储器单元阵列中的数据进行比较。

公开(公告)号：US20160371004A1

公开(公告)日：2016-12-22

申请号：US14939736

申请日：2015-11-12

申请人： SK hynix Inc.

发明人： Hae-Gi CHOI

IPC分类号： G06F3/06 ,  G06F12/12 ,  G06F12/08

CPC分类号： G06F13/16 ,  G06F3/0625 ,  G06F3/064 ,  G06F3/0679 ,  G11C7/106 ,  G11C7/1087 ,  G11C16/0483 ,  G11C16/06 ,  G11C16/10 ,  G11C16/32 ,  G11C2207/2245 ,  Y02D10/154

摘要： A memory system includes a memory device; a memory suitable for temporarily storing data transferred between a host and the memory device; and a controller suitable for classifying data provided from the host into first classification data of relatively great size based on a reference size and second classification data of relatively small size based on the reference size, classifying one or more of the second classification data, which is repeatedly provided more than a threshold value of repetition, as third classification data, and managing the third classification data only in the memory.

摘要翻译： 存储器系统包括存储器件; 适于临时存储在主机和存储设备之间传送的数据的存储器; 以及控制器，其适于将从主机提供的数据分类为基于参考尺寸的相对较大尺寸的第一分类数据和基于参考尺寸的相对较小尺寸的第二分类数据，对一个或多个第二分类数据进行分类，所述第二分类数据是 重复提供多于重复的阈值，作为第三分类数据，并且仅在存储器中管理第三分类数据。

公开(公告)号：US09520409B2

公开(公告)日：2016-12-13

申请号：US15016425

申请日：2016-02-05

申请人： SK hynix Inc.

发明人： Tae Kyung Kim ,  Dae Sung Eom

IPC分类号： H01L21/76 ,  H01L27/115 ,  G11C16/06 ,  H01L21/768

CPC分类号： H01L27/11582 ,  G11C16/06 ,  H01L21/76897 ,  H01L27/1157 ,  H01L27/11578

摘要： A three-dimensional nonvolatile memory device includes a first vertical channel layer and a second vertical channel layer extending from a substrate, a plurality of memory cells, first selection transistors and second selection transistors spaced apart from each other along the first vertical channel layer and the second vertical channel layer, a pad, a contact plug and a bit line in a stacked configuration over the first vertical channel layer, and a common source line formed over the second vertical channel layer.

摘要翻译： 三维非易失性存储器件包括第一垂直沟道层和从衬底延伸的第二垂直沟道层，多个存储单元，第一选择晶体管和第二选择晶体管，沿着第一垂直沟道层彼此间隔开， 第二垂直沟道层，衬垫，接触插塞和位于第一垂直沟道层上的层叠配置中的位线，以及形成在第二垂直沟道层上的公共源极线。

公开(公告)号：US20160350184A1

公开(公告)日：2016-12-01

申请号：US14721913

申请日：2015-05-26

申请人： MICRON TECHNOLOGY, INC.

发明人： CHANDRA C. VARANASI

IPC分类号： G06F11/10 ,  H03M13/15 ,  G11C29/52

CPC分类号： G06F11/1072 ,  G06F11/1012 ,  G11C16/06 ,  G11C29/42 ,  G11C29/52 ,  G11C2029/0411 ,  H03M13/152 ,  H03M13/154

摘要： Embodiments of the present invention disclose methods and apparatuses for correcting errors in data stored in a solid state device. The solid state device may have a plurality of bits stored in multi-level memory cells. The method may include identifying one or more errors in a plurality of memory cells. The method may further include converting the erroneous cells to erasures. The method may further include correcting the one or more erasures.

摘要翻译： 本发明的实施例公开了用于校正存储在固态设备中的数据中的错误的方法和装置。 固态设备可以具有存储在多级存储器单元中的多个位。 该方法可以包括识别多个存储器单元中的一个或多个错误。 该方法还可以包括将错误的单元格转换为擦除。 该方法还可以包括校正一个或多个擦除。