公开(公告)号：US06790757B1

公开(公告)日：2004-09-14

申请号：US09467253

申请日：1999-12-20

申请人： Sailesh Chittipeddi ,  Sailesh Mansinh Merchant

发明人： Sailesh Chittipeddi ,  Sailesh Mansinh Merchant

IPC分类号： H01L2144

CPC分类号： H01L24/85 ,  H01L24/03 ,  H01L24/05 ,  H01L24/45 ,  H01L24/48 ,  H01L24/78 ,  H01L2224/04042 ,  H01L2224/05681 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45565 ,  H01L2224/456 ,  H01L2224/45624 ,  H01L2224/48091 ,  H01L2224/48465 ,  H01L2224/48472 ,  H01L2224/48599 ,  H01L2224/48699 ,  H01L2224/78301 ,  H01L2224/85201 ,  H01L2224/85205 ,  H01L2224/85375 ,  H01L2224/85948 ,  H01L2924/00011 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01066 ,  H01L2924/01073 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/00 ,  H01L2224/48781 ,  H01L2224/48681 ,  H01L2224/45147 ,  H01L2924/00015 ,  H01L2924/013 ,  H01L2924/01006

摘要： The present invention uses wire bonding technology to bond interconnect materials that oxidize easily by using a wire with stable oxidation qualities. A passivation layer is formed on the semiconductor substrate to encapsulate the bonding pad made from the interconnect material such that the wire bonds with the passivation layer itself, not with the interconnect material. The passivation layer is selected to be a material that is metallurgically stable when bonded to the interconnect material. Since the wire is stable compared with the interconnect material, i.e., it does not readily corrode, a reliable mechanical and electrical connection is provided between the semiconductor device (interconnect material) and the wire, with the passivation layer disposed therebetween.

摘要翻译： 本发明使用引线接合技术，通过使用具有稳定的氧化特性的导线，可以容易地接合易氧化的互连材料。 在半导体衬底上形成钝化层以封装由互连材料制成的接合焊盘，使得引线与钝化层本身而不是与互连材料结合。 钝化层选择为当结合到互连材料时是冶金稳定的材料。 由于线与互连材料相比是稳定的，即不易腐蚀，所以在半导体器件（互连材料）和导线之间提供可靠的机械和电连接，其中钝化层位于它们之间。

公开(公告)号：US06706603B2

公开(公告)日：2004-03-16

申请号：US09792266

申请日：2001-02-23

申请人： Sailesh Chittipeddi

发明人： Sailesh Chittipeddi

IPC分类号： H01L218238

CPC分类号： H01L29/66666 ,  H01L21/823487 ,  H01L29/7827

摘要： The present invention provides a method of forming a vertical replacement gate (VRG) device on a semiconductor substrate. The method includes depositing an epitaxial layer over a first source/drain region, implanting a layer within the epitaxial layer wherein the thickness of the layer substantially defines a channel length of the device and replacing the layer with a gate layer.

摘要翻译： 本发明提供一种在半导体衬底上形成垂直置换栅极（VRG）器件的方法。 该方法包括在第一源极/漏极区域上沉积外延层，在外延层内注入层，其中层的厚度基本上限定了器件的沟道长度并用栅极层代替层。

公开(公告)号：US06503793B1

公开(公告)日：2003-01-07

申请号：US09927752

申请日：2001-08-10

申请人： Sailesh Chittipeddi ,  Yehuda Smooha

发明人： Sailesh Chittipeddi ,  Yehuda Smooha

IPC分类号： H01L218242

CPC分类号： H01L29/66181 ,  H01L21/76229 ,  H01L21/763 ,  H01L27/0251 ,  H01L29/945

摘要： The present invention provides a method of forming a trench capacitor in an input/output region and a trench isolation structure in an active device region and a method of manufacturing an integrated circuit using the aforementioned method of forming. The invention comprises concurrently forming an isolation trench in an active region and a capacitive trench in an input/output region, concurrently forming a dielectric layer over the walls of the isolation trench and the capacitive trench, and forming a conductive material in the capacitive trench.

摘要翻译： 本发明提供一种在有源器件区域中的输入/输出区域和沟槽隔离结构中形成沟槽电容器的方法和使用上述形成方法制造集成电路的方法。 本发明包括在输入/输出区域中的有源区域和电容沟槽中同时形成隔离沟槽，同时在隔离沟槽和电容沟槽的壁上形成电介质层，并在电容沟槽中形成导电材料。

公开(公告)号：US06500729B1

公开(公告)日：2002-12-31

申请号：US09586384

申请日：2000-06-02

申请人： Sailesh Chittipeddi ,  Arun Kumar Nanda ,  Ankineedu Velaga

发明人： Sailesh Chittipeddi ,  Arun Kumar Nanda ,  Ankineedu Velaga

IPC分类号： H01L2176

CPC分类号： H01L21/76224

摘要： A method for forming shallow trench isolation structures produces a shallow trench isolation structure having a substantially planar upper surface. The shallow trench isolation structure is formed from an originally formed shallow trench isolation structure which includes a deposited dielectric material within a trench and which exhibits dishing related problems in the form of a void formed within the trench, wherein the surface of the deposited dielectric material is recessed below the planar upper surface. The method provides for filling the void with a silicon film. The silicon film is then polished in its as-deposited or oxidized form, to produce a shallow trench isolation structure having a planar upper surface.

摘要翻译： 形成浅沟槽隔离结构的方法产生具有基本平坦的上表面的浅沟槽隔离结构。 浅沟槽隔离结构由原始形成的浅沟槽隔离结构形成，其包括在沟槽内的沉积的介电材料，并且其呈现出形成在沟槽内的空隙形式的凹陷相关问题，其中沉积的介电材料的表面是 凹进平面上表面下方。 该方法提供用硅膜填充空隙。 然后以其沉积或氧化形式抛光硅膜，以产生具有平坦上表面的浅沟槽隔离结构。

公开(公告)号：US06472304B2

公开(公告)日：2002-10-29

申请号：US09864577

申请日：2001-05-24

申请人： Sailesh Chittipeddi ,  Sailesh Mansinh Merchant

发明人： Sailesh Chittipeddi ,  Sailesh Mansinh Merchant

IPC分类号： H01L2144

CPC分类号： H01L24/85 ,  H01L24/03 ,  H01L24/05 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/02166 ,  H01L2224/04042 ,  H01L2224/05009 ,  H01L2224/05027 ,  H01L2224/05082 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05187 ,  H01L2224/05556 ,  H01L2224/05558 ,  H01L2224/05572 ,  H01L2224/05624 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48453 ,  H01L2224/48463 ,  H01L2224/48624 ,  H01L2224/48699 ,  H01L2224/48724 ,  H01L2224/48824 ,  H01L2224/85201 ,  H01L2224/85203 ,  H01L2224/85205 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01043 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/14 ,  H01L2924/20751 ,  H01L2924/20752 ,  H01L2924/20753 ,  H01L2924/20754 ,  H01L2924/20755 ,  H01L2224/78 ,  H01L2924/00 ,  H01L2224/05552 ,  H01L2924/00015 ,  H01L2924/013 ,  H01L2924/00013 ,  H01L2924/01004

摘要： The specification describes techniques for wire bonding gold wires to copper metallization in semiconductor integrated circuits. A barrier layer is formed on the copper, and an aluminum bonding pad is formed on the barrier layer. Gold wire is then thermocompression bonded to the aluminum pad.

摘要翻译： 该说明书描述了用于将金线引线接合到半导体集成电路中的铜金属化的技术。 在铜上形成阻挡层，在阻挡层上形成铝焊盘。 然后将金线热压粘合到铝垫上。

公开(公告)号：US06445043B1

公开(公告)日：2002-09-03

申请号：US08347527

申请日：1994-11-30

申请人： Sailesh Chittipeddi

发明人： Sailesh Chittipeddi

IPC分类号： H01L2516

CPC分类号： H01L21/76224

摘要： A process for forming isolated active device regions on a silicon substrate comprises the steps of forming at least one trench in a silicon substrate to define at least two active device regions on the substrate to be isolated from each other, depositing an electrically insulative material on the substrate to fill the trench with the material, planarizing the surface of the substrate, performing a masking and etching operation to expose at least one active device region on the substrate, selectively growing a first epitaxial layer of silicon on the exposed active device region, masking the substrate to leave exposed at least one other active device region on the substrate, selectively growing a second epitaxial layer of silicon on the other exposed active device region, the first epitaxial layer and second epitaxial layer being doped with dopant atoms to the same or different dopant concentration to provide, at least two isolated active device regions on the silicon substrate. The process of the invention enables the fabrication of performance optimized MOS-type and bipolar devices simultaneously and independently of each other on a single clip or wafer.

摘要翻译： 在硅衬底上形成隔离的有源器件区域的工艺包括以下步骤：在硅衬底中形成至少一个沟槽，以在衬底上限定至少两个有源器件区域以彼此隔离;将电绝缘材料沉积在 衬底以用材料填充沟槽，平坦化衬底的表面，执行掩模和蚀刻操作以暴露衬底上的至少一个有源器件区域，在暴露的有源器件区域上选择性地生长硅的第一外延层，掩蔽 衬底以在衬底上留下暴露的至少一个其它有源器件区域，在另一暴露的有源器件区域上选择性地生长硅的第二外延层，第一外延层和第二外延层掺杂有相同或不同的掺杂剂原子 掺杂剂浓度以在硅衬底上提供至少两个隔离的有源器件区域。 本发明的方法使得能够在单个夹子或晶片上同时且彼此独立地制造性能优化的MOS型和双极器件。

公开(公告)号：US06387772B1

公开(公告)日：2002-05-14

申请号：US09557536

申请日：2000-04-25

申请人： Sailesh Chittipeddi ,  Charles Walter Pearce ,  Pradip Kumar Roy

发明人： Sailesh Chittipeddi ,  Charles Walter Pearce ,  Pradip Kumar Roy

IPC分类号： H01L2120

CPC分类号： H01L29/66181 ,  H01L27/1203 ,  H01L29/945

摘要： A trench capacitor formed on an SOI substrate extends through an upper silicon layer and an insulating layer and into a semiconductor base substrate. The outer electrode of the trench capacitor includes portions of the semiconductor base substrate which bound the trench in which the trench capacitor is formed. The outer electrode is coupled to a contact structure formed in close proximity to the trench capacitor, and which extends through the insulating layer. The method for simultaneously producing the trench capacitor and contact structure includes forming two trench openings, forming a dielectric liner on one of the trench openings, then filling each of the trench openings with a semiconductor material.

摘要翻译： 形成在SOI衬底上的沟槽电容器延伸穿过上硅层和绝缘层并进入半导体基底衬底。 沟槽电容器的外部电极包括半导体基底基板的限定形成沟槽电容器的沟槽的部分。 外电极耦合到紧邻沟槽电容器形成的接触结构，并延伸穿过绝缘层。 用于同时制造沟槽电容器和接触结构的方法包括形成两个沟槽开口，在一个沟槽开口上形成电介质衬垫，然后用半导体材料填充每个沟槽开口。

公开(公告)号：US06365469B2

公开(公告)日：2002-04-02

申请号：US09140276

申请日：1998-08-26

申请人： Sailesh Chittipeddi ,  Michael James Kelly

发明人： Sailesh Chittipeddi ,  Michael James Kelly

IPC分类号： H01L21336

CPC分类号： H01L27/11 ,  H01L21/763

摘要： A process for fabricating novel dual-polysilicon structures comprises forming trenches of differing depths in a field oxide that overlies a substrate. The trenches are formed using a stop layer so that the depth of the trenches may be precisely controlled. Utilizing an ion implantation barrier in the trenches, ion implantation is performed to create self-aligned structures. Importantly, polysilicon is formed in the trenches in a single deposition.

摘要翻译： 一种用于制造新颖的双多晶硅结构的工艺包括在覆盖衬底的场氧化物中形成不同深度的沟槽。 使用停止层形成沟槽，使得可以精确地控制沟槽的深度。 利用离子注入势垒在沟槽中，进行离子注入以产生自对准结构。 重要的是，在单个沉积中在沟槽中形成多晶硅。

公开(公告)号：US06358785B1

公开(公告)日：2002-03-19

申请号：US09588058

申请日：2000-06-06

申请人： Sailesh Chittipeddi ,  Arun Kumar Nanda ,  Ankineedu Velaga

发明人： Sailesh Chittipeddi ,  Arun Kumar Nanda ,  Ankineedu Velaga

IPC分类号： H01L21338

CPC分类号： H01L21/76227

摘要： A method for forming a shallow trench isolation structure within a semiconductor substrate includes forming a trench opening within a semiconductor substrate having an oxidation-resistant material as a top surface. An oxide liner is formed on inner surfaces of the trench opening. A silicon material is then introduced into the trench opening and over the top surface. The silicon material is subsequently oxidized, either before or after a polishing operation is used to planarize the structure. Dishing related problems are avoided during polishing because the silicon or oxidized silicon material has a polishing rate similar to the oxidation resistant material, and less than that of conventionally formed CVD oxides.

摘要翻译： 在半导体衬底内形成浅沟槽隔离结构的方法包括在半导体衬底内形成具有抗氧化材料作为顶表面的沟槽开口。 氧化物衬垫形成在沟槽开口的内表面上。 然后将硅材料引入沟槽开口并在顶表面上。 在抛光操作用于平面化结构之前或之后，硅材料随后被氧化。 由于硅或氧化硅材料的抛光速率与耐氧化材料相似，并且小于常规形成的CVD氧化物的抛光速率，所以在抛光过程中避免了相关的问题。

公开(公告)号：US5986343A

公开(公告)日：1999-11-16

申请号：US072369

申请日：1998-05-04

申请人： Sailesh Chittipeddi ,  Vivian Ryan

发明人： Sailesh Chittipeddi ,  Vivian Ryan

IPC分类号： H01L27/04 ,  H01L21/60 ,  H01L21/822 ,  H01L23/485 ,  H01L23/48

CPC分类号： H01L24/05 ,  H01L24/48 ,  H01L2224/02166 ,  H01L2224/04042 ,  H01L2224/05093 ,  H01L2224/05096 ,  H01L2224/05556 ,  H01L2224/05599 ,  H01L2224/05624 ,  H01L2224/48463 ,  H01L2224/85424 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01027 ,  H01L2924/01033 ,  H01L2924/1306 ,  H01L2924/14

摘要： The present invention provides a bond pad support structure for use in an integrated circuit having a bond pad located thereon. In one embodiment, the bond pad support structure comprises a support layer that is located below the bond pad and that has an opening formed therein. The bond pad support structure further includes a dielectric layer that is located on the conductive layer and that extends at least partially into the opening to form a bond pad support surface over at least a portion of the opening. The first bond pad support layer, in one embodiment, may comprise a conductive metal and the second bond pad support layer may comprise of a dielectric material. The present invention provides a unique bond pad structure wherein an opening within a first bond pad support layer is at least partially filled with a second bond pad support layer. It is believed that the inter-structural cooperation between these two layers provides a graded composite support structure that acts as a differential force transducer to buffer internal and bonding stresses within an integrated circuit.

摘要翻译： 本发明提供一种用于集成电路中的接合焊盘支撑结构，该集成电路具有位于其上的接合焊盘。 在一个实施例中，接合焊盘支撑结构包括位于接合焊盘下方并且具有形成在其中的开口的支撑层。 接合焊盘支撑结构还包括位于导电层上并且至少部分地延伸到开口中以在开口的至少一部分上形成接合焊盘支撑表面的电介质层。 在一个实施例中，第一接合焊盘支撑层可以包括导电金属，并且第二接合焊盘支撑层可以包括电介质材料。 本发明提供了一种独特的接合焊盘结构，其中第一接合焊盘支撑层内的开口至少部分地被第二接合焊盘支撑层填充。 据信这两层之间的结构间协作提供了一种梯度复合支撑结构，其作为差分力传感器来缓冲集成电路内的内部和结合应力。