公开(公告)号：US20170054004A1

公开(公告)日：2017-02-23

申请号：US15244067

申请日：2016-08-23

Applicant: International Business Machines Corporation ,  GlobalFoundries, Inc.

Inventor： Kangguo Cheng ,  Ruilong Xie ,  Tenko Yamashita

IPC: H01L29/66 ,  H01L21/768 ,  H01L21/28 ,  H01L21/02

CPC classification number: H01L29/66553 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/0228 ,  H01L21/28079 ,  H01L21/76897 ,  H01L29/41791 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: A method of making a semiconductor device includes patterning a fin in a substrate; forming a gate between source/drain regions over the substrate, the gate having a dielectric spacer along a sidewall; removing a portion of the dielectric spacer and filling with a metal oxide to form a spacer having a first spacer portion and a second spacer portion; forming a source/drain contact over at least one of the source/drain regions; recessing the source/drain contact and forming a via contact over the source/drain contact; and forming a gate contact over the gate, the gate contact having a first gate contact portion contacting the gate and a second gate contact portion positioned over the first gate contact portion; wherein the first spacer portion isolates the first gate contact portion from the source/drain contact, and the second spacer portion isolates the second gate contact portion from the source/drain contact.

公开(公告)号：US20170047350A1

公开(公告)日：2017-02-16

申请号：US15335549

申请日：2016-10-27

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Andres Bryant ,  Jeffrey B. Johnson ,  Effendi Leobandung ,  Tenko Yamashita

IPC: H01L27/12 ,  H01L29/66 ,  H01L29/45 ,  H01L29/51 ,  H01L29/16 ,  H01L29/78 ,  H01L29/06

CPC classification number: H01L27/1211 ,  H01L29/0649 ,  H01L29/16 ,  H01L29/456 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: A method for fabricating a FinFET device includes forming a silicon-on-insulator (SOI) substrate having a semiconductor layer overlaying a buried oxide (BOX) layer; etching the semiconductor layer to form a plurality of fin structures and a semiconductor layer gap in between the plurality of fin structures and the BOX layer; depositing a sacrificial gate over at least one gate region, wherein the gate region separates a source and a drain region; disposing offset spacers on vertical sidewalls of the sacrificial gate; removing the sacrificial gate; removing the semiconductor layer gap in the gate region to prevent merging of the plurality of fin structures in the gate regions; and fabricating a high-k dielectric metal gate structure overlaying the fin structures in the gate region.

Abstract translation: 一种制造FinFET器件的方法包括：形成具有覆盖掩埋氧化物（BOX）层的半导体层的绝缘体上硅（SOI）衬底; 蚀刻半导体层以在多个翅片结构和BOX层之间形成多个翅片结构和半导体层间隙; 在至少一个栅极区上沉积牺牲栅极，其中栅极区域分离源区和漏区; 在牺牲栅极的垂直侧壁上设置偏置间隔物; 去除牺牲门; 去除所述栅极区域中的半导体层间隙，以防止所述栅极区域中的所述多个翅片结构的合流; 以及制造覆盖栅极区域中的鳍结构的高k电介质金属栅极结构。

公开(公告)号：US20170047226A1

公开(公告)日：2017-02-16

申请号：US15227142

申请日：2016-08-03

Applicant: International Business Machines Corporation ,  GlobalFoundries, Inc.

Inventor： Kangguo Cheng ,  Ruilong Xie ,  Tenko Yamashita

IPC: H01L21/285 ,  H01L29/45 ,  H01L29/08 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L21/28518 ,  H01L21/283 ,  H01L21/76897 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823475 ,  H01L27/0886 ,  H01L29/0847 ,  H01L29/41791 ,  H01L29/45 ,  H01L29/456 ,  H01L29/665 ,  H01L29/66795 ,  H01L29/7851 ,  H01L2029/7858

Abstract: A method of making a semiconductor device includes forming a recessed fin in a substrate, the recessed fin being substantially flush with a surface of the substrate; performing an epitaxial growth process over the recessed fin to form a source/drain over the recessed fin; and disposing a conductive metal around the source/drain.

公开(公告)号：US09564440B2

公开(公告)日：2017-02-07

申请号：US15232246

申请日：2016-08-09

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES INC.

Inventor： Hyun-Jin Cho ,  Tenko Yamashita ,  Hui Zang

IPC: H01L27/092 ,  H01L29/66 ,  H01L29/49 ,  H01L29/423 ,  H01L21/8238

CPC classification number: H01L29/512 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/28088 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823842 ,  H01L21/823864 ,  H01L21/845 ,  H01L27/0922 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/42364 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851

Abstract: A method of forming a gate structure for a semiconductor device that includes forming first spacers on the sidewalls of replacement gate structures that are present on a fin structure, wherein an upper surface of the first spacers is offset from an upper surface of the replacement gate structure, and forming at least second spacers on the first spacers and the exposed surfaces of the replacement gate structure. The method may further include substituting the replacement gate structure with a functional gate structure having a first width portion in a first space between adjacent first spacers, and a second width portion having a second width in a second space between adjacent second spacers, wherein the second width is greater than the first width.

Abstract translation: 一种形成用于半导体器件的栅极结构的方法，包括在存在于鳍状结构上的置换栅极结构的侧壁上形成第一间隔物，其中第一间隔物的上表面偏离替换栅极结构的上表面 并且在所述第一间隔物和所述替换栅极结构的所述暴露表面上形成至少第二间隔物。 该方法还可以包括用相邻的第一间隔件之间的第一空间中具有第一宽度部分的功能栅极结构代替替换栅极结构，以及在相邻的第二间隔物之间​​的第二空间中具有第二宽度的第二宽度部分，其中第二 宽度大于第一宽度。

公开(公告)号：US20170005014A1

公开(公告)日：2017-01-05

申请号：US14789476

申请日：2015-07-01

Applicant: International Business Machines Corporation ,  Globalfoundries, Inc.

Inventor： Tenko Yamashita ,  Chun-Chen Yeh ,  Hui Zang

IPC: H01L21/66 ,  H01L29/06 ,  H01L29/78 ,  H01L21/768 ,  H01L23/528 ,  H01L23/522

CPC classification number: H01L22/32 ,  H01L21/76895 ,  H01L21/823431 ,  H01L22/12 ,  H01L22/14 ,  H01L22/20 ,  H01L22/34 ,  H01L23/5222 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/66545 ,  H01L29/7851

Abstract: Embodiments are directed to a method Embodiments are directed to a test structure of a fin-type field effect transistor (FinFET). The test structure includes a first conducting layer electrically coupled to a dummy gate of the FinFET, and a second conducting layer electrically coupled to a substrate of the FinFET. The test structure further includes a third conducting layer electrically coupled to the dummy gate of the FinFET, and a first region of the FinFET at least partially bound by the first conducting layer and the second conducting layer. The test structure further includes a second region of the FinFET at least partially bound by the second conducting layer and the third conducting layer, wherein the first region comprises a first dielectric having a first dimension, and wherein the second region comprises a second dielectric having a second dimension greater than the first dimension.

Abstract translation: 实施例涉及一种方法。实施例涉及鳍式场效应晶体管（FinFET）的测试结构。 测试结构包括电耦合到FinFET的伪栅极的第一导电层和电耦合到FinFET的衬底的第二导电层。 测试结构还包括电耦合到FinFET的伪栅极的第三导电层，以及至少部分地由第一导电层和第二导电层限制的FinFET的第一区域。 所述测试结构还包括至少部分地由所述第二导电层和所述第三导电层限制的所述FinFET的第二区域，其中所述第一区域包括具有第一尺寸的第一电介质，并且其中所述第二区域包括具有 第二维度大于第一维度。

公开(公告)号：US09520392B1

公开(公告)日：2016-12-13

申请号：US14954050

申请日：2015-11-30

Applicant: International Business Machines Corporation ,  GlobalFoundries, Inc.

Inventor： Kangguo Cheng ,  Junli Wang ,  Ruilong Xie ,  Tenko Yamashita

IPC: H01L29/94 ,  H01L27/07 ,  H01L29/06 ,  H01L21/308 ,  H01L21/225

CPC classification number: H01L27/0629 ,  H01L21/3083 ,  H01L21/3086 ,  H01L21/823431 ,  H01L27/0733 ,  H01L29/1083 ,  H01L29/66174 ,  H01L29/66537 ,  H01L29/6656 ,  H01L29/785 ,  H01L29/93

Abstract: A semiconductor device includes a semiconductor substrate having a fin-type field effect transistor (finFET) on a first region and a fin varactor on a second region. The finFET includes a first semiconductor fin that extends from an upper finFET surface thereof to the upper surface of the first region to define a first total fin height. The fin varactor includes a second semiconductor fin that extends from an upper varactor surface thereof to the upper surface of the second region to define a second total fin height that is different from the first total fin height of the finFET.

Abstract translation: 半导体器件包括在第一区域上具有鳍式场效应晶体管（finFET）的半导体衬底和在第二区域上的鳍变容二极管。 finFET包括从其上finFET表面延伸到第一区域的上表面以限定第一总鳍高度的第一半导体鳍片。 翅片变容二极管包括从其上变性反应器表面延伸到第二区域的上表面的第二半导体鳍片，以限定与鳍片鳍片的第一总鳍片高度不同的第二总翅片高度。

公开(公告)号：US09484306B1

公开(公告)日：2016-11-01

申请号：US14943663

申请日：2015-11-17

Applicant: International Business Machines Corporation ,  GlobalFoundries, Inc.

Inventor： Kangguo Cheng ,  Xin Miao ,  Ruilong Xie ,  Tenko Yamashita

IPC: H01L21/70 ,  H01L23/535 ,  H01L21/8238 ,  H01L21/768 ,  H01L27/092 ,  H01L23/528

CPC classification number: H01L29/41791 ,  H01L21/76224 ,  H01L21/76805 ,  H01L21/76816 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/823821 ,  H01L21/823842 ,  H01L21/823871 ,  H01L23/485 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5283 ,  H01L23/53209 ,  H01L23/535 ,  H01L27/0922 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/16 ,  H01L29/41758 ,  H01L29/42356 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7851

Abstract: A semiconductor device includes a source and drain on a substrate; a first and second gate on the source, and the second gate and a third gate on the drain; a source contact over the source and between the first and second gates, the source contact including first and second portions, the first portion in contact with the source and extending between the first and second gates, and the second portion contacting the first portion and extending over the first and second gates; and a drain contact formed over the drain and between the second and third gates, the drain contact including first and second portions, the first portion contacting the drain, extending between second and third gates, and recessed with respect to the first portion of the source contact, and the second portion in contact with the first portion and extending between and over the second and third gates.

公开(公告)号：US09484255B1

公开(公告)日：2016-11-01

申请号：US14930933

申请日：2015-11-03

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES INC.

Inventor： Hiroaki Niimi ,  Shariq Siddiqui ,  Tenko Yamashita

IPC: H01L21/8238 ,  H01L21/768 ,  H01L27/092 ,  H01L23/535 ,  H01L21/285 ,  H01L29/78

CPC classification number: H01L29/45 ,  H01L21/02244 ,  H01L21/02252 ,  H01L21/02255 ,  H01L21/285 ,  H01L21/28512 ,  H01L21/28518 ,  H01L21/2855 ,  H01L21/28556 ,  H01L21/28568 ,  H01L21/32134 ,  H01L21/32136 ,  H01L21/76814 ,  H01L21/76831 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/7685 ,  H01L21/76855 ,  H01L21/76858 ,  H01L21/76865 ,  H01L21/76877 ,  H01L21/76879 ,  H01L21/76895 ,  H01L21/823814 ,  H01L21/823871 ,  H01L23/485 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53252 ,  H01L23/53266 ,  H01L23/535 ,  H01L27/092 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/165 ,  H01L29/41725 ,  H01L29/41783 ,  H01L29/665 ,  H01L29/66628 ,  H01L29/7848

Abstract: An electrical device including a first semiconductor device having a silicon and germanium containing source and drain region, and a second semiconductor device having a silicon containing source and drain region. A first device contact to at least one of said silicon and germanium containing source and drain region of the first semiconductor device including a metal liner of an aluminum titanium and silicon alloy and a first tungsten fill. A second device contact is in contact with at least one of the silicon containing source and drain region of the second semiconductor device including a material stack of a titanium oxide layer and a titanium layer. The second device contact may further include a second tungsten fill.

Abstract translation: 一种电气装置，包括具有硅和锗的源极和漏极区域的第一半导体器件，以及具有含硅源极和漏极区域的第二半导体器件。 与所述第一半导体器件的所述含硅和含锗的源极和漏极区域中的至少一个接触的第一器件包括铝钛和硅合金的金属衬垫和第一钨填充物。 第二器件触点与第二半导体器件的含硅源极和漏极区域中的至少一个接触，包括氧化钛层和钛层的材料堆叠。 第二器件接触件还可以包括第二钨填充物。

公开(公告)号：US09466570B1

公开(公告)日：2016-10-11

申请号：US15149286

申请日：2016-05-09

Applicant: International Business Machines Corporation ,  GlobalFoundries, Inc.

Inventor： Kangguo Cheng ,  Xin Miao ,  Ruilong Xie ,  Tenko Yamashita

IPC: H01L21/70 ,  H01L23/535 ,  H01L21/8238

CPC classification number: H01L29/41791 ,  H01L21/76224 ,  H01L21/76805 ,  H01L21/76816 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/823821 ,  H01L21/823842 ,  H01L21/823871 ,  H01L23/485 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5283 ,  H01L23/53209 ,  H01L23/535 ,  H01L27/0922 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/16 ,  H01L29/41758 ,  H01L29/42356 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7851

Abstract: A semiconductor device includes a source and drain on a substrate; a first and second gate on the source, and the second gate and a third gate on the drain; a source contact over the source and between the first and second gates, the source contact including first and second portions, the first portion in contact with the source and extending between the first and second gates, and the second portion contacting the first portion and extending over the first and second gates; and a drain contact formed over the drain and between the second and third gates, the drain contact including first and second portions, the first portion contacting the drain, extending between second and third gates, and recessed with respect to the first portion of the source contact, and the second portion in contact with the first portion and extending between and over the second and third gates.

Abstract translation: 半导体器件包括在衬底上的源极和漏极; 源极上的第一和第二栅极，以及漏极上的第二栅极和第三栅极; 在源极之间以及第一和第二栅极之间的源极接触，源极接触包括第一和第二部分，与源极接触并在第一和第二栅极之间延伸的第一部分，以及第二部分接触第一部分并延伸 在第一和第二个门口; 以及形成在所述漏极和所述第二和第三栅极之间的漏极接触，所述漏极接触包括第一和第二部分，所述第一部分接触所述漏极，在第二和第三栅极之间延伸并相对于所述源极的第一部分凹陷 接触，第二部分与第一部分接触并在第二和第三栅极之间和之上延伸。

公开(公告)号：US09425292B1

公开(公告)日：2016-08-23

申请号：US15085112

申请日：2016-03-30

Applicant: International Business Machines Corporation ,  GlobalFoundries, Inc.

Inventor： Xiuyu Cai ,  Sanjay C. Mehta ,  Tenko Yamashita

IPC: H01L29/66 ,  H01L21/00

CPC classification number: H01L27/0924 ,  H01L21/30604 ,  H01L21/31116 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823828 ,  H01L29/16 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7848

Abstract: A method for fabricating a field effect transistor device comprises forming a fin on a substrate, forming a first dummy gate stack and a second dummy gate stack over the fin, forming spacers adjacent to the fin, the first dummy gate stack, and the second dummy gate stack, etching to remove portions of the fin and form a first cavity partially defined by the spacers, depositing an insulator material in the first cavity, patterning a mask over the first dummy gate stack and portions of the fin, etching to remove exposed portions of the insulator material, and epitaxially growing a first semiconductor material on exposed portions of the fin.

Abstract translation: 一种用于制造场效应晶体管器件的方法，包括在衬底上形成翅片，在鳍片上形成第一虚拟栅极堆叠和第二虚拟栅极堆叠，形成与鳍片相邻的间隔物，第一伪栅极堆叠和第二虚拟栅极 栅极堆叠，蚀刻以去除所述鳍片的部分并形成由所述间隔物部分地限定的第一空腔，在所述第一腔体中沉积绝缘体材料，在第一虚拟栅极堆叠和所述鳍片的部分上图案化掩模，蚀刻以去除暴露部分 并且在所述鳍的暴露部分上外延生长第一半导体材料。