公开(公告)号：US09991373B1

公开(公告)日：2018-06-05

申请号：US15370639

申请日：2016-12-06

Applicant: Infineon Technologies AG

Inventor： Albert Birner ,  Helmut Brech

IPC: H01L31/0256 ,  H01L29/778 ,  H01L29/20 ,  H01L23/522 ,  H01L23/528 ,  H01L29/66 ,  H01L21/768

CPC classification number: H01L21/76846 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/5283 ,  H01L29/2003 ,  H01L29/4175 ,  H01L29/7786

Abstract: In an embodiment, a semiconductor device includes a substrate, a Group III nitride based transistor arranged on a front surface of the substrate, and a conductive through substrate via. The conductive through substrate via includes a via extending from the front surface to a rear surface of the substrate, and conductive material extending from the front surface to the rear surface of the substrate. The via tapers from the front surface to the rear surface of the substrate.

公开(公告)号：US09960229B2

公开(公告)日：2018-05-01

申请号：US15191854

申请日：2016-06-24

Applicant: Infineon Technologies AG

Inventor： Albert Birner ,  Helmut Brech ,  Matthias Zigldrum ,  Michaela Braun ,  Christian Eckl

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/78 ,  H01L29/10 ,  H01L21/265 ,  H01L21/768 ,  H01L23/528

CPC classification number: H01L29/063 ,  H01L21/26513 ,  H01L21/76877 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/5283 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/66681 ,  H01L29/7816 ,  H01L29/7823 ,  H03F1/0288 ,  H03F3/193 ,  H03F2200/451

Abstract: In an embodiment, a semiconductor device includes a semiconductor substrate having a bulk resistivity ρ≥100 Ohm.cm, a front surface and a rear surface, at least one LDMOS transistor in the semiconductor substrate, and a RESURF structure. The RESURF structure includes a doped buried layer arranged in the semiconductor substrate, spaced at a distance from the front surface and the rear surface, and coupled with at least one of a channel region and a body contact region of the LDMOS transistor.

公开(公告)号：US20180090455A1

公开(公告)日：2018-03-29

申请号：US15279649

申请日：2016-09-29

Applicant: Infineon Technologies AG

Inventor： Helmut Brech ,  Albert Birner ,  Matthias Zigldrum ,  Michaela Braun ,  Jan Ropohl

IPC: H01L23/66 ,  H01L29/78 ,  H01L23/48 ,  H01L49/02 ,  H01L21/768 ,  H03F3/193 ,  H03F3/21

CPC classification number: H01L23/66 ,  H01L21/7682 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/522 ,  H01L28/10 ,  H01L28/20 ,  H01L28/40 ,  H01L29/7816 ,  H01L2223/6616 ,  H01L2223/6655 ,  H01L2223/6683 ,  H03F3/193 ,  H03F3/21 ,  H03F2200/222 ,  H03F2200/411

Abstract: In an embodiment, a semiconductor device includes a semiconductor substrate including a front surface, an LDMOS transistor structure in the front surface, a conductive interconnection structure arranged on the front surface, and at least one cavity arranged in the front surface.

公开(公告)号：US09875933B2

公开(公告)日：2018-01-23

申请号：US15192146

申请日：2016-06-24

Applicant: Infineon Technologies AG

Inventor： Albert Birner ,  Tobias Herzig

IPC: H01L21/768 ,  H01L21/288 ,  H01L23/48 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532

CPC classification number: H01L21/76879 ,  H01L21/2885 ,  H01L21/7682 ,  H01L21/76834 ,  H01L21/7685 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/53228 ,  H01L23/53238

Abstract: In an embodiment, a substrate includes semiconductor material and a conductive via. The conductive via includes a via in the substrate, a conductive plug filling a first portion of the via and a conductive liner layer that lines side walls of a second portion of the via and is electrically coupled to the conductive plug. The conductive liner layer and the conductive plug have different microstructures.

公开(公告)号：US20170373187A1

公开(公告)日：2017-12-28

申请号：US15191937

申请日：2016-06-24

Applicant: Infineon Technologies AG

Inventor： Albert Birner ,  Helmut Brech ,  Matthias Zigldrum ,  Michaela Braun ,  Christian Eckl

IPC: H01L29/78 ,  H01L29/10 ,  H01L23/528 ,  H01L21/768 ,  H01L23/522 ,  H01L29/66 ,  H01L23/532

CPC classification number: H01L29/7816 ,  H01L21/76804 ,  H01L21/76877 ,  H01L23/5222 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/53228 ,  H01L23/53238 ,  H01L23/53295 ,  H01L29/1095 ,  H01L29/66681

Abstract: In an embodiment, a semiconductor device includes a semiconductor substrate having a front surface, a LDMOS transistor in the front surface, and a metallization structure arranged on the front surface. The metallization structure includes at least one cavity arranged in at least one dielectric layer.

公开(公告)号：US20170372985A1

公开(公告)日：2017-12-28

申请号：US15191989

申请日：2016-06-24

Applicant: Infineon Technologies AG

Inventor： Albert Birner ,  Helmut Brech ,  Matthias Zigldrum

IPC: H01L23/48 ,  H01L29/40 ,  H01L23/532 ,  H01L21/768 ,  H01L29/06 ,  H01L29/78 ,  H01L29/10

CPC classification number: H01L23/481 ,  H01L21/76898 ,  H01L23/53228 ,  H01L23/53238 ,  H01L29/063 ,  H01L29/0696 ,  H01L29/0847 ,  H01L29/1045 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/404 ,  H01L29/4175 ,  H01L29/66659 ,  H01L29/7816 ,  H01L29/7835

Abstract: In an embodiment, a semiconductor device includes a semiconductor substrate having a front surface, a LDMOS transistor arranged in the front surface of the substrate and having an intrinsic source, and a through substrate via. A first conductive layer lines sidewalls of the through substrate via and extends from the through substrate via onto the front surface of the semiconductor substrate and is electrically coupled with the intrinsic source.

公开(公告)号：US09543260B2

公开(公告)日：2017-01-10

申请号：US13958276

申请日：2013-08-02

Applicant: Infineon Technologies AG

Inventor： Albert Birner ,  Helmut Brech ,  Matthias Zigldrum

IPC: H01L23/538 ,  H01L23/00

CPC classification number: H01L24/06 ,  H01L24/03 ,  H01L24/05 ,  H01L24/09 ,  H01L24/40 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/70 ,  H01L24/73 ,  H01L2224/03831 ,  H01L2224/04042 ,  H01L2224/04073 ,  H01L2224/05552 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/05557 ,  H01L2224/05578 ,  H01L2224/05599 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/0603 ,  H01L2224/06133 ,  H01L2224/06153 ,  H01L2224/09133 ,  H01L2224/09153 ,  H01L2224/40095 ,  H01L2224/40245 ,  H01L2224/40247 ,  H01L2224/45014 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45155 ,  H01L2224/45157 ,  H01L2224/45166 ,  H01L2224/45169 ,  H01L2224/45176 ,  H01L2224/45181 ,  H01L2224/45184 ,  H01L2224/48091 ,  H01L2224/48101 ,  H01L2224/48153 ,  H01L2224/48247 ,  H01L2224/48453 ,  H01L2224/48463 ,  H01L2224/48465 ,  H01L2224/4847 ,  H01L2224/49111 ,  H01L2224/49175 ,  H01L2224/73221 ,  H01L2224/73271 ,  H01L2224/85181 ,  H01L2224/85205 ,  H01L2224/85207 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01079 ,  H01L2924/053 ,  H01L2924/10272 ,  H01L2924/1033 ,  H01L2924/12031 ,  H01L2924/12032 ,  H01L2924/1205 ,  H01L2924/1301 ,  H01L2924/1304 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/207 ,  H01L2924/00012 ,  H01L2224/37099 ,  H01L2224/84

Abstract: In accordance with an embodiment of the present invention, a semiconductor device includes a first bond pad disposed at a first side of a substrate. The first bond pad includes a first plurality of pad segments. At least one pad segment of the first plurality of pad segments is electrically isolated from the remaining pad segments of the first plurality of pad segments.

Abstract translation: 根据本发明的实施例，半导体器件包括设置在衬底的第一侧的第一接合焊盘。 第一接合焊盘包括第一多个焊盘段。 第一多个焊盘段的至少一个焊盘段与第一多个焊盘段的其余焊盘段电隔离。

公开(公告)号：US09530720B2

公开(公告)日：2016-12-27

申请号：US14834846

申请日：2015-08-25

Applicant: Infineon Technologies AG

Inventor： Albert Birner ,  Tobias Herzig

IPC: H01L21/00 ,  H01L23/48 ,  H01L21/66 ,  H01L21/768 ,  H01L23/31

CPC classification number: H01L22/26 ,  H01L21/76898 ,  H01L22/12 ,  H01L22/20 ,  H01L22/30 ,  H01L22/32 ,  H01L23/3107 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In accordance with an embodiment of the present invention, a method of forming an electronic device includes forming a first opening and a second opening in a workpiece. The first opening is deeper than the second opening. The method further includes forming a fill material within the first opening to form part of a through via and forming the fill material within the second opening.

公开(公告)号：US09269807B2

公开(公告)日：2016-02-23

申请号：US14716200

申请日：2015-05-19

Applicant: Infineon Technologies AG

Inventor： Albert Birner ,  Helmut Brech

IPC: H01L29/10 ,  H01L29/78 ,  H01L21/265 ,  H01L29/66 ,  H01L29/08 ,  H01L29/161 ,  H01L29/167 ,  H01L29/04 ,  H01L29/40 ,  H01L29/417

CPC classification number: H01L29/7816 ,  H01L21/26506 ,  H01L21/26586 ,  H01L29/04 ,  H01L29/0847 ,  H01L29/1083 ,  H01L29/1095 ,  H01L29/161 ,  H01L29/167 ,  H01L29/402 ,  H01L29/4175 ,  H01L29/66659 ,  H01L29/7835

Abstract: A semiconductor device includes a drift region in a first region of a semiconductor body. The drift region includes dopants of a first conductivity type. A dopant retarding region is formed at least adjacent an edge of the drift region. Dopants of a second conductivity type are implanted into the semiconductor body. The semiconductor body is annealed to form a body region so that dopants of the second conductivity type are driven into the semiconductor body at a first diffusion rate. The dopant retarding region prevents the dopants from diffusing into the drift region at the first diffusion rate.

公开(公告)号：US20150255597A1

公开(公告)日：2015-09-10

申请号：US14716200

申请日：2015-05-19

Applicant: INFINEON TECHNOLOGIES AG

Inventor： Albert Birner ,  Helmut Brech

IPC: H01L29/78 ,  H01L29/04 ,  H01L29/10 ,  H01L29/167

CPC classification number: H01L29/7816 ,  H01L21/26506 ,  H01L21/26586 ,  H01L29/04 ,  H01L29/0847 ,  H01L29/1083 ,  H01L29/1095 ,  H01L29/161 ,  H01L29/167 ,  H01L29/402 ,  H01L29/4175 ,  H01L29/66659 ,  H01L29/7835

Abstract: A semiconductor device includes a drift region in a first region of a semiconductor body. The drift region includes dopants of a first conductivity type. A dopant retarding region is formed at least adjacent an edge of the drift region. Dopants of a second conductivity type are implanted into the semiconductor body. The semiconductor body is annealed to form a body region so that dopants of the second conductivity type are driven into the semiconductor body at a first diffusion rate. The dopant retarding region prevents the dopants from diffusing into the drift region at the first diffusion rate.

Abstract translation: 半导体器件包括在半导体本体的第一区域中的漂移区域。 漂移区域包括第一导电类型的掺杂剂。 至少在漂移区域的边缘附近形成掺杂剂延迟区域。 将第二导电类型的掺杂剂注入半导体本体。 将半导体体进行退火以形成体区，使得第二导电类型的掺杂剂以第一扩散速率被驱动到半导体本体中。 掺杂剂延迟区域防止掺杂剂以第一扩散速率扩散到漂移区域。