公开(公告)号：US09153462B2

公开(公告)日：2015-10-06

申请号：US12964097

申请日：2010-12-09

Applicant: Yu-Liang Lin ,  Weng-Jin Wu ,  Jing-Cheng Lin ,  Wen-Chih Chiou

Inventor： Yu-Liang Lin ,  Weng-Jin Wu ,  Jing-Cheng Lin ,  Wen-Chih Chiou

IPC: H01L21/687 ,  H01L21/67

CPC classification number: H01L21/67051 ,  H01L21/68728

Abstract: A device and system for thin wafer cleaning is disclosed. A preferred embodiment comprises a spin chuck having at least three holding clamps. A thin wafer with a wafer frame is mounted on the spin chuck through a tape layer. When the holding clamps are unlocked, there is no interference with the removal and placement of the wafer frame. On the other hand, when the holding clamps are locked, the holding clamps are brought into contact with the outer edge of the wafer frame so as to prevent the wafer frame from moving laterally. Furthermore, the shape of the holding clamps in a locked position is capable of preventing the wafer frame from moving vertically.

Abstract translation: 公开了用于薄晶片清洁的装置和系统。 优选实施例包括具有至少三个保持夹具的旋转卡盘。 具有晶片框架的薄晶片通过带层安装在旋转卡盘上。 当保持夹具解锁时，不会干扰晶片框架的移除和放置。 另一方面，当保持夹具被锁定时，保持夹具与晶片框架的外边缘接触，以防止晶片框架横向移动。 此外，保持夹具处于锁定位置的形状能够防止晶片框架垂直移动。

公开(公告)号：US08936966B2

公开(公告)日：2015-01-20

申请号：US13369083

申请日：2012-02-08

Applicant: Jui-Pin Hung ,  Jing-Cheng Lin

Inventor： Jui-Pin Hung ,  Jing-Cheng Lin

IPC: H01L21/00

CPC classification number: H01L24/97 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/563 ,  H01L21/568 ,  H01L21/78 ,  H01L23/3128 ,  H01L23/3185 ,  H01L24/11 ,  H01L24/19 ,  H01L24/94 ,  H01L24/96 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16145 ,  H01L2224/16235 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2224/73259 ,  H01L2224/92224 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2224/83

Abstract: Methods of packaging semiconductor devices are disclosed. In one embodiment, a packaging method for semiconductor devices includes providing a workpiece including a plurality of first dies, and coupling a plurality of second dies to the plurality of first dies. The plurality of second dies and the plurality of first dies are partially packaged and separated. Top surfaces of the second dies are coupled to a carrier, and the partially packaged plurality of second dies and plurality of first dies are fully packaged. The carrier is removed, and the fully packaged plurality of second dies and plurality of first dies are separated.

Abstract translation: 公开了封装半导体器件的方法。 在一个实施例中，用于半导体器件的封装方法包括提供包括多个第一裸片的工件，以及将多个第二裸片耦合到多个第一裸片。 多个第二模具和多个第一模具被部分地包装和分离。 第二管芯的顶表面耦合到载体，并且部分封装的多个第二管芯和多个第一管芯被完全封装。 移除载体，分离完全封装的多个第二模具和多个第一模具。

公开(公告)号：US08896136B2

公开(公告)日：2014-11-25

申请号：US12827563

申请日：2010-06-30

Applicant: Chen-Yu Tsai ,  Shih-Hui Wang ,  Chien-Ming Chiu ,  Chia-Ho Chen ,  Fang Wen Tsai ,  Weng-Jin Wu ,  Jing-Cheng Lin ,  Wen-Chih Chiou ,  Shin-Puu Jeng ,  Chen-Hua Yu

Inventor： Chen-Yu Tsai ,  Shih-Hui Wang ,  Chien-Ming Chiu ,  Chia-Ho Chen ,  Fang Wen Tsai ,  Weng-Jin Wu ,  Jing-Cheng Lin ,  Wen-Chih Chiou ,  Shin-Puu Jeng ,  Chen-Hua Yu

IPC: H01L23/544 ,  H01L29/40 ,  H01L23/48 ,  H01L23/52 ,  H01L21/76 ,  H01L21/00 ,  H01L21/4763 ,  H01L21/44 ,  H01L21/683

CPC classification number: H01L23/481 ,  H01L21/30604 ,  H01L21/6835 ,  H01L21/76831 ,  H01L21/76877 ,  H01L21/76898 ,  H01L23/544 ,  H01L2221/68327 ,  H01L2223/54426 ,  H01L2224/13

Abstract: In accordance with an embodiment, a structure comprises a substrate having a first area and a second area; a through substrate via (TSV) in the substrate penetrating the first area of the substrate; an isolation layer over the second area of the substrate, the isolation layer having a recess; and a conductive material in the recess of the isolation layer, the isolation layer being disposed between the conductive material and the substrate in the recess.

Abstract translation: 根据实施例，结构包括具有第一区域和第二区域的基板; 穿过基板的第一区域的贯穿基板通孔（TSV）; 在所述衬底的所述第二区域上方的隔离层，所述隔离层具有凹部; 以及在所述隔离层的所述凹部中的导电材料，所述隔离层设置在所述凹部中的所述导电材料和所述基板之间。

公开(公告)号：US08846499B2

公开(公告)日：2014-09-30

申请号：US12858211

申请日：2010-08-17

Applicant: Ying-Ching Shih ,  Weng-Jin Wu ,  Jing-Cheng Lin ,  Wen-Chih Chiou ,  Shin-Puu Jeng ,  Chen-Hua Yu

Inventor： Ying-Ching Shih ,  Weng-Jin Wu ,  Jing-Cheng Lin ,  Wen-Chih Chiou ,  Shin-Puu Jeng ,  Chen-Hua Yu

IPC: H01L21/30

CPC classification number: G07F17/3213 ,  B32B17/10 ,  B32B37/1207 ,  B32B37/182 ,  B32B37/185 ,  B32B2457/14 ,  H01L21/6835 ,  H01L2221/68318 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68381

Abstract: A composite carrier structure for manufacturing semiconductor devices is provided. The composite carrier structure utilizes multiple carrier substrates, e.g., glass or silicon substrates, coupled together by interposed adhesive layers. The composite carrier structure may be attached to a wafer or a die for, e.g., backside processing, such as thinning processes. In an embodiment, the composite carrier structure comprises a first carrier substrate having through-substrate vias formed therethrough. The first substrate is attached to a second substrate using an adhesive such that the adhesive may extend into the through-substrate vias.

Abstract translation: 提供了一种用于制造半导体器件的复合载体结构。 复合载体结构利用多个载体衬底，例如玻璃或硅衬底，通过插入的粘合剂层耦合在一起。 复合载体结构可以附接到晶片或模具，用于例如背面处理，例如变薄处理。 在一个实施例中，复合载体结构包括具有贯穿其中形成的贯通基板通孔的第一载体基板。 使用粘合剂将第一衬底附接到第二衬底，使得粘合剂可以延伸到贯穿衬底通孔中。

公开(公告)号：US08829676B2

公开(公告)日：2014-09-09

申请号：US13170973

申请日：2011-06-28

Applicant: Chen-Hua Yu ,  Jing-Cheng Lin ,  Nai-Wei Liu ,  Jui-Pin Hung ,  Shin-Puu Jeng

Inventor： Chen-Hua Yu ,  Jing-Cheng Lin ,  Nai-Wei Liu ,  Jui-Pin Hung ,  Shin-Puu Jeng

IPC: H01L23/485

CPC classification number: H01L21/4853 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L21/78 ,  H01L23/3128 ,  H01L23/481 ,  H01L23/49838 ,  H01L24/11 ,  H01L24/13 ,  H01L24/19 ,  H01L24/97 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05008 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/12105 ,  H01L2224/13022 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/73267 ,  H01L2224/94 ,  H01L2224/96 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/0132 ,  H01L2924/014 ,  H01L2924/181 ,  H01L2224/19 ,  H01L2224/11 ,  H01L2224/03 ,  H01L2224/05552 ,  H01L2924/00 ,  H01L2224/214

Abstract: A package includes a device die having a substrate. A molding compound contacts a sidewall of the substrate. A metal pad is over the substrate. A passivation layer has a portion covering an edge portion of the metal pad. A metal pillar is over and contacting the metal pad. A dielectric layer is over the passivation layer. A package material formed of a molding compound or a polymer is over the dielectric layer. The dielectric layer includes a bottom portion between the passivation layer and the package material, and a sidewall portion between a sidewall of the metal pillar and a sidewall of the package material. A polymer layer is over the package material, the molding compound, and the metal pillar. A post-passivation interconnect (PPI) extends into the polymer layer. A solder ball is over the PPI, and is electrically coupled to the metal pad through the PPI.

Abstract translation: 封装包括具有基板的器件裸片。 模塑料与基材的侧壁接触。 金属焊盘在基板上。 钝化层具有覆盖金属焊盘的边缘部分的部分。 金属支柱已经过去并与金属垫接触。 介电层位于钝化层的上方。 由模塑料或聚合物形成的包装材料在电介质层的上面。 电介质层包括位于钝化层和封装材料之间的底部，以及在金属柱的侧壁和封装材料的侧壁之间的侧壁部分。 聚合物层在包装材料，模塑料和金属支柱之上。 后钝化互连（PPI）延伸到聚合物层中。 焊球在PPI上方，并通过PPI电耦合到金属焊盘。

公开(公告)号：US08816495B2

公开(公告)日：2014-08-26

申请号：US13398672

申请日：2012-02-16

Applicant: Chung Yu Wang ,  Shih-Yi Syu ,  Jing-Cheng Lin

Inventor： Chung Yu Wang ,  Shih-Yi Syu ,  Jing-Cheng Lin

IPC: H01L23/34

CPC classification number: H01L23/433 ,  H01L21/563 ,  H01L23/147 ,  H01L23/367 ,  H01L23/49811 ,  H01L23/49827 ,  H01L24/97 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00

Abstract: A device includes a package component, and a die over and bonded to the package component. The die includes a substrate. A heat sink is disposed over and bonded to a back surface of the substrate through direct bonding.

Abstract translation: 一种装置包括一个封装部件和一个模具，并结合到封装部件上。 芯片包括基板。 散热器通过直接接合设置在基板的背面上并结合到基板的背面。

公开(公告)号：US08779599B2

公开(公告)日：2014-07-15

申请号：US13298126

申请日：2011-11-16

Applicant: Jing-Cheng Lin ,  Cheng-Lin Huang ,  Szu Wei Lu ,  Jui-Pin Hung ,  Shin-Puu Jeng ,  Chen-Hua Yu

Inventor： Jing-Cheng Lin ,  Cheng-Lin Huang ,  Szu Wei Lu ,  Jui-Pin Hung ,  Shin-Puu Jeng ,  Chen-Hua Yu

IPC: H01L23/538 ,  H01L21/56

CPC classification number: H01L21/561 ,  H01L21/568 ,  H01L23/16 ,  H01L23/3128 ,  H01L23/481 ,  H01L23/562 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0652 ,  H01L25/50 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06586 ,  H01L2225/06593 ,  H01L2924/10253 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2224/81 ,  H01L2924/00

Abstract: A device includes a bottom chip and an active top die bonded to the bottom chip. A dummy die is attached to the bottom chip. The dummy die is electrically insulated from the bottom chip.

Abstract translation: 一种器件包括底部芯片和结合到底部芯片的有源顶部管芯。 虚设裸片连接到底部芯片。 虚设裸片与底部芯片电绝缘。

公开(公告)号：US08759118B2

公开(公告)日：2014-06-24

申请号：US13297845

申请日：2011-11-16

Applicant: Chin-Fu Kao ,  Cheng-Lin Huang ,  Jing-Cheng Lin

Inventor： Chin-Fu Kao ,  Cheng-Lin Huang ,  Jing-Cheng Lin

IPC: H01L21/66 ,  H01L23/58

CPC classification number: H01L22/32

Abstract: A system and method for plating a contact is provided. An embodiment comprises forming protective layers over a contact and a test pad, and then selectively removing the protective layer over the contact without removing the protective layer over the test pad. With the protective layer still on the test pad, a conductive layer may be plated onto the contact without plating it onto the test pad. After the contact has been plated, the protective layer over the contact may be removed.

Abstract translation: 提供了一种用于电镀触点的系统和方法。 一个实施例包括在触点和测试垫上形成保护层，然后在触头上选择性地去除保护层，而不需要在测试垫上移除保护层。 在保护层仍在测试焊盘上的情况下，可以将导电层电镀到触点上，而不将其覆盖在测试焊盘上。 接触电镀后，触点上的保护层可以被去除。

公开(公告)号：US08722540B2

公开(公告)日：2014-05-13

申请号：US12841874

申请日：2010-07-22

Applicant: Yu-Liang Lin ,  Weng-Jin Wu ,  Jing-Cheng Lin

Inventor： Yu-Liang Lin ,  Weng-Jin Wu ,  Jing-Cheng Lin

IPC: H01L21/302 ,  H01L21/461

CPC classification number: H01L21/6835 ,  H01L2221/68327 ,  H01L2221/6834

Abstract: A method includes bonding a wafer on a carrier through an adhesive, and performing a thinning process on the wafer. After the step of performing the thinning process, a portion of the adhesive not covered by the wafer is removed, while the portion of the adhesive covered by the wafer is not removed.

Abstract translation: 一种方法包括通过粘合剂将晶片接合在载体上，并在晶片上进行稀化处理。 在进行稀化处理的步骤之后，去除未被晶片覆盖的粘合剂的一部分，同时由晶片覆盖的粘合剂部分未被除去。

公开(公告)号：US08629568B2

公开(公告)日：2014-01-14

申请号：US12847802

申请日：2010-07-30

Applicant: Yan-Fu Lin ,  Jing-Cheng Lin ,  Wen-Chih Chiou ,  Shin-Puu Jeng ,  Chen-Hua Yu

Inventor： Yan-Fu Lin ,  Jing-Cheng Lin ,  Wen-Chih Chiou ,  Shin-Puu Jeng ,  Chen-Hua Yu

IPC: H01L23/544 ,  H01L21/76

CPC classification number: H01L21/563 ,  H01L23/49838 ,  H01L23/544 ,  H01L24/11 ,  H01L24/81 ,  H01L2223/54413 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/54473 ,  H01L2223/5448 ,  H01L2223/54486 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1145 ,  H01L2224/11462 ,  H01L2224/11849 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/73204 ,  H01L2224/8113 ,  H01L2224/81132 ,  H01L2224/81191 ,  H01L2224/81815 ,  H01L2924/0001 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/351 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2924/00

Abstract: A system and method for determining underfill expansion is provided. An embodiment comprises forming cover marks along a top surface of a substrate, attaching a semiconductor substrate to the top surface of the substrate, placing an underfill material between the semiconductor substrate and the substrate, and then using the cover marks to determine the expansion of the underfill over the top surface of the substrate. Additionally, cover marks may also be formed along a top surface of the semiconductor substrate, and the cover marks on both the substrate and the semiconductor substrate may be used together as alignment marks during the alignment of the substrate and the semiconductor substrate.

Abstract translation: 提供了一种用于确定底部填充膨胀的系统和方法。 一个实施例包括沿着衬底的顶表面形成覆盖标记，将半导体衬底附接到衬底的顶表面，将底部填充材料放置在半导体衬底和衬底之间，然后使用覆盖标记来确定 底部填充在基材的顶表面上。 此外，也可以沿着半导体衬底的顶表面形成覆盖标记，并且衬底和半导体衬底上的覆盖标记可以在衬底和半导体衬底的对准期间一起用作对准标记。