公开(公告)号：US20210043504A1

公开(公告)日：2021-02-11

申请号：US16532035

申请日：2019-08-05

Applicant: Micron Technology, Inc.

Inventor： Anilkumar Chandolu ,  Christopher R. Ritchie ,  Darwin A. Clampitt ,  S M Istiaque Hossain

IPC: H01L21/768 ,  H01L27/11556 ,  H01L27/11582

Abstract: A method of forming a microelectronic device comprises forming a stack structure comprising vertically alternating insulating structures and additional insulating structures arranged in tiers. Each of the tiers individually comprises one of the insulating structures and one of the additional insulating structures. A first trench is formed to partially vertically extend through the stack structure. The first trench comprises a first portion having a first width, and a second portion at a horizontal boundary of the first portion and having a second width greater than the first width. A dielectric structure is formed within the first trench. The dielectric structure comprises a substantially void-free section proximate the horizontal boundary of the first portion of the trench. Microelectronic devices and electronic systems are also described.

公开(公告)号：US10770435B2

公开(公告)日：2020-09-08

申请号：US16459394

申请日：2019-07-01

Applicant: Micron Technology, Inc.

Inventor： Sameer S. Vadhavkar ,  Xiao Li ,  Anilkumar Chandolu

IPC: H01L23/31 ,  H01L25/065 ,  H01L23/367

Abstract: Apparatuses and methods for semiconductor die heat dissipation are described. For example, an apparatus for semiconductor die heat dissipation may include a substrate and a heat spreader. The substrate may include a thermal interface layer disposed on a surface of the substrate, such as disposed between the substrate and the heat spreader. The heat spreader may include a plurality of substrate-facing protrusions in contact with the thermal interface layer, wherein the plurality of substrate-facing protrusions are disposed at least partially through the thermal interface layer.

公开(公告)号：US10658380B2

公开(公告)日：2020-05-19

申请号：US16160146

申请日：2018-10-15

Applicant: Micron Technology, Inc.

Inventor： Matthew J. King ,  Anilkumar Chandolu ,  Indra V. Chary ,  Darwin A. Clampitt ,  Gordon Haller ,  Thomas George ,  Brett D. Lowe ,  David A. Daycock

IPC: H01L27/115 ,  H01L27/11582 ,  H01L27/1157 ,  H01L27/11526 ,  H01L27/11556 ,  H01L27/11524 ,  H01L27/11573

Abstract: In an example, a method of forming a stacked memory array includes forming a stack of alternating first and second dielectrics, forming a termination structure through the stack, the termination structure comprising a dielectric liner around a conductor, forming a set of contacts concurrently with forming the termination structure, forming a third dielectric over an upper surface of the stack and an upper surface of the termination structure, forming a first opening through the third dielectric and the stack between first and second groups of semiconductor structures so that the first opening exposes an upper surface of the conductor, and removing the conductor from the termination structure to form a second opening lined with the dielectric liner. In some examples, the dielectric liner can include a rectangular or a triangular tab or a pair of prongs that can have a rectangular profile or that can be tapered.

公开(公告)号：US20190206766A1

公开(公告)日：2019-07-04

申请号：US15858501

申请日：2017-12-29

Applicant: Micron Technology, Inc.

Inventor： Anilkumar Chandolu ,  Wayne H. Huang ,  Sameer S. Vadhavkar

IPC: H01L23/48 ,  H01L21/683 ,  H01L23/00 ,  H01L25/065

CPC classification number: H01L23/481 ,  H01L21/6835 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L25/0657 ,  H01L2224/0346 ,  H01L2224/0401 ,  H01L2224/05025 ,  H01L2224/05568 ,  H01L2224/1146 ,  H01L2224/13006 ,  H01L2224/13023 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/06541

Abstract: Semiconductor devices having one or more vias filled with an electrically conductive material are disclosed herein. In one embodiment, a semiconductor device includes a semiconductor substrate having a first side, a plurality of circuit elements proximate to the first side, and a second side opposite the first side. A via can extend between the first and second sides, and a conductive material in the via can extend beyond the second side of the substrate to define a projecting portion of the conductive material. The semiconductor device can have a tall conductive pillar formed over the second side and surrounding the projecting portion of the conductive material, and a short conductive pad formed over the first side and electrically coupled to the conductive material in the via.

公开(公告)号：US10276529B2

公开(公告)日：2019-04-30

申请号：US15687691

申请日：2017-08-28

Applicant: Micron Technology, Inc.

Inventor： Anilkumar Chandolu ,  Kenneth N. Hagen

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/00 ,  H01L25/065 ,  H01L25/00 ,  H01L21/66

Abstract: A method of forming a conductive material on a semiconductor device. The method comprises removing at least a portion of a conductive pad within an aperture in a dielectric material over a substrate. The method further comprises forming a seed material at least within a bottom of the aperture and over the dielectric material, forming a protective material over the seed material within the aperture, and forming a conductive pillar in contact with the seed material through an opening in the protective material over surfaces of the seed material within the aperture. A method of forming an electrical connection between adjacent semiconductor devices, and a semiconductor device, are also described.

公开(公告)号：US09818728B2

公开(公告)日：2017-11-14

申请号：US15162209

申请日：2016-05-23

Applicant: Micron Technology, Inc.

Inventor： Anilkumar Chandolu

IPC: H01L23/49 ,  H01L25/065 ,  H01L23/00 ,  H01L25/18 ,  H01L25/00 ,  H01L21/768 ,  H01L23/48 ,  H01L21/56 ,  H01L23/367 ,  H01L23/31 ,  H01L23/498

CPC classification number: H01L25/0657 ,  H01L21/56 ,  H01L21/76898 ,  H01L23/3128 ,  H01L23/3675 ,  H01L23/481 ,  H01L23/49816 ,  H01L24/02 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L24/81 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/02371 ,  H01L2224/02372 ,  H01L2224/0239 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/05647 ,  H01L2224/1145 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/13024 ,  H01L2224/13083 ,  H01L2224/13084 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/1329 ,  H01L2224/133 ,  H01L2224/13565 ,  H01L2224/13647 ,  H01L2224/1411 ,  H01L2224/14181 ,  H01L2224/16113 ,  H01L2224/16145 ,  H01L2224/17107 ,  H01L2224/17181 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73253 ,  H01L2224/81193 ,  H01L2224/81815 ,  H01L2224/83424 ,  H01L2224/83447 ,  H01L2224/83455 ,  H01L2224/83487 ,  H01L2224/8385 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06544 ,  H01L2225/06555 ,  H01L2225/06582 ,  H01L2225/06589 ,  H01L2924/10253 ,  H01L2924/1033 ,  H01L2924/14 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/15311 ,  H01L2924/16235 ,  H01L2924/16251 ,  H01L2924/3512 ,  H01L2924/00014 ,  H01L2924/05032 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/01047

Abstract: Semiconductor die assemblies having interconnect structures with redundant electrical connectors are disclosed herein. In one embodiment, a semiconductor die assembly includes a first semiconductor die, a second semiconductor die, and an interconnect structure between the first and the second semiconductor dies. The interconnect structure includes a first conductive film coupled to the first semiconductor die and a second conductive film coupled to the second semiconductor die. The interconnect structure further includes a plurality of redundant electrical connectors extending between the first and second conductive films and electrically coupled to one another via the first conductive film.

公开(公告)号：US09768134B2

公开(公告)日：2017-09-19

申请号：US14608466

申请日：2015-01-29

Applicant: Micron Technology, Inc.

Inventor： Anilkumar Chandolu ,  Kenneth N. Hagen

IPC: H01L21/4763 ,  H01L23/00 ,  H01L25/065 ,  H01L25/00 ,  H01L21/66

CPC classification number: H01L24/13 ,  H01L22/14 ,  H01L22/20 ,  H01L24/02 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L24/94 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/02215 ,  H01L2224/0239 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/03614 ,  H01L2224/0362 ,  H01L2224/03914 ,  H01L2224/03916 ,  H01L2224/03921 ,  H01L2224/0401 ,  H01L2224/05017 ,  H01L2224/05018 ,  H01L2224/05025 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05187 ,  H01L2224/05558 ,  H01L2224/05565 ,  H01L2224/0557 ,  H01L2224/05583 ,  H01L2224/05647 ,  H01L2224/05687 ,  H01L2224/05688 ,  H01L2224/0569 ,  H01L2224/1132 ,  H01L2224/11424 ,  H01L2224/1145 ,  H01L2224/11452 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/1147 ,  H01L2224/11612 ,  H01L2224/11614 ,  H01L2224/11622 ,  H01L2224/11632 ,  H01L2224/13021 ,  H01L2224/13025 ,  H01L2224/13147 ,  H01L2224/16146 ,  H01L2224/2919 ,  H01L2224/29191 ,  H01L2224/2929 ,  H01L2224/29387 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2224/81 ,  H01L2224/81203 ,  H01L2224/81424 ,  H01L2224/81447 ,  H01L2224/83 ,  H01L2224/83102 ,  H01L2224/83104 ,  H01L2224/83862 ,  H01L2224/8388 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06596 ,  H01L2924/00012 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0474 ,  H01L2924/0503 ,  H01L2924/05994 ,  H01L2924/0715 ,  H01L2924/00014 ,  H01L2924/04941 ,  H01L2924/07025 ,  H01L2924/05442 ,  H01L2924/05042 ,  H01L2924/06 ,  H01L2924/0665 ,  H01L2924/05432

Abstract: A method of forming a conductive material on a semiconductor device. The method comprises removing at least a portion of a conductive pad within an aperture in a dielectric material over a substrate. The method further comprises forming a seed material at least within a bottom of the aperture and over the dielectric material, forming a protective material over the seed material within the aperture, and forming a conductive pillar in contact with the seed material through an opening in the protective material over surfaces of the seed material within the aperture. A method of forming an electrical connection between adjacent semiconductor devices, and a semiconductor device, are also described.

公开(公告)号：US20160268235A1

公开(公告)日：2016-09-15

申请号：US15162209

申请日：2016-05-23

Applicant: Micron Technology, Inc.

Inventor： Anilkumar Chandolu

IPC: H01L25/065 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L21/56 ,  H01L21/76898 ,  H01L23/3128 ,  H01L23/3675 ,  H01L23/481 ,  H01L23/49816 ,  H01L24/02 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L24/81 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/02371 ,  H01L2224/02372 ,  H01L2224/0239 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/05647 ,  H01L2224/1145 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/13024 ,  H01L2224/13083 ,  H01L2224/13084 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/1329 ,  H01L2224/133 ,  H01L2224/13565 ,  H01L2224/13647 ,  H01L2224/1411 ,  H01L2224/14181 ,  H01L2224/16113 ,  H01L2224/16145 ,  H01L2224/17107 ,  H01L2224/17181 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73253 ,  H01L2224/81193 ,  H01L2224/81815 ,  H01L2224/83424 ,  H01L2224/83447 ,  H01L2224/83455 ,  H01L2224/83487 ,  H01L2224/8385 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06544 ,  H01L2225/06555 ,  H01L2225/06582 ,  H01L2225/06589 ,  H01L2924/10253 ,  H01L2924/1033 ,  H01L2924/14 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/15311 ,  H01L2924/16235 ,  H01L2924/16251 ,  H01L2924/3512 ,  H01L2924/00014 ,  H01L2924/05032 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/01047

Abstract: Semiconductor die assemblies having interconnect structures with redundant electrical connectors are disclosed herein. In one embodiment, a semiconductor die assembly includes a first semiconductor die, a second semiconductor die, and an interconnect structure between the first and the second semiconductor dies. The interconnect structure includes a first conductive film coupled to the first semiconductor die and a second conductive film coupled to the second semiconductor die. The interconnect structure further includes a plurality of redundant electrical connectors extending between the first and second conductive films and electrically coupled to one another via the first conductive film.

公开(公告)号：US09356009B2

公开(公告)日：2016-05-31

申请号：US14287418

申请日：2014-05-27

Applicant: Micron Technology, Inc.

Inventor： Anilkumar Chandolu

IPC: H01L23/02 ,  H01L25/18 ,  H01L23/367 ,  H01L23/00 ,  H01L25/065 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L21/56 ,  H01L21/76898 ,  H01L23/3128 ,  H01L23/3675 ,  H01L23/481 ,  H01L23/49816 ,  H01L24/02 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L24/81 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/02371 ,  H01L2224/02372 ,  H01L2224/0239 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/05647 ,  H01L2224/1145 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/13024 ,  H01L2224/13083 ,  H01L2224/13084 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/1329 ,  H01L2224/133 ,  H01L2224/13565 ,  H01L2224/13647 ,  H01L2224/1411 ,  H01L2224/14181 ,  H01L2224/16113 ,  H01L2224/16145 ,  H01L2224/17107 ,  H01L2224/17181 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73253 ,  H01L2224/81193 ,  H01L2224/81815 ,  H01L2224/83424 ,  H01L2224/83447 ,  H01L2224/83455 ,  H01L2224/83487 ,  H01L2224/8385 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06544 ,  H01L2225/06555 ,  H01L2225/06582 ,  H01L2225/06589 ,  H01L2924/10253 ,  H01L2924/1033 ,  H01L2924/14 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/15311 ,  H01L2924/16235 ,  H01L2924/16251 ,  H01L2924/3512 ,  H01L2924/00014 ,  H01L2924/05032 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/01047

Abstract: Semiconductor die assemblies having interconnect structures with redundant electrical connectors are disclosed herein. In one embodiment, a semiconductor die assembly includes a first semiconductor die, a second semiconductor die, and an interconnect structure between the first and the second semiconductor dies. The interconnect structure includes a first conductive film coupled to the first semiconductor die and a second conductive film coupled to the second semiconductor die. The interconnect structure further includes a plurality of redundant electrical connectors extending between the first and second conductive films and electrically coupled to one another via the first conductive film.

Abstract translation: 本文公开了具有冗余电连接器的互连结构的半导体管芯组件。 在一个实施例中，半导体管芯组件包括第一半导体管芯，第二半导体管芯和第一和第二半导体管芯之间的互连结构。 互连结构包括耦合到第一半导体管芯的第一导电膜和耦合到第二半导体管芯的第二导电膜。 互连结构还包括在第一和第二导电膜之间延伸并经由第一导电膜彼此电耦合的多个冗余电连接器。

公开(公告)号：US20250096042A1

公开(公告)日：2025-03-20

申请号：US18970741

申请日：2024-12-05

Applicant: Micron Technology, Inc.

Inventor： Anilkumar Chandolu ,  Indra V. Chary

IPC: H01L21/768 ,  H01L23/535 ,  H10B41/27 ,  H10B43/27

Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming a stack comprising vertically-alternating first tiers and second tiers. Horizontally-elongated trenches are formed into the stack to form laterally-spaced memory-block regions. The memory-block regions comprise part of a memory-plane region. A pair of elevationally-extending walls are formed that are laterally-spaced relative one another and that are individually horizontally-longitudinally-elongated. The pair of walls are one of (a) or (b), where: (a): in the memory-plane region laterally-between immediately-laterally-adjacent of the memory-block regions; and (b): in a region that is edge-of-plane relative to the memory-plane region. Through the horizontally-elongated trenches and after forming the pair of walls, sacrificial material that is in the first tiers is isotropically etching away and replaced with conducting material of individual conducting lines. Other embodiments, including structure independent of method, are disclosed.